diff options
Diffstat (limited to 'arch/m32r')
| -rw-r--r-- | arch/m32r/Kconfig | 1 | ||||
| -rw-r--r-- | arch/m32r/kernel/irq.c | 45 | ||||
| -rw-r--r-- | arch/m32r/platforms/m32104ut/setup.c | 8 | ||||
| -rw-r--r-- | arch/m32r/platforms/m32700ut/setup.c | 28 | ||||
| -rw-r--r-- | arch/m32r/platforms/mappi/setup.c | 16 | ||||
| -rw-r--r-- | arch/m32r/platforms/mappi2/setup.c | 20 | ||||
| -rw-r--r-- | arch/m32r/platforms/mappi3/setup.c | 20 | ||||
| -rw-r--r-- | arch/m32r/platforms/oaks32r/setup.c | 12 | ||||
| -rw-r--r-- | arch/m32r/platforms/opsput/setup.c | 28 | ||||
| -rw-r--r-- | arch/m32r/platforms/usrv/setup.c | 18 |
10 files changed, 76 insertions, 120 deletions
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 62afe23c9a49..b28d0908a402 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -10,6 +10,7 @@ config M32R select HAVE_GENERIC_HARDIRQS select GENERIC_HARDIRQS_NO_DEPRECATED select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW config SBUS bool diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 76eaf3883fbd..c7272b894283 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c @@ -18,55 +18,10 @@ #include <linux/kernel_stat.h> #include <linux/interrupt.h> -#include <linux/seq_file.h> #include <linux/module.h> #include <asm/uaccess.h> /* - * Generic, controller-independent functions: - */ - -int show_interrupts(struct seq_file *p, void *v) -{ - int i = *(loff_t *) v, j; - struct irqaction * action; - unsigned long flags; - - if (i == 0) { - seq_printf(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ",j); - seq_putc(p, '\n'); - } - - if (i < NR_IRQS) { - struct irq_desc *desc = irq_to_desc(i); - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto skip; - seq_printf(p, "%3d: ",i); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(i)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#endif - seq_printf(p, " %14s", desc->irq_data.chip->name); - seq_printf(p, " %s", action->name); - - for (action=action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -skip: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } - return 0; -} - -/* * do_IRQ handles all normal device IRQs (the special * SMP cross-CPU interrupts have their own specific * handlers). diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 4a693d02c1e1..34671d32cefc 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -76,7 +76,7 @@ void __init init_IRQ(void) #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, handle_level_irq); /* "H" level sense */ cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; @@ -84,20 +84,20 @@ void __init init_IRQ(void) #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_S); diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 2074bcc841eb..1053e1cb7401 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -259,76 +259,76 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, + irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32700ut_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_m32700ut_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); @@ -349,7 +349,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, + irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type, handle_level_irq); lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ @@ -366,7 +366,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_m32700ut_irq(M32R_IRQ_INT3); diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index cdd8c4574027..35130ac3f8d1 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -75,39 +75,39 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT0 : LAN controller (RTL8019AS) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; disable_mappi_irq(M32R_IRQ_INT0); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); @@ -115,13 +115,13 @@ void __init init_IRQ(void) #if defined(CONFIG_M32R_PCC) /* INT1 : pccard0 interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT1); /* INT2 : pccard1 interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT2); diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index 9117c30ea365..f3ed6b60a5f8 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -76,38 +76,38 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi2_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_S); @@ -115,27 +115,27 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi2_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* ICUCR40: CFC IREQ */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi2_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi2_irq(PLD_IRQ_CFC_INSERT); /* ICUCR42: CFC Eject */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(PLD_IRQ_CFC_EJECT); diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index b44f5ded2bbe..2408e356ad10 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -75,38 +75,38 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi3_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_S); @@ -114,21 +114,21 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi3_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* CFC IREQ */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi3_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert & eject */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi3_irq(PLD_IRQ_CFC_INSERT); @@ -136,7 +136,7 @@ void __init init_IRQ(void) #endif /* CONFIG_M32R_CFC */ /* IDE IREQ */ - set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, + irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, handle_level_irq); icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(PLD_IRQ_IDEIREQ); diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index 19a02db7b818..83b46b067a17 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -74,39 +74,39 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 12731547e8bf..32660705f5fd 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -259,76 +259,76 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, + irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); @@ -349,7 +349,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, + irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type, handle_level_irq); lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); @@ -365,7 +365,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index f3cff26d6e74..0c7a1e8c77b0 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -138,32 +138,32 @@ void __init init_IRQ(void) once++; /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #if defined(CONFIG_SERIAL_M32R_SIO) /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); @@ -171,7 +171,7 @@ void __init init_IRQ(void) /* INT#67-#71: CFC#0 IREQ on PLD */ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { - set_irq_chip_and_handler(PLD_IRQ_CF0 + i, + irq_set_chip_and_handler(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr @@ -181,14 +181,14 @@ void __init init_IRQ(void) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* INT#76: 16552D#0 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART0); /* INT#77: 16552D#1 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ @@ -197,7 +197,7 @@ void __init init_IRQ(void) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) /* INT#80: AK4524 IREQ on PLD */ - set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, + irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |