diff options
Diffstat (limited to 'arch/mips/netlogic/common')
| -rw-r--r-- | arch/mips/netlogic/common/irq.c | 43 | ||||
| -rw-r--r-- | arch/mips/netlogic/common/smp.c | 8 | ||||
| -rw-r--r-- | arch/mips/netlogic/common/smpboot.S | 20 | ||||
| -rw-r--r-- | arch/mips/netlogic/common/time.c | 56 |
4 files changed, 90 insertions, 37 deletions
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c index 00dcc7a2bc5a..9f84c60bf535 100644 --- a/arch/mips/netlogic/common/irq.c +++ b/arch/mips/netlogic/common/irq.c @@ -69,7 +69,7 @@ #else #define SMP_IRQ_MASK 0 #endif -#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \ +#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \ (1ull << IRQ_FMN)) struct nlm_pic_irq { @@ -105,21 +105,23 @@ static void xlp_pic_disable(struct irq_data *d) static void xlp_pic_mask_ack(struct irq_data *d) { struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); - uint64_t mask = 1ull << pd->picirq; - write_c0_eirr(mask); /* ack by writing EIRR */ + clear_c0_eimr(pd->picirq); + ack_c0_eirr(pd->picirq); } static void xlp_pic_unmask(struct irq_data *d) { struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); - if (!pd) - return; + BUG_ON(!pd); if (pd->extra_ack) pd->extra_ack(d); + /* re-enable the intr on this cpu */ + set_c0_eimr(pd->picirq); + /* Ack is a single write, no need to lock */ nlm_pic_ack(pd->node->picbase, pd->irt); } @@ -134,32 +136,17 @@ static struct irq_chip xlp_pic = { static void cpuintr_disable(struct irq_data *d) { - uint64_t eimr; - uint64_t mask = 1ull << d->irq; - - eimr = read_c0_eimr(); - write_c0_eimr(eimr & ~mask); + clear_c0_eimr(d->irq); } static void cpuintr_enable(struct irq_data *d) { - uint64_t eimr; - uint64_t mask = 1ull << d->irq; - - eimr = read_c0_eimr(); - write_c0_eimr(eimr | mask); + set_c0_eimr(d->irq); } static void cpuintr_ack(struct irq_data *d) { - uint64_t mask = 1ull << d->irq; - - write_c0_eirr(mask); -} - -static void cpuintr_nop(struct irq_data *d) -{ - WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq); + ack_c0_eirr(d->irq); } /* @@ -170,9 +157,9 @@ struct irq_chip nlm_cpu_intr = { .name = "XLP-CPU-INTR", .irq_enable = cpuintr_enable, .irq_disable = cpuintr_disable, - .irq_mask = cpuintr_nop, - .irq_ack = cpuintr_nop, - .irq_eoi = cpuintr_ack, + .irq_mask = cpuintr_disable, + .irq_ack = cpuintr_ack, + .irq_eoi = cpuintr_enable, }; static void __init nlm_init_percpu_irqs(void) @@ -230,7 +217,7 @@ static void nlm_init_node_irqs(int node) nlm_setup_pic_irq(node, i, i, irt); /* set interrupts to first cpu in node */ nlm_pic_init_irt(nodep->picbase, irt, i, - node * NLM_CPUS_PER_NODE); + node * NLM_CPUS_PER_NODE, 0); irqmask |= (1ull << i); } nodep->irqmask = irqmask; @@ -265,7 +252,7 @@ asmlinkage void plat_irq_dispatch(void) int i, node; node = nlm_nodeid(); - eirr = read_c0_eirr() & read_c0_eimr(); + eirr = read_c0_eirr_and_eimr(); i = __ilog2_u64(eirr); if (i == -1) diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index a080d9ee3cd7..2bb95dcfe20a 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -84,15 +84,19 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) /* IRQ_IPI_SMP_FUNCTION Handler */ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) { - write_c0_eirr(1ull << irq); + clear_c0_eimr(irq); + ack_c0_eirr(irq); smp_call_function_interrupt(); + set_c0_eimr(irq); } /* IRQ_IPI_SMP_RESCHEDULE handler */ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) { - write_c0_eirr(1ull << irq); + clear_c0_eimr(irq); + ack_c0_eirr(irq); scheduler_ipi(); + set_c0_eimr(irq); } /* diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S index a0b74874bebe..026517488584 100644 --- a/arch/mips/netlogic/common/smpboot.S +++ b/arch/mips/netlogic/common/smpboot.S @@ -49,12 +49,12 @@ #include <asm/netlogic/xlp-hal/sys.h> #include <asm/netlogic/xlp-hal/cpucontrol.h> -#define CP0_EBASE $15 +#define CP0_EBASE $15 #define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ SYS_CPU_NONCOHERENT_MODE * 4 -#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ +#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ /* Enable XLP features and workarounds in the LSU */ .macro xlp_config_lsu @@ -69,6 +69,12 @@ #endif mtcr t1, t0 + li t0, ICU_DEFEATURE + mfcr t1, t0 + ori t1, 0x1000 /* Enable Icache partitioning */ + mtcr t1, t0 + + #ifdef XLP_AX_WORKAROUND li t0, SCHED_DEFEATURE lui t1, 0x0100 /* Disable BRU accepting ALU ops */ @@ -85,7 +91,7 @@ li t0, LSU_DEBUG_DATA0 li t1, LSU_DEBUG_ADDR li t2, 0 /* index */ - li t3, 0x1000 /* loop count */ + li t3, 0x1000 /* loop count */ 1: sll v0, t2, 5 mtcr zero, t0 @@ -134,7 +140,7 @@ FEXPORT(nlm_reset_entry) and k1, k0, k1 beqz k1, 1f /* go to real reset entry */ nop - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ + li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ ld k0, BOOT_NMI_HANDLER(k1) jr k0 nop @@ -235,7 +241,7 @@ EXPORT(nlm_reset_entry_end) FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ xlp_config_lsu - dmtc0 sp, $4, 2 /* SP saved in UserLocal */ + dmtc0 sp, $4, 2 /* SP saved in UserLocal */ SAVE_ALL sync /* find the location to which nlm_boot_siblings was relocated */ @@ -301,13 +307,13 @@ NESTED(nlm_rmiboot_preboot, 16, sp) */ li t0, 0x400 mfcr t1, t0 - li t2, 6 /* XLR thread mode mask */ + li t2, 6 /* XLR thread mode mask */ nor t3, t2, zero and t2, t1, t2 /* t2 - current thread mode */ li v0, CKSEG1ADDR(RESET_DATA_PHYS) lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */ sll v1, 1 - beq v1, t2, 1f /* same as request value */ + beq v1, t2, 1f /* same as request value */ nop /* nothing to do */ and t2, t1, t3 /* mask out old thread mode */ diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c index bd3e498157ff..5c56555380bb 100644 --- a/arch/mips/netlogic/common/time.c +++ b/arch/mips/netlogic/common/time.c @@ -35,17 +35,73 @@ #include <linux/init.h> #include <asm/time.h> +#include <asm/cpu-features.h> + #include <asm/netlogic/interrupt.h> #include <asm/netlogic/common.h> +#include <asm/netlogic/haldefs.h> +#include <asm/netlogic/common.h> + +#if defined(CONFIG_CPU_XLP) +#include <asm/netlogic/xlp-hal/iomap.h> +#include <asm/netlogic/xlp-hal/xlp.h> +#include <asm/netlogic/xlp-hal/pic.h> +#elif defined(CONFIG_CPU_XLR) +#include <asm/netlogic/xlr/iomap.h> +#include <asm/netlogic/xlr/pic.h> +#include <asm/netlogic/xlr/xlr.h> +#else +#error "Unknown CPU" +#endif unsigned int __cpuinit get_c0_compare_int(void) { return IRQ_TIMER; } +static cycle_t nlm_get_pic_timer(struct clocksource *cs) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + return ~nlm_pic_read_timer(picbase, PIC_CLOCK_TIMER); +} + +static cycle_t nlm_get_pic_timer32(struct clocksource *cs) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + return ~nlm_pic_read_timer32(picbase, PIC_CLOCK_TIMER); +} + +static struct clocksource csrc_pic = { + .name = "PIC", + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void nlm_init_pic_timer(void) +{ + uint64_t picbase = nlm_get_node(0)->picbase; + + nlm_pic_set_timer(picbase, PIC_CLOCK_TIMER, ~0ULL, 0, 0); + if (current_cpu_data.cputype == CPU_XLR) { + csrc_pic.mask = CLOCKSOURCE_MASK(32); + csrc_pic.read = nlm_get_pic_timer32; + } else { + csrc_pic.mask = CLOCKSOURCE_MASK(64); + csrc_pic.read = nlm_get_pic_timer; + } + csrc_pic.rating = 1000; + clocksource_register_hz(&csrc_pic, PIC_CLK_HZ); +} + void __init plat_time_init(void) { + nlm_init_pic_timer(); mips_hpt_frequency = nlm_get_cpu_frequency(); + if (current_cpu_type() == CPU_XLR) + preset_lpj = mips_hpt_frequency / (3 * HZ); + else + preset_lpj = mips_hpt_frequency / (2 * HZ); pr_info("MIPS counter frequency [%ld]\n", (unsigned long)mips_hpt_frequency); } |