diff options
Diffstat (limited to 'arch/powerpc/platforms/85xx')
| -rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_mds.c | 27 | ||||
| -rw-r--r-- | arch/powerpc/platforms/85xx/socrates_fpga_pic.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/platforms/85xx/stx_gp3.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/platforms/85xx/xes_mpc85xx.c | 4 |
4 files changed, 31 insertions, 4 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index cc29c0f5300d..f0684c8ac960 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -237,6 +237,8 @@ static void __init mpc85xx_mds_setup_arch(void) } else if (machine_is(mpc8569_mds)) { #define BCSR7_UCC12_GETHnRST (0x1 << 2) #define BCSR8_UEM_MARVELL_RST (0x1 << 1) +#define BCSR_UCC_RGMII (0x1 << 6) +#define BCSR_UCC_RTBI (0x1 << 5) /* * U-Boot mangles interrupt polarity for Marvell PHYs, * so reset built-in and UEM Marvell PHYs, this puts @@ -247,6 +249,28 @@ static void __init mpc85xx_mds_setup_arch(void) setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); + + for (np = NULL; (np = of_find_compatible_node(np, + "network", + "ucc_geth")) != NULL;) { + const unsigned int *prop; + int ucc_num; + + prop = of_get_property(np, "cell-index", NULL); + if (prop == NULL) + continue; + + ucc_num = *prop - 1; + + prop = of_get_property(np, "phy-connection-type", NULL); + if (prop == NULL) + continue; + + if (strcmp("rtbi", (const char *)prop) == 0) + clrsetbits_8(&bcsr_regs[7 + ucc_num], + BCSR_UCC_RGMII, BCSR_UCC_RTBI); + } + } iounmap(bcsr_regs); } @@ -302,11 +326,14 @@ static struct of_device_id mpc85xx_ids[] = { { .compatible = "gianfar", }, { .compatible = "fsl,rapidio-delta", }, { .compatible = "fsl,mpc8548-guts", }, + { .compatible = "gpio-leds", }, {}, }; static int __init mpc85xx_publish_devices(void) { + if (machine_is(mpc8568_mds)) + simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio"); if (machine_is(mpc8569_mds)) simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index e5da5f62b24a..42e87f08aa01 100644 --- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c @@ -232,7 +232,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq, } static struct irq_chip socrates_fpga_pic_chip = { - .name = " FPGA-PIC ", + .name = "FPGA-PIC", .ack = socrates_fpga_pic_ack, .mask = socrates_fpga_pic_mask, .mask_ack = socrates_fpga_pic_mask_ack, diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c index f559918f3c6f..bc33d1859ae7 100644 --- a/arch/powerpc/platforms/85xx/stx_gp3.c +++ b/arch/powerpc/platforms/85xx/stx_gp3.c @@ -134,7 +134,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m) pvid = mfspr(SPRN_PVR); svid = mfspr(SPRN_SVR); - seq_printf(m, "Vendor\t\t: RPC Electronics STx \n"); + seq_printf(m, "Vendor\t\t: RPC Electronics STx\n"); seq_printf(m, "PVR\t\t: 0x%x\n", pvid); seq_printf(m, "SVR\t\t: 0x%x\n", svid); diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c index 1b426050a2f9..0125604d096e 100644 --- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c @@ -80,8 +80,8 @@ static void xes_mpc85xx_configure_l2(void __iomem *l2_base) printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; - if (machine_is_compatible("MPC8540") || - machine_is_compatible("MPC8560")) + if (of_machine_is_compatible("MPC8540") || + of_machine_is_compatible("MPC8560")) /* * Assume L2 SRAM is used fully for cache, so set * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). |