diff options
Diffstat (limited to 'arch/powerpc/platforms/8xx')
| -rw-r--r-- | arch/powerpc/platforms/8xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/powerpc/platforms/8xx/mpc86xads.h | 95 | ||||
| -rw-r--r-- | arch/powerpc/platforms/8xx/mpc86xads_setup.c | 301 |
3 files changed, 397 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile index 1b59ffa92521..5e2dae3afd2f 100644 --- a/arch/powerpc/platforms/8xx/Makefile +++ b/arch/powerpc/platforms/8xx/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_PPC_8xx) += m8xx_setup.o obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o +obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o diff --git a/arch/powerpc/platforms/8xx/mpc86xads.h b/arch/powerpc/platforms/8xx/mpc86xads.h new file mode 100644 index 000000000000..b5d19dd0619c --- /dev/null +++ b/arch/powerpc/platforms/8xx/mpc86xads.h @@ -0,0 +1,95 @@ +/* + * A collection of structures, addresses, and values associated with + * the Freescale MPC86xADS board. + * Copied from the FADS stuff. + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_MPC86XADS_H__ +#define __ASM_MPC86XADS_H__ + +#include <asm/ppcboot.h> +#include <sysdev/fsl_soc.h> + +/* U-Boot maps BCSR to 0xff080000 */ +#define BCSR_ADDR ((uint)0xff080000) +#define BCSR_SIZE ((uint)32) +#define BCSR0 ((uint)(BCSR_ADDR + 0x00)) +#define BCSR1 ((uint)(BCSR_ADDR + 0x04)) +#define BCSR2 ((uint)(BCSR_ADDR + 0x08)) +#define BCSR3 ((uint)(BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint)(BCSR_ADDR + 0x10)) + +#define CFG_PHYDEV_ADDR ((uint)0xff0a0000) +#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300)) + +#define IMAP_ADDR (get_immrbase()) +#define IMAP_SIZE ((uint)(64 * 1024)) + +#define MPC8xx_CPM_OFFSET (0x9c0) +#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) +#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver + +#define PCMCIA_MEM_ADDR (uint)0xff020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +/* Bits of interest in the BCSRs. + */ +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDAEN ((uint)0x10000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP0 ((uint)0x00200000) +#define BCSR1_PCCVPP1 ((uint)0x00100000) +#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) +#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1) + +#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/ +#define BCSR4_USB_LO_SPD ((uint)0x04000000) +#define BCSR4_USB_VCC ((uint)0x02000000) +#define BCSR4_USB_FULL_SPD ((uint)0x00040000) +#define BCSR4_USB_EN ((uint)0x00020000) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + +/* Interrupt level assignments */ +#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */ +#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */ +#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */ + +/* We don't use the 8259 */ +#define NR_8259_INTS 0 + +/* CPM Ethernet through SCC1 */ +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00001000) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002c) + +#endif /* __ASM_MPC86XADS_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c new file mode 100644 index 000000000000..ef52ce701b0e --- /dev/null +++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c @@ -0,0 +1,301 @@ +/*arch/ppc/platforms/mpc86xads-setup.c + * + * Platform setup for the Freescale mpc86xads board + * + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/root_dev.h> + +#include <linux/fs_enet_pd.h> +#include <linux/fs_uart_pd.h> +#include <linux/mii.h> + +#include <asm/delay.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/page.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/ppcboot.h> +#include <asm/mpc8xx.h> +#include <asm/8xx_immap.h> +#include <asm/commproc.h> +#include <asm/fs_pd.h> +#include <asm/prom.h> + +extern void cpm_reset(void); +extern void mpc8xx_show_cpuinfo(struct seq_file*); +extern void mpc8xx_restart(char *cmd); +extern void mpc8xx_calibrate_decr(void); +extern int mpc8xx_set_rtc_time(struct rtc_time *tm); +extern void mpc8xx_get_rtc_time(struct rtc_time *tm); +extern void m8xx_pic_init(void); +extern unsigned int mpc8xx_get_irq(void); + +static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi); +static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi); +static void init_scc1_ioports(struct fs_platform_info* ptr); + +void __init mpc86xads_board_setup(void) +{ + cpm8xx_t *cp; + unsigned int *bcsr_io; + u8 tmpval8; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + cp = (cpm8xx_t *)immr_map(im_cpm); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + clrbits32(bcsr_io, BCSR1_RS232EN_1); + clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */ + tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX); + out_8(&(cp->cp_smc[0].smc_smcm), tmpval8); + clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); +#else + setbits32(bcsr_io,BCSR1_RS232EN_1); + out_be16(&cp->cp_smc[0].smc_smcmr, 0); + out_8(&cp->cp_smc[0].smc_smce, 0); +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + clrbits32(bcsr_io,BCSR1_RS232EN_2); + clrbits32(&cp->cp_simode, 0xe0000000 >> 1); + setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */ + tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX); + out_8(&(cp->cp_smc[1].smc_smcm), tmpval8); + clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN); + + init_smc2_uart_ioports(0); +#else + setbits32(bcsr_io,BCSR1_RS232EN_2); + out_be16(&cp->cp_smc[1].smc_smcmr, 0); + out_8(&cp->cp_smc[1].smc_smce, 0); +#endif + immr_unmap(cp); + iounmap(bcsr_io); +} + + +static void init_fec1_ioports(struct fs_platform_info* ptr) +{ + iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport); + + /* configure FEC1 pins */ + + setbits16(&io_port->iop_pdpar, 0x1fff); + setbits16(&io_port->iop_pddir, 0x1fff); + + immr_unmap(io_port); +} + +void init_fec_ioports(struct fs_platform_info *fpi) +{ + int fec_no = fs_get_fec_index(fpi->fs_no); + + switch (fec_no) { + case 0: + init_fec1_ioports(fpi); + break; + default: + printk(KERN_ERR "init_fec_ioports: invalid FEC number\n"); + return; + } +} + +static void init_scc1_ioports(struct fs_platform_info* fpi) +{ + unsigned *bcsr_io; + iop8xx_t *io_port; + cpm8xx_t *cp; + + bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); + io_port = (iop8xx_t *)immr_map(im_ioport); + cp = (cpm8xx_t *)immr_map(im_cpm); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } + + /* Configure port A pins for Txd and Rxd. + */ + setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&io_port->iop_paodr, PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port A for TCLK and RCLK. + */ + setbits16(&io_port->iop_papar, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits16(&io_port->iop_padir, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits32(&cp->cp_pbpar, PB_ENET_TENA); + clrbits32(&cp->cp_pbdir, PB_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&cp->cp_sicr, SICR_ENET_MASK); + setbits32(&cp->cp_sicr, SICR_ENET_CLKRT); + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&cp->cp_pbpar, PB_ENET_TENA); + setbits32(&cp->cp_pbdir, PB_ENET_TENA); + + clrbits32(bcsr_io+1, BCSR1_ETHEN); + iounmap(bcsr_io); + immr_unmap(cp); + immr_unmap(io_port); +} + +void init_scc_ioports(struct fs_platform_info *fpi) +{ + int scc_no = fs_get_scc_index(fpi->fs_no); + + switch (scc_no) { + case 0: + init_scc1_ioports(fpi); + break; + default: + printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); + return; + } +} + + + +static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr) +{ + unsigned *bcsr_io; + cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); + + setbits32(&cp->cp_pbpar, 0x000000c0); + clrbits32(&cp->cp_pbdir, 0x000000c0); + clrbits16(&cp->cp_pbodr, 0x00c0); + immr_unmap(cp); + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } + clrbits32(bcsr_io,BCSR1_RS232EN_1); + iounmap(bcsr_io); +} + +static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi) +{ + unsigned *bcsr_io; + cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); + + setbits32(&cp->cp_pbpar, 0x00000c00); + clrbits32(&cp->cp_pbdir, 0x00000c00); + clrbits16(&cp->cp_pbodr, 0x0c00); + immr_unmap(cp); + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } + clrbits32(bcsr_io,BCSR1_RS232EN_2); + iounmap(bcsr_io); +} + +void init_smc_ioports(struct fs_uart_platform_info *data) +{ + int smc_no = fs_uart_id_fsid2smc(data->fs_no); + + switch (smc_no) { + case 0: + init_smc1_uart_ioports(data); + data->brg = data->clk_rx; + break; + case 1: + init_smc2_uart_ioports(data); + data->brg = data->clk_rx; + break; + default: + printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); + return; + } +} + +int platform_device_skip(char *model, int id) +{ + return 0; +} + +static void __init mpc86xads_setup_arch(void) +{ + struct device_node *cpu; + + cpu = of_find_node_by_type(NULL, "cpu"); + if (cpu != 0) { + const unsigned int *fp; + + fp = get_property(cpu, "clock-frequency", NULL); + if (fp != 0) + loops_per_jiffy = *fp / HZ; + else + loops_per_jiffy = 50000000 / HZ; + of_node_put(cpu); + } + + cpm_reset(); + + mpc86xads_board_setup(); + + ROOT_DEV = Root_NFS; +} + +static int __init mpc86xads_probe(void) +{ + char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), + "model", NULL); + if (model == NULL) + return 0; + if (strcmp(model, "MPC866ADS")) + return 0; + + return 1; +} + +define_machine(mpc86x_ads) { + .name = "MPC86x ADS", + .probe = mpc86xads_probe, + .setup_arch = mpc86xads_setup_arch, + .init_IRQ = m8xx_pic_init, + .show_cpuinfo = mpc8xx_show_cpuinfo, + .get_irq = mpc8xx_get_irq, + .restart = mpc8xx_restart, + .calibrate_decr = mpc8xx_calibrate_decr, + .set_rtc_time = mpc8xx_set_rtc_time, + .get_rtc_time = mpc8xx_get_rtc_time, +}; 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