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path: root/arch/sh/drivers/pci/pcie-sh7786.h
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Diffstat (limited to 'arch/sh/drivers/pci/pcie-sh7786.h')
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.h74
1 files changed, 8 insertions, 66 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index c655290a7750..90a6992576b0 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -30,47 +30,9 @@
* for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
*/
-/* PCI0-0: PCI I/O space */
-#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
-#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
-#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
-
-#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
-#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
-#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
-
-/* PCI0-1: PCI memory space 29-bit address */
-#define SH4A_PCIMEM_BASE 0x10000000
-#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
-
-/* PCI0-2: PCI memory space 32-bit address */
-#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
-#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
-#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
-#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
-
/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
-#define SH4A_PCI_DEVICE_ID 0x0002
-#define SH4A_PCI_VENDOR_ID 0x1912
-
-// PCI compatible 000-03f
-#define PCI_CMD 0x004
-#define PCI_RID 0x008
-#define PCI_IBAR 0x010
-#define PCI_MBAR0 0x014
-#define PCI_MBAR1 0x018
-
-/* PCI power management/MSI/capablity 040-0ff */
-/* PCIE extended 100-fff */
-
-/* SH7786 device identification */ // Rev1.171
-#define SH4A_PVR (0xFF000030)
-#define SH4A_PVR_SHX3 (0x10400000)
-#define SH4A_PRR (0xFF000044)
-#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
-
/* SPVCR0 */
#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
#define BITS_TOP_MB (24)
@@ -350,23 +312,23 @@
#define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
-/* PCIEPARL0 */
-#define SH4A_PCIEPARL0 (0x020400) /* R/W R/W 0x0000 0000 32 */
+/* PCIEPARL */
+#define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAL (18)
#define MASK_PAL (0x3fff<<BITS_PAL)
-/* PCIEPARH0 */
-#define SH4A_PCIEPARH0 (0x020404) /* R/W R/W 0x0000 0000 32 */
+/* PCIEPARH */
+#define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAH (0)
#define MASK_PAH (0xffffffff<<BITS_PAH)
-/* PCIEPAMR0 */
-#define SH4A_PCIEPAMR0 (0x020408) /* R/W R/W 0x0000 0000 32 */
+/* PCIEPAMR */
+#define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define BITS_PAM (18)
#define MASK_PAM (0x3fff<<BITS_PAM)
-/* PCIEPTCTLR0 */
-#define SH4A_PCIEPTCTLR0 (0x02040C) /* R/W R/W 0x0000 0000 32 */
+/* PCIEPTCTLR */
+#define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20))
#define BITS_PARE (31)
#define MASK_PARE (0x1<<BITS_PARE)
#define BITS_TC (20)
@@ -378,26 +340,6 @@
#define BITS_SPC (8)
#define MASK_SPC (0x1<<BITS_SPC)
-#define SH4A_PCIEPARL1 (0x020420) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH1 (0x020424) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR1 (0x020428) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR1 (0x02042C) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL2 (0x020440) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH2 (0x020444) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR2 (0x020448) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR2 (0x02044C) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL3 (0x020460) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH3 (0x020464) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR3 (0x020468) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR3 (0x02046C) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL4 (0x020480) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH4 (0x020484) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR4 (0x020488) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR4 (0x02048C) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL5 (0x0204A0) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH5 (0x0204A4) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR5 (0x0204A8) /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR5 (0x0204AC) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
#define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */