diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/configs/imx6_defconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-mx6/Kconfig | 7 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6dl_arm2.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6dl_sabresd.h | 5 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_arm2.c | 42 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_arm2.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabreauto.c | 45 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabreauto.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabrelite.c | 37 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabresd.c | 43 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabresd.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6solo_sabreauto.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-mx6/clock.c | 13 | ||||
-rw-r--r-- | arch/arm/mach-mx6/cpu.c | 8 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/iomux-mx6dl.h | 5 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/iomux-mx6q.h | 12 |
16 files changed, 146 insertions, 125 deletions
diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig index 5ad4a002676d..fc897eddcfa3 100644 --- a/arch/arm/configs/imx6_defconfig +++ b/arch/arm/configs/imx6_defconfig @@ -331,7 +331,6 @@ CONFIG_ARCH_MXC_AUDMUX_V2=y CONFIG_IRAM_ALLOC=y CONFIG_CLK_DEBUG=y CONFIG_DMA_ZONE_SIZE=184 -#CONFIG_MX6_ENET_IRQ_TO_GPIO is not set # # System MMU diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig index e567f67fa901..64ce4d4ac71d 100644 --- a/arch/arm/mach-mx6/Kconfig +++ b/arch/arm/mach-mx6/Kconfig @@ -332,13 +332,6 @@ config MACH_IMX_BLUETOOTH_RFKILL ---help--- Say Y to get the standard rfkill interface of Bluetooth -config MX6_ENET_IRQ_TO_GPIO - bool "Route ENET interrupts to GPIO" - default n - help - Enabling this will direct all the ENET interrupts to a board specific GPIO. - This will allow the system to enter WAIT mode when ENET is active. - config SDMA_IRAM bool "Use Internal RAM for SDMA data structures" depends on IMX_SDMA && SOC_IMX6SL diff --git a/arch/arm/mach-mx6/board-mx6dl_arm2.h b/arch/arm/mach-mx6/board-mx6dl_arm2.h index dd7e66588785..f4560e4a0d74 100644 --- a/arch/arm/mach-mx6/board-mx6dl_arm2.h +++ b/arch/arm/mach-mx6/board-mx6dl_arm2.h @@ -182,16 +182,7 @@ static iomux_v3_cfg_t mx6dl_arm2_pads[] = { /* USBOTG ID pin */ MX6DL_PAD_GPIO_1__USBOTG_ID, - -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else - /* MLB150 */ - MX6DL_PAD_GPIO_3__MLB_MLBCLK, - MX6DL_PAD_GPIO_6__MLB_MLBSIG, - MX6DL_PAD_GPIO_2__MLB_MLBDAT, -#endif -}; + }; static iomux_v3_cfg_t mx6dl_arm2_epdc_pads[] = { MX6DL_PAD_EIM_A17__GPIO_2_21, diff --git a/arch/arm/mach-mx6/board-mx6dl_sabresd.h b/arch/arm/mach-mx6/board-mx6dl_sabresd.h index 4e2d322fe2a9..7cb69246a824 100644 --- a/arch/arm/mach-mx6/board-mx6dl_sabresd.h +++ b/arch/arm/mach-mx6/board-mx6dl_sabresd.h @@ -64,13 +64,8 @@ static iomux_v3_cfg_t mx6dl_sabresd_pads[] = { MX6DL_PAD_KEY_COL3__I2C2_SCL, MX6DL_PAD_KEY_ROW3__I2C2_SDA, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else /* I2C3 */ MX6DL_PAD_GPIO_3__I2C3_SCL, - MX6DL_PAD_GPIO_6__I2C3_SDA, -#endif /* DISPLAY */ MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c index 0fcf99596204..828080565cd3 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.c +++ b/arch/arm/mach-mx6/board-mx6q_arm2.c @@ -155,12 +155,10 @@ #define MX6_ARM2_CAN2_STBY MX6_ARM2_IO_EXP_GPIO2(1) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO #define MX6_ENET_IRQ IMX_GPIO_NR(1, 6) #define IOMUX_OBSRV_MUX1_OFFSET 0x3c #define OBSRV_MUX1_MASK 0x3f #define OBSRV_MUX1_ENET_IRQ 0x9 -#endif #define BMCR_PDOWN 0x0800 /* PHY Powerdown */ @@ -179,6 +177,7 @@ extern char *gp_reg_id; extern char *soc_reg_id; extern char *pu_reg_id; extern int epdc_enabled; +extern bool enet_to_gpio_6; static int max17135_regulator_init(struct max17135 *max17135); enum sd_pad_mode { @@ -393,9 +392,7 @@ static struct fec_platform_data fec_data __initdata = { .init = mx6_arm2_fec_phy_init, .power_hibernate = mx6_arm2_fec_power_hibernate, .phy = PHY_INTERFACE_MODE_RGMII, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO .gpio_irq = MX6_ENET_IRQ, -#endif }; static int mx6_arm2_spi_cs[] = { @@ -2056,6 +2053,18 @@ static void __init mx6_arm2_init(void) spdif_pads_cnt = ARRAY_SIZE(mx6q_arm2_spdif_pads); flexcan_pads_cnt = ARRAY_SIZE(mx6q_arm2_can_pads); i2c3_pads_cnt = ARRAY_SIZE(mx6q_arm2_i2c3_pads); + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t mlb_pads[] = { + MX6Q_PAD_GPIO_3__MLB_MLBCLK, + MX6Q_PAD_GPIO_6__MLB_MLBSIG, + MX6Q_PAD_GPIO_2__MLB_MLBDAT}; + mxc_iomux_v3_setup_multiple_pads(mlb_pads, + ARRAY_SIZE(mlb_pads)); + } } else if (cpu_is_mx6dl()) { common_pads = mx6dl_arm2_pads; esai_rec_pads = mx6dl_arm2_esai_record_pads; @@ -2070,6 +2079,18 @@ static void __init mx6_arm2_init(void) flexcan_pads_cnt = ARRAY_SIZE(mx6dl_arm2_can_pads); i2c3_pads_cnt = ARRAY_SIZE(mx6dl_arm2_i2c3_pads); epdc_pads_cnt = ARRAY_SIZE(mx6dl_arm2_epdc_pads); + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6DL_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t mlb_pads[] = { + MX6DL_PAD_GPIO_3__MLB_MLBCLK, + MX6DL_PAD_GPIO_6__MLB_MLBSIG, + MX6DL_PAD_GPIO_2__MLB_MLBDAT}; + mxc_iomux_v3_setup_multiple_pads(mlb_pads, + ARRAY_SIZE(mlb_pads)); + } } BUG_ON(!common_pads); @@ -2181,12 +2202,15 @@ static void __init mx6_arm2_init(void) imx6q_add_anatop_thermal_imx(1, &mx6_arm2_anatop_thermal_data); if (!esai_record) { + if (enet_to_gpio_6) + /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ + mxc_iomux_set_specialbits_register( + IOMUX_OBSRV_MUX1_OFFSET, + OBSRV_MUX1_ENET_IRQ, + OBSRV_MUX1_MASK); + else + fec_data.gpio_irq = -1; imx6_init_fec(fec_data); -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ - mxc_iomux_set_specialbits_register(IOMUX_OBSRV_MUX1_OFFSET, - OBSRV_MUX1_ENET_IRQ, OBSRV_MUX1_MASK); -#endif } imx6q_add_pm_imx(0, &mx6_arm2_pm_data); diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.h b/arch/arm/mach-mx6/board-mx6q_arm2.h index 2a6a2052b3f9..24a894fab905 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.h +++ b/arch/arm/mach-mx6/board-mx6q_arm2.h @@ -182,16 +182,7 @@ static iomux_v3_cfg_t mx6q_arm2_pads[] = { /* USBOTG ID pin */ MX6Q_PAD_GPIO_1__USBOTG_ID, - -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else - /* MLB150 */ - MX6Q_PAD_GPIO_3__MLB_MLBCLK, - MX6Q_PAD_GPIO_6__MLB_MLBSIG, - MX6Q_PAD_GPIO_2__MLB_MLBDAT, -#endif -}; + }; static iomux_v3_cfg_t mx6q_arm2_i2c3_pads[] = { MX6Q_PAD_GPIO_5__I2C3_SCL, diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c index 5e0ed0d1f99b..e1df8723146c 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c @@ -114,12 +114,10 @@ #define SABREAUTO_MAX7310_2_BASE_ADDR IMX_GPIO_NR(8, 8) #define SABREAUTO_MAX7310_3_BASE_ADDR IMX_GPIO_NR(8, 16) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO #define MX6_ENET_IRQ IMX_GPIO_NR(1, 6) #define IOMUX_OBSRV_MUX1_OFFSET 0x3c #define OBSRV_MUX1_MASK 0x3f #define OBSRV_MUX1_ENET_IRQ 0x9 -#endif #define SABREAUTO_IO_EXP_GPIO1(x) (SABREAUTO_MAX7310_1_BASE_ADDR + (x)) #define SABREAUTO_IO_EXP_GPIO2(x) (SABREAUTO_MAX7310_2_BASE_ADDR + (x)) @@ -142,6 +140,7 @@ extern char *gp_reg_id; extern char *soc_reg_id; extern char *pu_reg_id; +extern bool enet_to_gpio_6; static int mma8451_position = 3; static int mag3110_position = 2; @@ -411,9 +410,7 @@ static struct fec_platform_data fec_data __initdata = { .init = mx6q_sabreauto_fec_phy_init, .power_hibernate = mx6q_sabreauto_fec_power_hibernate, .phy = PHY_INTERFACE_MODE_RGMII, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - .gpio_irq = MX6_ENET_IRQ, -#endif + .gpio_irq = MX6_ENET_IRQ, }; static int mx6q_sabreauto_spi_cs[] = { @@ -1506,6 +1503,18 @@ static void __init mx6_board_init(void) mxc_iomux_v3_setup_multiple_pads(extra_pads, extra_pads_cnt); } + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t mlb_pads[] = { + MX6Q_PAD_ENET_TXD1__MLB_MLBCLK, + MX6Q_PAD_GPIO_6__MLB_MLBSIG, + MX6Q_PAD_GPIO_2__MLB_MLBDAT}; + mxc_iomux_v3_setup_multiple_pads(mlb_pads, + ARRAY_SIZE(mlb_pads)); + } } else if (cpu_is_mx6dl()) { common_pads = mx6dl_sabreauto_pads; can0_pads = mx6dl_sabreauto_can0_pads; @@ -1538,6 +1547,18 @@ static void __init mx6_board_init(void) mxc_iomux_v3_setup_multiple_pads(extra_pads, extra_pads_cnt); } + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6DL_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t mlb_pads[] = { + MX6DL_PAD_ENET_TXD1__MLB_MLBCLK, + MX6DL_PAD_GPIO_6__MLB_MLBSIG, + MX6DL_PAD_GPIO_2__MLB_MLBDAT}; + mxc_iomux_v3_setup_multiple_pads(mlb_pads, + ARRAY_SIZE(mlb_pads)); + } } BUG_ON(!common_pads); @@ -1681,13 +1702,15 @@ static void __init mx6_board_init(void) imx6q_add_anatop_thermal_imx(1, &mx6q_sabreauto_anatop_thermal_data); if (!can0_enable) { + if (enet_to_gpio_6) + /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ + mxc_iomux_set_specialbits_register( + IOMUX_OBSRV_MUX1_OFFSET, + OBSRV_MUX1_ENET_IRQ, + OBSRV_MUX1_MASK); + else + fec_data.gpio_irq = -1; imx6_init_fec(fec_data); -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ - mxc_iomux_set_specialbits_register(IOMUX_OBSRV_MUX1_OFFSET, - OBSRV_MUX1_ENET_IRQ, OBSRV_MUX1_MASK); -#endif - } imx6q_add_pm_imx(0, &mx6q_sabreauto_pm_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h index e4d62f1baaa5..436a11d03a31 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h @@ -207,16 +207,7 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = { /* HDMI */ MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE, - -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else - /* MLB150 */ - MX6Q_PAD_ENET_TXD1__MLB_MLBCLK, - MX6Q_PAD_GPIO_6__MLB_MLBSIG, - MX6Q_PAD_GPIO_2__MLB_MLBDAT, -#endif -}; + }; static iomux_v3_cfg_t mx6q_sabreauto_can0_pads[] = { /* CAN1 */ diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c index 14f87ee96cf5..1fe0f7b1c084 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c +++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c @@ -93,12 +93,10 @@ #define MX6Q_SABRELITE_CSI0_RST IMX_GPIO_NR(1, 8) #define MX6Q_SABRELITE_CSI0_PWN IMX_GPIO_NR(1, 6) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO #define MX6_ENET_IRQ IMX_GPIO_NR(1, 6) #define IOMUX_OBSRV_MUX1_OFFSET 0x3c #define OBSRV_MUX1_MASK 0x3f #define OBSRV_MUX1_ENET_IRQ 0x9 -#endif #define MX6Q_SABRELITE_SD3_WP_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ @@ -110,6 +108,7 @@ static struct clk *sata_clk; extern char *gp_reg_id; extern char *soc_reg_id; extern char *pu_reg_id; +extern bool enet_to_gpio_6; static int caam_enabled; extern struct regulator *(*get_cpu_regulator)(void); @@ -216,8 +215,8 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = { MX6Q_PAD_EIM_D28__I2C1_SDA, /* GPIO3[28] */ /* I2C2 Camera, MIPI */ - MX6Q_PAD_KEY_COL3__I2C2_SCL, /* GPIO4[12] */ - MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* GPIO4[13] */ + MX6Q_PAD_KEY_COL3__I2C2_SCL, /* GPIO4[12] */ + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* GPIO4[13] */ /* I2C3 */ MX6Q_PAD_GPIO_5__I2C3_SCL, /* GPIO1[5] - J7 - Display card */ @@ -328,9 +327,6 @@ static iomux_v3_cfg_t mx6q_sabrelite_csi0_sensor_pads[] = { MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC, MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK, MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC, -#ifndef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6Q_PAD_GPIO_6__GPIO_1_6, /* J5 - Camera GP */ -#endif MX6Q_PAD_GPIO_8__GPIO_1_8, /* J5 - Camera Reset */ MX6Q_PAD_SD1_DAT0__GPIO_1_16, /* J5 - Camera GP */ MX6Q_PAD_NANDF_D5__GPIO_2_5, /* J16 - MIPI GP */ @@ -476,9 +472,7 @@ static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev) static struct fec_platform_data fec_data __initdata = { .init = mx6q_sabrelite_fec_phy_init, .phy = PHY_INTERFACE_MODE_RGMII, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO .gpio_irq = MX6_ENET_IRQ, -#endif }; static int mx6q_sabrelite_spi_cs[] = { @@ -1171,6 +1165,17 @@ static void __init mx6_sabrelite_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_pads, ARRAY_SIZE(mx6q_sabrelite_pads)); + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + /* J5 - Camera GP */ + iomux_v3_cfg_t camera_gpio_pad = + MX6Q_PAD_GPIO_6__GPIO_1_6; + mxc_iomux_v3_setup_pad(camera_gpio_pad); + } + #ifdef CONFIG_FEC_1588 /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock * For MX6 GPR1 bit21 meaning: @@ -1231,12 +1236,16 @@ static void __init mx6_sabrelite_board_init(void) imx6q_add_mxc_hdmi(&hdmi_data); imx6q_add_anatop_thermal_imx(1, &mx6q_sabrelite_anatop_thermal_data); + if (enet_to_gpio_6) + /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ + mxc_iomux_set_specialbits_register( + IOMUX_OBSRV_MUX1_OFFSET, + OBSRV_MUX1_ENET_IRQ, + OBSRV_MUX1_MASK); + else + fec_data.gpio_irq = -1; + imx6_init_fec(fec_data); -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ - mxc_iomux_set_specialbits_register(IOMUX_OBSRV_MUX1_OFFSET, - OBSRV_MUX1_ENET_IRQ, OBSRV_MUX1_MASK); -#endif imx6q_add_pm_imx(0, &mx6q_sabrelite_pm_data); imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabrelite_sd4_data); imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabrelite_sd3_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c index 608c3553ec37..3f9a845f3b68 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabresd.c +++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c @@ -198,12 +198,10 @@ #define SABRESD_ELAN_RST IMX_GPIO_NR(3, 8) #define SABRESD_ELAN_INT IMX_GPIO_NR(3, 28) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO #define MX6_ENET_IRQ IMX_GPIO_NR(1, 6) #define IOMUX_OBSRV_MUX1_OFFSET 0x3c #define OBSRV_MUX1_MASK 0x3f #define OBSRV_MUX1_ENET_IRQ 0x9 -#endif static struct clk *sata_clk; static struct clk *clko; @@ -216,6 +214,7 @@ extern char *gp_reg_id; extern char *soc_reg_id; extern char *pu_reg_id; extern int epdc_enabled; +extern bool enet_to_gpio_6; static int max17135_regulator_init(struct max17135 *max17135); @@ -298,9 +297,7 @@ static int mx6q_sabresd_fec_phy_init(struct phy_device *phydev) static struct fec_platform_data fec_data __initdata = { .init = mx6q_sabresd_fec_phy_init, .phy = PHY_INTERFACE_MODE_RGMII, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO .gpio_irq = MX6_ENET_IRQ, -#endif }; static int mx6q_sabresd_spi_cs[] = { @@ -1717,14 +1714,34 @@ static void __init mx6_sabresd_board_init(void) int rate; struct platform_device *voutdev; - if (cpu_is_mx6q()) + if (cpu_is_mx6q()) { mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_pads, ARRAY_SIZE(mx6q_sabresd_pads)); - else if (cpu_is_mx6dl()) { + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t i2c3_pad = + MX6Q_PAD_GPIO_6__I2C3_SDA; + mxc_iomux_v3_setup_pad(i2c3_pad); + } + } else if (cpu_is_mx6dl()) { mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_pads, ARRAY_SIZE(mx6dl_sabresd_pads)); + + if (enet_to_gpio_6) { + iomux_v3_cfg_t enet_gpio_pad = + MX6DL_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6; + mxc_iomux_v3_setup_pad(enet_gpio_pad); + } else { + iomux_v3_cfg_t i2c3_pad = + MX6DL_PAD_GPIO_6__I2C3_SDA; + mxc_iomux_v3_setup_pad(i2c3_pad); + } } + #ifdef CONFIG_FEC_1588 /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock * For MX6 GPR1 bit21 meaning: @@ -1817,12 +1834,16 @@ static void __init mx6_sabresd_board_init(void) imx6q_add_mxc_hdmi(&hdmi_data); imx6q_add_anatop_thermal_imx(1, &mx6q_sabresd_anatop_thermal_data); + + if (enet_to_gpio_6) + /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ + mxc_iomux_set_specialbits_register( + IOMUX_OBSRV_MUX1_OFFSET, + OBSRV_MUX1_ENET_IRQ, + OBSRV_MUX1_MASK); + else + fec_data.gpio_irq = -1; imx6_init_fec(fec_data); -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */ - mxc_iomux_set_specialbits_register(IOMUX_OBSRV_MUX1_OFFSET, - OBSRV_MUX1_ENET_IRQ, OBSRV_MUX1_MASK); -#endif imx6q_add_pm_imx(0, &mx6q_sabresd_pm_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.h b/arch/arm/mach-mx6/board-mx6q_sabresd.h index b2bb8c923f0f..adb2e3e557db 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabresd.h +++ b/arch/arm/mach-mx6/board-mx6q_sabresd.h @@ -132,13 +132,8 @@ static iomux_v3_cfg_t mx6q_sabresd_pads[] = { MX6Q_PAD_KEY_COL3__I2C2_SCL, MX6Q_PAD_KEY_ROW3__I2C2_SDA, -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else - /* I2C3 */ - MX6Q_PAD_GPIO_3__I2C3_SCL, /* GPIO1[3] */ - MX6Q_PAD_GPIO_6__I2C3_SDA, -#endif + /*I2C3 */ + MX6Q_PAD_GPIO_3__I2C3_SCL, /* DISPLAY */ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h index b0edb5e52b52..e4047d585eaf 100644 --- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h @@ -204,16 +204,7 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = { /* HDMI */ MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE, - -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO - MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1, -#else - /* MLB150 */ - MX6DL_PAD_ENET_TXD1__MLB_MLBCLK, - MX6DL_PAD_GPIO_6__MLB_MLBSIG, - MX6DL_PAD_GPIO_2__MLB_MLBDAT, -#endif -}; + }; static iomux_v3_cfg_t mx6dl_sabreauto_can0_pads[] = { /* CAN1 */ diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 61bedb57a54c..52af5daa09f8 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -51,6 +51,7 @@ extern int wait_mode_arm_podf; extern int lp_audio_freq; extern int cur_arm_podf; extern bool enet_is_active; +extern bool enet_to_gpio_6; void __iomem *apll_base; @@ -3751,9 +3752,9 @@ static unsigned long _clk_enet_get_rate(struct clk *clk) static int _clk_enet_enable(struct clk *clk) { -#ifndef CONFIG_MX6_ENET_IRQ_TO_GPIO - enet_is_active = true; -#endif + if (!enet_to_gpio_6) + enet_is_active = true; + _clk_enable(clk); return 0; } @@ -3761,9 +3762,9 @@ static int _clk_enet_enable(struct clk *clk) static void _clk_enet_disable(struct clk *clk) { _clk_disable(clk); -#ifndef CONFIG_MX6_ENET_IRQ_TO_GPIO - enet_is_active = false; -#endif + + if (!enet_to_gpio_6) + enet_is_active = false; } static struct clk enet_clk[] = { diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index eaeae1d3c57c..a65ad81e666d 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -37,6 +37,7 @@ bool enable_wait_mode = true; u32 enable_ldo_mode = LDO_MODE_DEFAULT; u32 arm_max_freq = CPU_AT_1_2GHz; bool mem_clk_on_in_wait; +bool enet_to_gpio_6; int chip_rev; void __iomem *gpc_base; @@ -276,5 +277,10 @@ static int __init enable_mem_clk_in_wait(char *p) early_param("mem_clk_on", enable_mem_clk_in_wait); +static int __init set_enet_irq_to_gpio(char *p) +{ + enet_to_gpio_6 = true; + return 0; +} - +early_param("enet_gpio_6", set_enet_irq_to_gpio); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h index a94e15b4a4aa..59f8399be39c 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h @@ -2531,10 +2531,8 @@ #define MX6DL_PAD_GPIO_5__SIMBA_EVENTI \ IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO -#define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ +#define MX6DL_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6 \ IOMUX_PAD(0x0604, 0x0234, 1 | IOMUX_CONFIG_SION, 0x0000, 0, ENET_IRQ_PAD_CTRL) -#else #define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_GPIO_6__ESAI1_SCKT \ @@ -2551,7 +2549,6 @@ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) #define MX6DL_PAD_GPIO_6__MLB_MLBSIG \ IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, MX6DL_MLB150_PAD_CTRL) -#endif #define MX6DL_PAD_GPIO_7__ESAI1_TX4_RX1 \ IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h index 291b6af14be7..16cd87f46459 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -2332,13 +2332,10 @@ #define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \ IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO -#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ +#define _MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6 \ IOMUX_PAD(0x0600, 0x0230, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -#else #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0) -#endif #define _MX6Q_PAD_GPIO_6__I2C3_SDA \ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0) #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ @@ -5940,10 +5937,8 @@ #define MX6Q_PAD_GPIO_3__MLB_MLBCLK \ (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL)) -#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO -#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ - (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(ENET_IRQ_PAD_CTRL)) -#else +#define MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6 \ + (_MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6 | MUX_PAD_CTRL(ENET_IRQ_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__ESAI1_SCKT \ @@ -5960,7 +5955,6 @@ (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__MLB_MLBSIG \ (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL)) -#endif #define MX6Q_PAD_GPIO_2__ESAI1_FST \ (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) |