diff options
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/arm/plat-mxc/include/mach/mxc_edid.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc_hdmi.h | 85 |
2 files changed, 56 insertions, 30 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h index 59688f657a25..4cbbb78ad703 100755 --- a/arch/arm/plat-mxc/include/mach/mxc_edid.h +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -28,6 +28,7 @@ #define FB_VMODE_ASPECT_4_3 0x10 #define FB_VMODE_ASPECT_16_9 0x20 +#define FB_VMODE_ASPECT_MASK (FB_VMODE_ASPECT_4_3 | FB_VMODE_ASPECT_16_9) struct mxc_edid_cfg { bool cea_underscan; diff --git a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h index a7f22de9b407..56729b229585 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h +++ b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h @@ -377,6 +377,7 @@ #define HDMI_AUD_CTS2 0x3204 #define HDMI_AUD_CTS3 0x3205 #define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 #define HDMI_AUD_CONF0_HBR 0x3400 #define HDMI_AUD_HBR_STATUS 0x3401 #define HDMI_AUD_HBR_INT 0x3402 @@ -564,6 +565,16 @@ * Register field definitions */ enum { +/* IH_FC_INT2 field values */ + HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_FC_STAT2 field values */ + HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + /* IH_PHY_STAT0 field values */ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, @@ -584,6 +595,11 @@ enum { HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, +/* IH_MUTE_FC_STAT2 field values */ + HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + /* IH_MUTE_AHBDMAAUD_STAT0 field values */ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, @@ -750,6 +766,21 @@ enum { HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, +/* FC_STAT2 field values */ + HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_INT2 field values */ + HDMI_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_MASK2 field values */ + HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, + HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, + /* FC_PRCONF field values */ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, @@ -822,24 +853,19 @@ enum { HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, /* PHY_CONF0 field values */ - HDMI_PHY_CONF0_PDZ = 0x80, HDMI_PHY_CONF0_PDZ_MASK = 0x80, HDMI_PHY_CONF0_PDZ_OFFSET = 7, - HDMI_PHY_CONF0_ENTMDS = 0x40, HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, HDMI_PHY_CONF0_SPARECTRL = 0x20, HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_ENABLE = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_DISABLE = 0x00, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_ON = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_OFF = 0x0, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE = 0x4, - HDMI_PHY_CONF0_SELDATAENPOL = 0x2, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, - HDMI_PHY_CONF0_SELDIPIF = 0x1, HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, @@ -867,6 +893,16 @@ enum { HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, +/* HDMI_PHY_I2CM_INT_ADDR */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, + +/* HDMI_PHY_I2CM_CTLINT_ADDR */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, + /* AUD_CTS3 field values */ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, @@ -916,27 +952,16 @@ enum { HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, /* MC_CLKDIS field values */ - HDMI_MC_CLKDIS_HDCPCLK_DISABLE_MASK = 0x40, - HDMI_MC_CLKDIS_HDCPCLK_DISABLE_DISABLE = 0x40, - HDMI_MC_CLKDIS_HDCPCLK_DISABLE_ENABLE = 0x00, - HDMI_MC_CLKDIS_CECCLK_DISABLE_MASK = 0x20, - HDMI_MC_CLKDIS_CECCLK_DISABLE_DISABLE = 0x20, - HDMI_MC_CLKDIS_CECCLK_DISABLE_ENABLE = 0x00, - HDMI_MC_CLKDIS_CSCCLK_DISABLE_MASK = 0x10, - HDMI_MC_CLKDIS_CSCCLK_DISABLE_DISABLE = 0x10, - HDMI_MC_CLKDIS_CSCCLK_DISABLE_ENABLE = 0x00, - HDMI_MC_CLKDIS_AUDCLK_DISABLE_MASK = 0x8, - HDMI_MC_CLKDIS_AUDCLK_DISABLE_DISABLE = 0x8, - HDMI_MC_CLKDIS_AUDCLK_DISABLE_ENABLE = 0x0, - HDMI_MC_CLKDIS_PREPCLK_DISABLE_MASK = 0x4, - HDMI_MC_CLKDIS_PREPCLK_DISABLE_DISABLE = 0x4, - HDMI_MC_CLKDIS_PREPCLK_DISABLE_ENABLE = 0x0, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE_MASK = 0x2, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE_DISABLE = 0x2, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE_ENABLE = 0x0, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE_MASK = 0x1, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE_DISABLE = 0x1, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE_ENABLE = 0x0, + HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, + HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, + HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + +/* MC_SWRSTZ field values */ + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, /* MC_FLOWCTRL field values */ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, |