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-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi10
-rw-r--r--arch/arm/boot/dts/imx6sx-19x19-arm2.dts12
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts12
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi80
-rw-r--r--arch/arm/configs/imx_v7_android_defconfig1
-rw-r--r--arch/arm/configs/imx_v7_defconfig1
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c4
9 files changed, 114 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index fd5d0b31e1c4..b40495e5e820 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -628,6 +628,18 @@
};
};
+&dcic1 {
+ dcic_id = <0>;
+ dcic_mux = "dcic-hdmi";
+ status = "okay";
+};
+
+&dcic2 {
+ dcic_id = <1>;
+ dcic_mux = "dcic-lvds0";
+ status = "okay";
+};
+
&mlb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mlb_2>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 1a9ab935c0cf..9b0505675a32 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -586,6 +586,18 @@
status = "okay";
};
+&dcic1 {
+ dcic_id = <0>;
+ dcic_mux = "dcic-hdmi";
+ status = "okay";
+};
+
+&dcic2 {
+ dcic_id = <1>;
+ dcic_mux = "dcic-lvds1";
+ status = "okay";
+};
+
&pcie {
power-on-gpio = <&gpio3 19 0>;
reset-gpio = <&gpio7 12 0>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index cecc6c298c06..268592644c4a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -717,13 +717,23 @@
};
dcic1: dcic@020e4000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
+ clocks = <&clks 231>, <&clks 231>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
dcic2: dcic@020e8000 {
+ compatible = "fsl,imx6q-dcic";
reg = <0x020e8000 0x4000>;
interrupts = <0 125 0x04>;
+ clocks = <&clks 232>, <&clks 232>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
};
sdma: sdma@020ec000 {
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
index 131f330decfe..fbcff0c22a4d 100644
--- a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
@@ -405,6 +405,18 @@
};
};
+&dcic1 {
+ dcic_id = <0>;
+ dcic_mux = "dcic-lcdif1";
+ status = "okay";
+};
+
+&dcic2 {
+ dcic_id = <1>;
+ dcic_mux = "dcic-lvds";
+ status = "okay";
+};
+
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3_0>;
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index bd152a26aa8d..391153930bca 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -609,6 +609,18 @@
};
};
+&dcic1 {
+ dcic_id = <0>;
+ dcic_mux = "dcic-lcdif1";
+ status = "okay";
+};
+
+&dcic2 {
+ dcic_id = <1>;
+ dcic_mux = "dcic-lvds";
+ status = "okay";
+};
+
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3_1>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index ab915d2e17e6..b3316bf775cd 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1062,6 +1062,28 @@
reg = <0x02240000 0x40000>;
ranges;
+ dcic1: dcic@0220c000 {
+ compatible = "fsl,imx6sx-dcic";
+ reg = <0x0220c000 0x4000>;
+ interrupts = <0 124 0x04>;
+ clocks = <&clks IMX6SX_CLK_DCIC1>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
+ };
+
+ dcic2: dcic@02210000 {
+ compatible = "fsl,imx6sx-dcic";
+ reg = <0x02210000 0x4000>;
+ interrupts = <0 125 0x04>;
+ clocks = <&clks IMX6SX_CLK_DCIC2>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "dcic", "disp-axi";
+ gpr = <&gpr>;
+ status = "disabled";
+ };
+
csi1: csi@02214000 {
compatible = "fsl,imx6sx-csi", "fsl,imx6sl-csi";
reg = <0x02214000 0x4000>;
@@ -1448,40 +1470,40 @@
lcdif1 {
pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
fsl,pins = <
- MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x1b0b0
- MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x1b0b0
- MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x1b0b0
- MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x1b0b0
- MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x1b0b0
- MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x1b0b0
- MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x1b0b0
- MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x1b0b0
- MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x1b0b0
- MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x1b0b0
- MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x1b0b0
- MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x1b0b0
- MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x1b0b0
- MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x1b0b0
- MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x1b0b0
- MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x1b0b0
- MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x1b0b0
- MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x1b0b0
- MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x1b0b0
- MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x1b0b0
- MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x1b0b0
- MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x1b0b0
- MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x1b0b0
- MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x1b0b0
+ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
>;
};
pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
fsl,pins = <
- MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x1b0b0
- MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x1b0b0
- MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x1b0b0
- MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x1b0b0
- MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0
+ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
+ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
};
diff --git a/arch/arm/configs/imx_v7_android_defconfig b/arch/arm/configs/imx_v7_android_defconfig
index cba370789f04..fc97892c87ac 100644
--- a/arch/arm/configs/imx_v7_android_defconfig
+++ b/arch/arm/configs/imx_v7_android_defconfig
@@ -2504,6 +2504,7 @@ CONFIG_FB_MXC_EDID=y
CONFIG_FB_MXC_EINK_PANEL=y
# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
CONFIG_FB_MXS_SII902X=y
+CONFIG_FB_MXC_DCIC=m
CONFIG_HANNSTAR_CABC=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index ff1b66c9e1cd..9f4d52cf80ca 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -226,6 +226,7 @@ CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
CONFIG_FB_MXC_HDMI=y
CONFIG_FB_MXC_EINK_PANEL=y
CONFIG_FB_MXS_SII902X=y
+CONFIG_FB_MXC_DCIC=m
CONFIG_HANNSTAR_CABC=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4497e29fb602..4e7259669f4e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -118,7 +118,7 @@ enum mx6q_clks {
pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk,
caam_ipg, epit1, epit2, tzasc2, pll4_sel, lvds2_sel, lvds2_in, lvds2_out,
anaclk1, anaclk2, spdif1, asrc_ipg, asrc_mem, esai_ipg, esai_mem,
- axi_alt_sel, clk_max
+ axi_alt_sel, dcic1, dcic2, clk_max
};
static struct clk *clk[clk_max];
@@ -505,6 +505,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
+ clk[dcic1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
+ clk[dcic2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
generated by cgit v1.2.3 (git 2.0.4) at 2024-12-26 19:53:30 +0000