diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/imx7ulp-evk.dts | 33 | ||||
-rw-r--r-- | arch/arm/configs/imx_v7_defconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-imx/anatop.c | 60 | ||||
-rw-r--r-- | arch/arm/mach-imx/cpu.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-imx/gpc.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-imx/mach-imx6q.c | 5 |
6 files changed, 57 insertions, 57 deletions
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 0ff23f42aa44..3ee6e3c34747 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -16,6 +16,11 @@ model = "NXP i.MX7ULP EVK"; compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; + }; + chosen { bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; stdout-path = &lpuart4; @@ -166,6 +171,22 @@ status = "okay"; }; + rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + rpmsg_keys: rpmsg-keys { compatible = "fsl,rpmsg-keys"; @@ -484,15 +505,11 @@ &rpmsg{ /* * 64K for one rpmsg instance, default using 2 rpmsg instances: - * --0x9FF00000~0x9FF0FFFF: pingpong - * --0x9FF10000~0x9FF1FFFF: pmic - * --0x9FF20000~0x9FF2FFFF: pm - * --0x9FF30000~0x9FF3FFFF: audio - * --0x9FF40000~0x9FF4FFFF: virtual tty - * --0x9FF50000~0x9FF5FFFF: keys + * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio + * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty */ - vdev-nums = <6>; - reg = <0x9FF00000 0x60000>; + vdev-nums = <2>; + reg = <0x9FF00000 0x20000>; status = "okay"; }; diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 25fbcf67a6c2..5d6d3d0189b5 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -198,6 +198,7 @@ CONFIG_SPI_IMX=y CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_SPIDEV=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_IMX_RPMSG=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_74X164=y diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index e6e55723d9cf..d46f68417bbb 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -145,7 +146,7 @@ void imx_anatop_pre_suspend(void) return; } - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(true); if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || @@ -175,7 +176,7 @@ void imx_anatop_post_resume(void) return; } - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(false); if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || @@ -209,6 +210,7 @@ void __init imx_init_revision_from_anatop(void) unsigned int revision; u32 digprog; u16 offset = ANADIG_DIGPROG; + u16 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); @@ -220,45 +222,25 @@ void __init imx_init_revision_from_anatop(void) digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); - switch (digprog & 0xff) { - case 0: - /* - * For i.MX6QP, most of the code for i.MX6Q can be resued, - * so internally, we identify it as i.MX6Q Rev 2.0 - */ - if (digprog >> 8 & 0x01) - revision = IMX_CHIP_REVISION_2_0; - else - revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - revision = IMX_CHIP_REVISION_1_2; - break; - case 3: - revision = IMX_CHIP_REVISION_1_3; - break; - case 4: - revision = IMX_CHIP_REVISION_1_4; - break; - case 5: - /* - * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked - * as 'D' in Part Number last character. - */ - revision = IMX_CHIP_REVISION_1_5; - break; - default: + /* + * On i.MX7D digprog value match linux version format, so + * it needn't map again and we can use register value directly. + */ + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { + revision = digprog & 0xff; + } else { /* - * Fail back to return raw register value instead of 0xff. - * It will be easy to know version information in SOC if it - * can't be recognized by known version. And some chip's (i.MX7D) - * digprog value match linux version format, so it needn't map - * again and we can use register value directly. + * MAJOR: [15:8], the major silicon revison; + * MINOR: [7: 0], the minor silicon revison; + * + * please refer to the i.MX RM for the detailed + * silicon revison bit define. + * format the major part and minor part to match the + * linux kernel soc version format. */ - revision = digprog & 0xff; + major_part = (digprog >> 8) & 0xf; + minor_part = digprog & 0xf; + revision = ((major_part + 1) << 4) | minor_part; } mxc_set_cpu_type(digprog >> 16 & 0xff); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index d23af05447d0..30ab50744cd3 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -173,9 +173,7 @@ struct device * __init imx_soc_device_init(void) soc_id = "i.MX6SX"; break; case MXC_CPU_IMX6Q: - soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); - - if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) soc_id = "i.MX6QP"; else soc_id = "i.MX6Q"; diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 1629608899a9..551ecd0f2a4f 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -1,6 +1,7 @@ /* * Copyright 2011-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -231,7 +232,7 @@ void imx_gpc_pre_suspend(bool arm_power_off) void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) _imx6q_pm_pu_power_off(&imx6q_pu_domain.base); /* power down the mega-fast power domain */ @@ -254,7 +255,7 @@ void imx_gpc_post_resume(void) void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) _imx6q_pm_pu_power_on(&imx6q_pu_domain.base); /* Keep ARM core powered on for other low-power modes */ @@ -648,7 +649,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) struct pu_domain *pu = container_of(genpd, struct pu_domain, base); if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() && - imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) return 0; _imx6q_pm_pu_power_off(genpd); @@ -693,7 +694,7 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) struct pu_domain *pu = container_of(genpd, struct pu_domain, base); int ret; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0 + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0 && &imx6q_pu_domain == pu) { if (!pu_on) pu_on = true; @@ -856,7 +857,7 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) is_off = IS_ENABLED(CONFIG_PM); if (is_off && !(cpu_is_imx6q() && - imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)) { + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)) { _imx6q_pm_pu_power_off(&imx6q_pu_domain.base); } else { /* diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 7569722ff7ea..c0e3928d5f73 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -1,6 +1,7 @@ /* * Copyright 2011-2015 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -342,7 +343,7 @@ static inline void imx6q_enet_init(void) imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp"); imx6q_enet_phy_init(); imx6q_1588_init(); - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx6q_enet_clk_sel(); } @@ -350,7 +351,7 @@ static void __init imx6q_init_machine(void) { struct device *parent; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", |