diff options
Diffstat (limited to 'drivers/bcma/driver_chipcommon.c')
| -rw-r--r-- | drivers/bcma/driver_chipcommon.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index acca327db3de..47cce9d69630 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -106,3 +106,51 @@ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) { return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); } + +#ifdef CONFIG_BCMA_DRIVER_MIPS +void bcma_chipco_serial_init(struct bcma_drv_cc *cc) +{ + unsigned int irq; + u32 baud_base; + u32 i; + unsigned int ccrev = cc->core->id.rev; + struct bcma_serial_port *ports = cc->serial_ports; + + if (ccrev >= 11 && ccrev != 15) { + /* Fixed ALP clock */ + baud_base = bcma_pmu_alp_clock(cc); + if (ccrev >= 21) { + /* Turn off UART clock before switching clocksource. */ + bcma_cc_write32(cc, BCMA_CC_CORECTL, + bcma_cc_read32(cc, BCMA_CC_CORECTL) + & ~BCMA_CC_CORECTL_UARTCLKEN); + } + /* Set the override bit so we don't divide it */ + bcma_cc_write32(cc, BCMA_CC_CORECTL, + bcma_cc_read32(cc, BCMA_CC_CORECTL) + | BCMA_CC_CORECTL_UARTCLK0); + if (ccrev >= 21) { + /* Re-enable the UART clock. */ + bcma_cc_write32(cc, BCMA_CC_CORECTL, + bcma_cc_read32(cc, BCMA_CC_CORECTL) + | BCMA_CC_CORECTL_UARTCLKEN); + } + } else { + pr_err("serial not supported on this device ccrev: 0x%x\n", + ccrev); + return; + } + + irq = bcma_core_mips_irq(cc->core); + + /* Determine the registers of the UARTs */ + cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); + for (i = 0; i < cc->nr_serial_ports; i++) { + ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + + (i * 256); + ports[i].irq = irq; + ports[i].baud_base = baud_base; + ports[i].reg_shift = 0; + } +} +#endif /* CONFIG_BCMA_DRIVER_MIPS */ |