diff options
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_ring.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/si.c | 6 |
5 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c1f691958f89..742206e45103 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1789,7 +1789,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) */ mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; gfp = mapping_gfp_mask(mapping); - gfp |= __GFP_NORETRY | __GFP_NOWARN; + gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; gfp &= ~(__GFP_IO | __GFP_WAIT); for_each_sg(st->sgl, sg, page_count, i) { page = shmem_read_mapping_page_gfp(mapping, i, gfp); @@ -1802,7 +1802,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) * our own buffer, now let the real VM do its job and * go down in flames if truly OOM. */ - gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); + gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); gfp |= __GFP_IO | __GFP_WAIT; i915_gem_shrink_all(dev_priv); @@ -1810,7 +1810,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) if (IS_ERR(page)) goto err_pages; - gfp |= __GFP_NORETRY | __GFP_NOWARN; + gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; gfp &= ~(__GFP_IO | __GFP_WAIT); } diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 8dbc69a6e5bd..f95d7fc1f5e0 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1650,7 +1650,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev) ring->wptr = 0; WREG32(CP_RB_WPTR, ring->wptr); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 39e8be1d1e89..7bdbcb00aaf2 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -1072,7 +1072,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) WREG32(CP_DEBUG, (1 << 27)); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32(SCRATCH_UMSK, 0xff); @@ -1089,7 +1089,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) #endif WREG32(cp_rb_cntl[i], rb_cntl); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 47634f27f2e5..ebd69562ef6c 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -459,7 +459,7 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *r * * @ring: radeon_ring structure holding ring information * - * Reset the driver's copy of the wtpr (all asics). + * Reset the driver's copy of the wptr (all asics). */ void radeon_ring_undo(struct radeon_ring *ring) { @@ -503,7 +503,7 @@ void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring * } /** - * radeon_ring_force_activity - update lockup variables + * radeon_ring_lockup_update - update lockup variables * * @ring: radeon_ring structure holding ring information * diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 7e835d94df4a..ef683653f0b7 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -2012,7 +2012,7 @@ static int si_cp_resume(struct radeon_device *rdev) ring->wptr = 0; WREG32(CP_RB0_WPTR, ring->wptr); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); @@ -2045,7 +2045,7 @@ static int si_cp_resume(struct radeon_device *rdev) ring->wptr = 0; WREG32(CP_RB1_WPTR, ring->wptr); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); @@ -2071,7 +2071,7 @@ static int si_cp_resume(struct radeon_device *rdev) ring->wptr = 0; WREG32(CP_RB2_WPTR, ring->wptr); - /* set the wb address wether it's enabled or not */ + /* set the wb address whether it's enabled or not */ WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |