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path: root/drivers/media/video/cx18/cx18-firmware.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-firmware.c')
-rw-r--r--drivers/media/video/cx18/cx18-firmware.c140
1 files changed, 75 insertions, 65 deletions
diff --git a/drivers/media/video/cx18/cx18-firmware.c b/drivers/media/video/cx18/cx18-firmware.c
index 78fadd2ada5d..51534428cd00 100644
--- a/drivers/media/video/cx18/cx18-firmware.c
+++ b/drivers/media/video/cx18/cx18-firmware.c
@@ -20,6 +20,7 @@
*/
#include "cx18-driver.h"
+#include "cx18-io.h"
#include "cx18-scb.h"
#include "cx18-irq.h"
#include "cx18-firmware.h"
@@ -113,11 +114,11 @@ static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
src = (const u32 *)fw->data;
for (i = 0; i < fw->size; i += 4096) {
- setup_page(i);
+ cx18_setup_page(cx, i);
for (j = i; j < fw->size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
- __raw_writel(*src, dst);
- if (__raw_readl(dst) != *src) {
+ cx18_raw_writel(cx, *src, dst);
+ if (cx18_raw_readl(cx, dst) != *src) {
CX18_ERR("Mismatch at offset %x\n", i);
release_firmware(fw);
return -EIO;
@@ -170,12 +171,15 @@ static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx)
if (offset + seghdr.size > sz)
break;
for (i = 0; i < seghdr.size; i += 4096) {
- setup_page(offset + i);
+ cx18_setup_page(cx, offset + i);
for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
- __raw_writel(src[(offset + j) / 4], dst + seghdr.addr + j);
- if (__raw_readl(dst + seghdr.addr + j) != src[(offset + j) / 4]) {
- CX18_ERR("Mismatch at offset %x\n", offset + j);
+ cx18_raw_writel(cx, src[(offset + j) / 4],
+ dst + seghdr.addr + j);
+ if (cx18_raw_readl(cx, dst + seghdr.addr + j)
+ != src[(offset + j) / 4]) {
+ CX18_ERR("Mismatch at offset %x\n",
+ offset + j);
release_firmware(fw);
return -EIO;
}
@@ -189,43 +193,45 @@ static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx)
size = fw->size;
release_firmware(fw);
/* Clear bit0 for APU to start from 0 */
- write_reg(read_reg(0xc72030) & ~1, 0xc72030);
+ cx18_write_reg(cx, cx18_read_reg(cx, 0xc72030) & ~1, 0xc72030);
return size;
}
void cx18_halt_firmware(struct cx18 *cx)
{
CX18_DEBUG_INFO("Preparing for firmware halt.\n");
- write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
- write_reg(0x00020002, CX18_ADEC_CONTROL);
+ cx18_write_reg(cx, 0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
+ cx18_write_reg(cx, 0x00020002, CX18_ADEC_CONTROL);
}
void cx18_init_power(struct cx18 *cx, int lowpwr)
{
/* power-down Spare and AOM PLLs */
/* power-up fast, slow and mpeg PLLs */
- write_reg(0x00000008, CX18_PLL_POWER_DOWN);
+ cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
/* ADEC out of sleep */
- write_reg(0x00020000, CX18_ADEC_CONTROL);
+ cx18_write_reg(cx, 0x00020000, CX18_ADEC_CONTROL);
/* The fast clock is at 200/245 MHz */
- write_reg(lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
- write_reg(lowpwr ? 0x1EFBF37 : 0x038E3D7, CX18_FAST_CLOCK_PLL_FRAC);
+ cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
+ cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
+ CX18_FAST_CLOCK_PLL_FRAC);
- write_reg(2, CX18_FAST_CLOCK_PLL_POST);
- write_reg(1, CX18_FAST_CLOCK_PLL_PRESCALE);
- write_reg(4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
+ cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
+ cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
+ cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
/* set slow clock to 125/120 MHz */
- write_reg(lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
- write_reg(lowpwr ? 0xEBAF05 : 0x18618A8, CX18_SLOW_CLOCK_PLL_FRAC);
- write_reg(4, CX18_SLOW_CLOCK_PLL_POST);
+ cx18_write_reg(cx, lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
+ cx18_write_reg(cx, lowpwr ? 0xEBAF05 : 0x18618A8,
+ CX18_SLOW_CLOCK_PLL_FRAC);
+ cx18_write_reg(cx, 4, CX18_SLOW_CLOCK_PLL_POST);
/* mpeg clock pll 54MHz */
- write_reg(0xF, CX18_MPEG_CLOCK_PLL_INT);
- write_reg(0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
- write_reg(8, CX18_MPEG_CLOCK_PLL_POST);
+ cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
+ cx18_write_reg(cx, 0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
+ cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
/* Defaults */
/* APU = SC or SC/2 = 125/62.5 */
@@ -242,81 +248,84 @@ void cx18_init_power(struct cx18 *cx, int lowpwr)
/* VFC = disabled */
/* USB = disabled */
- write_reg(lowpwr ? 0xFFFF0020 : 0x00060004, CX18_CLOCK_SELECT1);
- write_reg(lowpwr ? 0xFFFF0004 : 0x00060006, CX18_CLOCK_SELECT2);
+ cx18_write_reg(cx, lowpwr ? 0xFFFF0020 : 0x00060004,
+ CX18_CLOCK_SELECT1);
+ cx18_write_reg(cx, lowpwr ? 0xFFFF0004 : 0x00060006,
+ CX18_CLOCK_SELECT2);
- write_reg(0xFFFF0002, CX18_HALF_CLOCK_SELECT1);
- write_reg(0xFFFF0104, CX18_HALF_CLOCK_SELECT2);
+ cx18_write_reg(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1);
+ cx18_write_reg(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2);
- write_reg(0xFFFF9026, CX18_CLOCK_ENABLE1);
- write_reg(0xFFFF3105, CX18_CLOCK_ENABLE2);
+ cx18_write_reg(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1);
+ cx18_write_reg(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2);
}
void cx18_init_memory(struct cx18 *cx)
{
cx18_msleep_timeout(10, 0);
- write_reg(0x10000, CX18_DDR_SOFT_RESET);
+ cx18_write_reg(cx, 0x10000, CX18_DDR_SOFT_RESET);
cx18_msleep_timeout(10, 0);
- write_reg(cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
+ cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
cx18_msleep_timeout(10, 0);
- write_reg(cx->card->ddr.refresh, CX18_DDR_REFRESH);
- write_reg(cx->card->ddr.timing1, CX18_DDR_TIMING1);
- write_reg(cx->card->ddr.timing2, CX18_DDR_TIMING2);
+ cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
+ cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
+ cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
cx18_msleep_timeout(10, 0);
/* Initialize DQS pad time */
- write_reg(cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
- write_reg(cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
+ cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
+ cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
cx18_msleep_timeout(10, 0);
- write_reg(0x20000, CX18_DDR_SOFT_RESET);
+ cx18_write_reg(cx, 0x20000, CX18_DDR_SOFT_RESET);
cx18_msleep_timeout(10, 0);
/* use power-down mode when idle */
- write_reg(0x00000010, CX18_DDR_POWER_REG);
-
- write_reg(0x10001, CX18_REG_BUS_TIMEOUT_EN);
-
- write_reg(0x48, CX18_DDR_MB_PER_ROW_7);
- write_reg(0xE0000, CX18_DDR_BASE_63_ADDR);
-
- write_reg(0x00000101, CX18_WMB_CLIENT02); /* AO */
- write_reg(0x00000101, CX18_WMB_CLIENT09); /* AI2 */
- write_reg(0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
- write_reg(0x00000101, CX18_WMB_CLIENT06); /* AI1 */
- write_reg(0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
- write_reg(0x00000101, CX18_WMB_CLIENT10); /* ME */
- write_reg(0x00000101, CX18_WMB_CLIENT12); /* ENC */
- write_reg(0x00000101, CX18_WMB_CLIENT13); /* PK */
- write_reg(0x00000101, CX18_WMB_CLIENT11); /* RC */
- write_reg(0x00000101, CX18_WMB_CLIENT14); /* AVO */
+ cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
+
+ cx18_write_reg(cx, 0x10001, CX18_REG_BUS_TIMEOUT_EN);
+
+ cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
+ cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
+
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
+ cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
}
int cx18_firmware_init(struct cx18 *cx)
{
/* Allow chip to control CLKRUN */
- write_reg(0x5, CX18_DSP0_INTERRUPT_MASK);
+ cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
- write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
+ cx18_write_reg(cx, 0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
cx18_msleep_timeout(1, 0);
- sw1_irq_enable(IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
- sw2_irq_enable(IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
+ cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
+ cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
/* Only if the processor is not running */
- if (read_reg(CX18_PROC_SOFT_RESET) & 8) {
+ if (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) {
int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
cx->enc_mem, cx);
- write_enc(0xE51FF004, 0);
- write_enc(0xa00000, 4); /* todo: not hardcoded */
- write_reg(0x00010000, CX18_PROC_SOFT_RESET); /* Start APU */
+ cx18_write_enc(cx, 0xE51FF004, 0);
+ cx18_write_enc(cx, 0xa00000, 4); /* todo: not hardcoded */
+ /* Start APU */
+ cx18_write_reg(cx, 0x00010000, CX18_PROC_SOFT_RESET);
cx18_msleep_timeout(500, 0);
sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
@@ -326,9 +335,10 @@ int cx18_firmware_init(struct cx18 *cx)
int retries = 0;
/* start the CPU */
- write_reg(0x00080000, CX18_PROC_SOFT_RESET);
+ cx18_write_reg(cx, 0x00080000, CX18_PROC_SOFT_RESET);
while (retries++ < 50) { /* Loop for max 500mS */
- if ((read_reg(CX18_PROC_SOFT_RESET) & 1) == 0)
+ if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET)
+ & 1) == 0)
break;
cx18_msleep_timeout(10, 0);
}
@@ -342,6 +352,6 @@ int cx18_firmware_init(struct cx18 *cx)
return -EIO;
}
/* initialize GPIO */
- write_reg(0x14001400, 0xC78110);
+ cx18_write_reg(cx, 0x14001400, 0xC78110);
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-14 14:10:11 +0000