diff options
Diffstat (limited to 'drivers/mfd')
| -rw-r--r-- | drivers/mfd/twl6040.c | 92 | ||||
| -rw-r--r-- | drivers/mfd/wm5110-tables.c | 139 |
2 files changed, 224 insertions, 7 deletions
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c index 0779d5ab9ab1..51b6df1a7949 100644 --- a/drivers/mfd/twl6040.c +++ b/drivers/mfd/twl6040.c @@ -44,6 +44,54 @@ #define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1) #define TWL6040_NUM_SUPPLIES (2) +static struct reg_default twl6040_defaults[] = { + { 0x01, 0x4B }, /* REG_ASICID (ro) */ + { 0x02, 0x00 }, /* REG_ASICREV (ro) */ + { 0x03, 0x00 }, /* REG_INTID */ + { 0x04, 0x00 }, /* REG_INTMR */ + { 0x05, 0x00 }, /* REG_NCPCTRL */ + { 0x06, 0x00 }, /* REG_LDOCTL */ + { 0x07, 0x60 }, /* REG_HPPLLCTL */ + { 0x08, 0x00 }, /* REG_LPPLLCTL */ + { 0x09, 0x4A }, /* REG_LPPLLDIV */ + { 0x0A, 0x00 }, /* REG_AMICBCTL */ + { 0x0B, 0x00 }, /* REG_DMICBCTL */ + { 0x0C, 0x00 }, /* REG_MICLCTL */ + { 0x0D, 0x00 }, /* REG_MICRCTL */ + { 0x0E, 0x00 }, /* REG_MICGAIN */ + { 0x0F, 0x1B }, /* REG_LINEGAIN */ + { 0x10, 0x00 }, /* REG_HSLCTL */ + { 0x11, 0x00 }, /* REG_HSRCTL */ + { 0x12, 0x00 }, /* REG_HSGAIN */ + { 0x13, 0x00 }, /* REG_EARCTL */ + { 0x14, 0x00 }, /* REG_HFLCTL */ + { 0x15, 0x00 }, /* REG_HFLGAIN */ + { 0x16, 0x00 }, /* REG_HFRCTL */ + { 0x17, 0x00 }, /* REG_HFRGAIN */ + { 0x18, 0x00 }, /* REG_VIBCTLL */ + { 0x19, 0x00 }, /* REG_VIBDATL */ + { 0x1A, 0x00 }, /* REG_VIBCTLR */ + { 0x1B, 0x00 }, /* REG_VIBDATR */ + { 0x1C, 0x00 }, /* REG_HKCTL1 */ + { 0x1D, 0x00 }, /* REG_HKCTL2 */ + { 0x1E, 0x00 }, /* REG_GPOCTL */ + { 0x1F, 0x00 }, /* REG_ALB */ + { 0x20, 0x00 }, /* REG_DLB */ + /* 0x28, REG_TRIM1 */ + /* 0x29, REG_TRIM2 */ + /* 0x2A, REG_TRIM3 */ + /* 0x2B, REG_HSOTRIM */ + /* 0x2C, REG_HFOTRIM */ + { 0x2D, 0x08 }, /* REG_ACCCTL */ + { 0x2E, 0x00 }, /* REG_STATUS (ro) */ +}; + +struct reg_default twl6040_patch[] = { + /* Select I2C bus access to dual access registers */ + { TWL6040_REG_ACCCTL, 0x09 }, +}; + + static bool twl6040_has_vibra(struct device_node *node) { #ifdef CONFIG_OF @@ -238,6 +286,9 @@ int twl6040_power(struct twl6040 *twl6040, int on) if (twl6040->power_count++) goto out; + /* Allow writes to the chip */ + regcache_cache_only(twl6040->regmap, false); + if (gpio_is_valid(twl6040->audpwron)) { /* use automatic power-up sequence */ ret = twl6040_power_up_automatic(twl6040); @@ -253,6 +304,10 @@ int twl6040_power(struct twl6040 *twl6040, int on) goto out; } } + + /* Sync with the HW */ + regcache_sync(twl6040->regmap); + /* Default PLL configuration after power up */ twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; twl6040->sysclk = 19200000; @@ -279,6 +334,11 @@ int twl6040_power(struct twl6040 *twl6040, int on) /* use manual power-down sequence */ twl6040_power_down_manual(twl6040); } + + /* Set regmap to cache only and mark it as dirty */ + regcache_cache_only(twl6040->regmap, true); + regcache_mark_dirty(twl6040->regmap); + twl6040->sysclk = 0; twl6040->mclk = 0; } @@ -490,9 +550,24 @@ static bool twl6040_readable_reg(struct device *dev, unsigned int reg) static bool twl6040_volatile_reg(struct device *dev, unsigned int reg) { switch (reg) { - case TWL6040_REG_VIBCTLL: - case TWL6040_REG_VIBCTLR: - case TWL6040_REG_INTMR: + case TWL6040_REG_ASICID: + case TWL6040_REG_ASICREV: + case TWL6040_REG_INTID: + case TWL6040_REG_LPPLLCTL: + case TWL6040_REG_HPPLLCTL: + case TWL6040_REG_STATUS: + return true; + default: + return false; + } +} + +static bool twl6040_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case TWL6040_REG_ASICID: + case TWL6040_REG_ASICREV: + case TWL6040_REG_STATUS: return false; default: return true; @@ -502,10 +577,15 @@ static bool twl6040_volatile_reg(struct device *dev, unsigned int reg) static struct regmap_config twl6040_regmap_config = { .reg_bits = 8, .val_bits = 8, + + .reg_defaults = twl6040_defaults, + .num_reg_defaults = ARRAY_SIZE(twl6040_defaults), + .max_register = TWL6040_REG_STATUS, /* 0x2e */ .readable_reg = twl6040_readable_reg, .volatile_reg = twl6040_volatile_reg, + .writeable_reg = twl6040_writeable_reg, .cache_type = REGCACHE_RBTREE, }; @@ -624,6 +704,8 @@ static int twl6040_probe(struct i2c_client *client, /* dual-access registers controlled by I2C only */ twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL); + regmap_register_patch(twl6040->regmap, twl6040_patch, + ARRAY_SIZE(twl6040_patch)); /* * The main functionality of twl6040 to provide audio on OMAP4+ systems. @@ -656,6 +738,10 @@ static int twl6040_probe(struct i2c_client *client, cell->name = "twl6040-gpo"; children++; + /* The chip is powered down so mark regmap to cache only and dirty */ + regcache_cache_only(twl6040->regmap, true); + regcache_mark_dirty(twl6040->regmap); + ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children, NULL, 0, NULL); if (ret) diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c index bf8b3b5ad1fe..abd6713de7b0 100644 --- a/drivers/mfd/wm5110-tables.c +++ b/drivers/mfd/wm5110-tables.c @@ -14,6 +14,7 @@ #include <linux/mfd/arizona/core.h> #include <linux/mfd/arizona/registers.h> +#include <linux/device.h> #include "arizona.h" @@ -524,6 +525,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000300, 0x0000 }, /* R768 - Input Enables */ { 0x00000308, 0x0000 }, /* R776 - Input Rate */ { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ + { 0x0000030C, 0x0002 }, /* R780 - HPF Control */ { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ @@ -545,6 +547,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000328, 0x2000 }, /* R808 - IN4L Control */ { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */ { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */ + { 0x0000032C, 0x0000 }, /* R812 - IN4R Control */ { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */ { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */ { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ @@ -598,6 +601,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */ { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */ { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */ + { 0x00000440, 0x8FFF }, /* R1088 - DRE Enable */ { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */ @@ -882,6 +886,38 @@ static const struct reg_default wm5110_reg_default[] = { { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ + { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */ + { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */ + { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */ + { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */ + { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */ + { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */ + { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */ + { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */ + { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */ + { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */ + { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */ + { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */ + { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */ + { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */ + { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */ + { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */ + { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */ + { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */ + { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */ + { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */ + { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */ + { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */ + { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */ + { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */ + { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */ + { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */ + { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */ + { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */ + { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */ + { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */ + { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */ + { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */ { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ @@ -1342,6 +1378,64 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */ }; +static bool wm5110_is_rev_b_adsp_memory(unsigned int reg) +{ + if ((reg >= 0x100000 && reg < 0x103000) || + (reg >= 0x180000 && reg < 0x181000) || + (reg >= 0x190000 && reg < 0x192000) || + (reg >= 0x1a8000 && reg < 0x1a9000) || + (reg >= 0x200000 && reg < 0x209000) || + (reg >= 0x280000 && reg < 0x281000) || + (reg >= 0x290000 && reg < 0x29a000) || + (reg >= 0x2a8000 && reg < 0x2aa000) || + (reg >= 0x300000 && reg < 0x30f000) || + (reg >= 0x380000 && reg < 0x382000) || + (reg >= 0x390000 && reg < 0x39e000) || + (reg >= 0x3a8000 && reg < 0x3b6000) || + (reg >= 0x400000 && reg < 0x403000) || + (reg >= 0x480000 && reg < 0x481000) || + (reg >= 0x490000 && reg < 0x492000) || + (reg >= 0x4a8000 && reg < 0x4a9000)) + return true; + else + return false; +} + +static bool wm5110_is_rev_d_adsp_memory(unsigned int reg) +{ + if ((reg >= 0x100000 && reg < 0x106000) || + (reg >= 0x180000 && reg < 0x182000) || + (reg >= 0x190000 && reg < 0x198000) || + (reg >= 0x1a8000 && reg < 0x1aa000) || + (reg >= 0x200000 && reg < 0x20f000) || + (reg >= 0x280000 && reg < 0x282000) || + (reg >= 0x290000 && reg < 0x29c000) || + (reg >= 0x2a6000 && reg < 0x2b4000) || + (reg >= 0x300000 && reg < 0x30f000) || + (reg >= 0x380000 && reg < 0x382000) || + (reg >= 0x390000 && reg < 0x3a2000) || + (reg >= 0x3a6000 && reg < 0x3b4000) || + (reg >= 0x400000 && reg < 0x406000) || + (reg >= 0x480000 && reg < 0x482000) || + (reg >= 0x490000 && reg < 0x498000) || + (reg >= 0x4a8000 && reg < 0x4aa000)) + return true; + else + return false; +} + +static bool wm5110_is_adsp_memory(struct device *dev, unsigned int reg) +{ + struct arizona *arizona = dev_get_drvdata(dev); + + switch (arizona->rev) { + case 0 ... 2: + return wm5110_is_rev_b_adsp_memory(reg); + default: + return wm5110_is_rev_d_adsp_memory(reg); + } +} + static bool wm5110_readable_register(struct device *dev, unsigned int reg) { switch (reg) { @@ -1460,6 +1554,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_INPUT_ENABLES_STATUS: case ARIZONA_INPUT_RATE: case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: case ARIZONA_IN1L_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_1L: case ARIZONA_DMIC1L_CONTROL: @@ -1481,6 +1576,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_IN4L_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_4L: case ARIZONA_DMIC4L_CONTROL: + case ARIZONA_IN4R_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_4R: case ARIZONA_DMIC4R_CONTROL: case ARIZONA_OUTPUT_ENABLES_1: @@ -1536,6 +1632,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DAC_DIGITAL_VOLUME_6R: case ARIZONA_DAC_VOLUME_LIMIT_6R: case ARIZONA_NOISE_GATE_SELECT_6R: + case ARIZONA_DRE_ENABLE: case ARIZONA_DAC_AEC_CONTROL_1: case ARIZONA_NOISE_GATE_CONTROL: case ARIZONA_PDM_SPK1_CTRL_1: @@ -1820,6 +1917,38 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: @@ -2331,7 +2460,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DSP4_SCRATCH_3: return true; default: - return false; + return wm5110_is_adsp_memory(dev, reg); } } @@ -2407,16 +2536,18 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg) case ARIZONA_DSP4_SCRATCH_3: return true; default: - return false; + return wm5110_is_adsp_memory(dev, reg); } } +#define WM5110_MAX_REGISTER 0x4a9fff + const struct regmap_config wm5110_spi_regmap = { .reg_bits = 32, .pad_bits = 16, .val_bits = 16, - .max_register = ARIZONA_DSP1_STATUS_2, + .max_register = WM5110_MAX_REGISTER, .readable_reg = wm5110_readable_register, .volatile_reg = wm5110_volatile_register, @@ -2430,7 +2561,7 @@ const struct regmap_config wm5110_i2c_regmap = { .reg_bits = 32, .val_bits = 16, - .max_register = ARIZONA_DSP1_STATUS_2, + .max_register = WM5110_MAX_REGISTER, .readable_reg = wm5110_readable_register, .volatile_reg = wm5110_volatile_register, |