diff options
Diffstat (limited to 'drivers/net/wireless')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-3945.c | 16 | ||||
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-prph.h | 12 |
2 files changed, 20 insertions, 8 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index 154f2a258db2..aec564d976a5 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c @@ -805,18 +805,18 @@ static int iwl3945_tx_reset(struct iwl_priv *priv) } /* bypass mode */ - iwl_write_prph(priv, SCD_MODE_REG, 0x2); + iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); /* RA 0 is active */ - iwl_write_prph(priv, SCD_ARASTAT_REG, 0x01); + iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); /* all 6 fifo are active */ - iwl_write_prph(priv, SCD_TXFACT_REG, 0x3f); + iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); - iwl_write_prph(priv, SCD_SBYP_MODE_1_REG, 0x010000); - iwl_write_prph(priv, SCD_SBYP_MODE_2_REG, 0x030002); - iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004); - iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005); + iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); + iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); + iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); + iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); iwl_write_direct32(priv, FH_TSSR_CBB_BASE, priv->hw_setting.shared_phys); @@ -1044,7 +1044,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv) } /* stop SCD */ - iwl_write_prph(priv, SCD_MODE_REG, 0); + iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); /* reset TFD queues */ for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index 9639832ad0ff..ee4af3f04db3 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h @@ -225,6 +225,18 @@ #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) #define BSM_SRAM_SIZE (1024) /* bytes */ +/* ALM SCD */ +/* SCD (Scheduler) */ +#define ALM_SCD_BASE (PRPH_BASE + 0x2E00) +#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) +#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) +#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010) +#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014) +#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020) +#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) +#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) + + /* 4965 SCD memory mapped registers */ #define KDR_SCD_BASE (PRPH_BASE + 0xa02c00) |