diff options
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/8250.c | 10 | ||||
| -rw-r--r-- | drivers/serial/Kconfig | 55 | ||||
| -rw-r--r-- | drivers/serial/Makefile | 4 | ||||
| -rw-r--r-- | drivers/serial/mxc_uart.c | 1950 | ||||
| -rw-r--r-- | drivers/serial/mxc_uart_early.c | 253 | ||||
| -rw-r--r-- | drivers/serial/mxc_uart_reg.h | 128 | ||||
| -rw-r--r-- | drivers/serial/stmp-app.c | 1081 | ||||
| -rw-r--r-- | drivers/serial/stmp-app.h | 82 | ||||
| -rw-r--r-- | drivers/serial/stmp-dbg.c | 840 | ||||
| -rw-r--r-- | drivers/serial/stmp-dbg.h | 180 |
10 files changed, 4583 insertions, 0 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index fb867a9f55e9..d5da26f34cee 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -942,6 +942,10 @@ static void autoconfig_16550a(struct uart_8250_port *up) * Check for presence of the EFR when DLAB is set. * Only ST16C650V1 UARTs pass this test. */ +#ifndef CONFIG_ARCH_MXC + /* This test fails as EFR reads 0, but our uart requires LCR=0xBF + * to access EFR. + */ serial_outp(up, UART_LCR, UART_LCR_DLAB); if (serial_in(up, UART_EFR) == 0) { serial_outp(up, UART_EFR, 0xA8); @@ -955,6 +959,7 @@ static void autoconfig_16550a(struct uart_8250_port *up) serial_outp(up, UART_EFR, 0); return; } +#endif /* * Maybe it requires 0xbf to be written to the LCR. @@ -1477,7 +1482,12 @@ static void transmit_chars(struct uart_8250_port *up) count = up->tx_loadsz; do { +#ifdef CONFIG_ARCH_MXC + /* Seems like back-to-back accesses are a problem */ + serial_out_sync(up, UART_TX, xmit->buf[xmit->tail]); +#else serial_out(up, UART_TX, xmit->buf[xmit->tail]); +#endif xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); up->port.icount.tx++; if (uart_circ_empty(xmit)) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6553833c12db..669c6373e6d6 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -304,6 +304,61 @@ config SERIAL_AMBA_PL010_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) +config SERIAL_MXC + tristate "MXC Internal serial port support" + depends on ARCH_MXC + select SERIAL_CORE + help + This selects the Freescale Semiconductor MXC Internal UART driver. + If unsure, say N. + +config SERIAL_MXC_CONSOLE + bool "Support for console on a MXC/MX27/MX21 Internal serial port" + depends on SERIAL_MXC=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use an MXC Internal UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttymxc". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_STMP_DBG + tristate "STMP debug serial port support" + depends on ARCH_STMP3XXX + select SERIAL_CORE + help + Driver for Sigmatel 36XX/37XX internal debug serial port + +config SERIAL_STMP_DBG_CONSOLE + bool "Support for console on STMP37XX DBG serial port" + depends on SERIAL_STMP_DBG=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use the STMP36XX/37XX debug serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyAM0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_STMP_APP + tristate "STMP app serial port support" + depends on ARCH_STMP3XXX + select SERIAL_CORE + help + Driver for Sigmatel 36XX/37XX internal application serial port + config SERIAL_AMBA_PL011 tristate "ARM AMBA PL011 serial port support" depends on ARM_AMBA diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index d5a29981c6c4..289f41c24efe 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -73,6 +73,10 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o +obj-$(CONFIG_SERIAL_MXC) += mxc_uart.o +obj-$(CONFIG_SERIAL_MXC_CONSOLE) += mxc_uart_early.o +obj-$(CONFIG_SERIAL_STMP_DBG) += stmp-dbg.o +obj-$(CONFIG_SERIAL_STMP_APP) += stmp-app.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o diff --git a/drivers/serial/mxc_uart.c b/drivers/serial/mxc_uart.c new file mode 100644 index 000000000000..f212ba96cd5c --- /dev/null +++ b/drivers/serial/mxc_uart.c @@ -0,0 +1,1950 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * @ingroup UART + */ + +/* + * Include Files + */ +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/tty.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/console.h> +#include <linux/platform_device.h> +#include <linux/sysrq.h> +#include <linux/dma-mapping.h> +#include <linux/clk.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/dma.h> +#include <asm/div64.h> +#include <mach/hardware.h> +#include <mach/mxc_uart.h> + +#if defined(CONFIG_SERIAL_MXC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif +#define SERIAL_MXC_MAJOR 207 +#define SERIAL_MXC_MINOR 16 +#define MXC_ISR_PASS_LIMIT 256 +#define UART_CREAD_BIT 256 + +#define MXC_UART_NR 8 + +/* IRDA minimum pulse duration in micro seconds */ +#define MIN_PULSE_DUR 2 +/* + * Transmit DMA buffer size is set to 1024 bytes, this is limited + * by UART_XMIT_SIZE. + */ +#define TXDMA_BUFF_SIZE UART_XMIT_SIZE +/* + * Receive DMA sub-buffer size + */ +#define RXDMA_BUFF_SIZE 128 + +/*! + * This structure is used to store the information for DMA data transfer. + */ +typedef struct { + /*! + * Holds the read channel number. + */ + int rd_channel; + /*! + * Holds the write channel number. + */ + int wr_channel; + /*! + * UART Transmit Event ID + */ + int tx_event_id; + /*! + * UART Receive Event ID + */ + int rx_event_id; + /*! + * DMA Transmit tasklet + */ + struct tasklet_struct dma_tx_tasklet; + /*! + * Flag indicates if the channel is in use + */ + int dma_txchnl_inuse; +} dma_info; + +/*! + * This is used to indicate if we want echo cancellation in the Irda mode. + */ +static int echo_cancel; +extern void gpio_uart_active(int port, int no_irda); +extern void gpio_uart_inactive(int port, int no_irda); +extern void config_uartdma_event(int port); + +static uart_mxc_port *mxc_ports[MXC_UART_NR]; + +/*! + * This array holds the DMA channel information for each MXC UART + */ +static dma_info dma_list[MXC_UART_NR]; + +/*! + * This function is called by the core driver to stop UART transmission. + * This might be due to the TTY layer indicating that the user wants to stop + * transmission. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_stop_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Disable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_TXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * DMA Transmit tasklet method is scheduled on completion of a DMA transmit + * to send out any more data that is available in the UART xmit buffer. + * + * @param arg driver private data + */ +static void dma_tx_do_tasklet(unsigned long arg) +{ + uart_mxc_port *umxc = (uart_mxc_port *) arg; + struct circ_buf *xmit = &umxc->port.info->xmit; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + unsigned long flags; + + spin_lock_irqsave(&umxc->port.lock, flags); + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + (UART_XMIT_SIZE - xmit->tail), + xmit->buf, xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, tx_num); + } + umxc->tx_handle = dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + + writechnl_request.dst_addr = umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + + if ((mxc_dma_config(dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line].wr_channel); + } + } else { + /* No more data available in the xmit queue, clear the flag */ + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * DMA Write callback is called by the SDMA controller after it has sent out all + * the data from the user buffer. This function updates the xmit buffer pointers. + * + * @param arg driver private data + * @param error any DMA error + * @param count amount of data that was transferred + */ +static void mxcuart_dma_writecallback(void *arg, int error, unsigned int count) +{ + uart_mxc_port *umxc = arg; + struct circ_buf *xmit = &umxc->port.info->xmit; + int tx_num; + + if (error != MXC_DMA_TRANSFER_ERROR) { + tx_num = count; + umxc->port.icount.tx += tx_num; + xmit->tail = (xmit->tail + tx_num) & (UART_XMIT_SIZE - 1); + } + + dma_unmap_single(umxc->port.dev, umxc->tx_handle, TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + tx_num = uart_circ_chars_pending(xmit); + /* Schedule a tasklet to send out the pending characters */ + if (tx_num > 0) { + tasklet_schedule(&dma_list[umxc->port.line].dma_tx_tasklet); + } else { + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + if (tx_num < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } +} + +/*! + * This function is called by the core driver to start transmitting characters. + * This function enables the transmit interrupts. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_start_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + struct circ_buf *xmit = &umxc->port.info->xmit; + volatile unsigned int cr1; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Enable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + /* + * If the channel is in use then return immediately and use + * the dma_tx tasklet to transfer queued data when current DMA + * transfer is complete + */ + if (dma_list[umxc->port.line].dma_txchnl_inuse == 1) { + return; + } + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + dma_list[umxc->port.line].dma_txchnl_inuse = 1; + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + + (UART_XMIT_SIZE - xmit->tail), xmit->buf, + xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + tx_num); + } + umxc->tx_handle = + dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, DMA_TO_DEVICE); + + writechnl_request.dst_addr = + umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + if ((mxc_dma_config + (dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line]. + wr_channel); + } + cr1 |= MXC_UARTUCR1_TXDMAEN; + } + } else { + cr1 |= MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to stop receiving characters; the + * port is in the process of being closed. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_stop_rx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_RXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_RRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to enable the modem status + * interrupts. If the port is configured to be in DTE mode then it enables the + * DCDDELT and RIDELT interrupts in addition to the DTRDEN interrupt. The RTSDEN + * interrupt is enabled only for interrupt-driven hardware flow control. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_enable_ms(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1, cr3; + + /* + * RTS interrupt is enabled only if we are using interrupt-driven + * software controlled hardware flow control + */ + if (umxc->hardware_flow == 0) { + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + cr1 |= MXC_UARTUCR1_RTSDEN; + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + } + cr3 = readl(umxc->port.membase + MXC_UARTUCR3); + cr3 |= MXC_UARTUCR3_DTRDEN; + if (umxc->mode == MODE_DTE) { + cr3 |= MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI; + } + writel(cr3, umxc->port.membase + MXC_UARTUCR3); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the receive fifo data level is above the set threshold. The + * function reads the character and queues them into the TTY layers read + * buffer. The function also looks for break characters, parity and framing + * errors in the received character and sets the appropriate flag in the TTY + * receive buffer. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_rx_chars(uart_mxc_port * umxc) +{ + volatile unsigned int ch, sr2; + unsigned int status, flag, max_count = 256; + + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + while (((sr2 & MXC_UARTUSR2_RDR) == 1) && (max_count-- > 0)) { + ch = readl(umxc->port.membase + MXC_UARTURXD); + + flag = TTY_NORMAL; + status = ch | UART_CREAD_BIT; + ch &= 0xFF; /* Clear the upper bits */ + umxc->port.icount.rx++; + + /* + * Check to see if there is an error in the received + * character. Perform the appropriate actions based on the + * error bit that was set. + */ + if (status & MXC_UARTURXD_ERR) { + if (status & MXC_UARTURXD_BRK) { + /* + * Clear the frame and parity error bits + * as these always get set on receiving a + * break character + */ + status &= ~(MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR); + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto ignore_char; + } + } else if (status & MXC_UARTURXD_FRMERR) { + umxc->port.icount.frame++; + } else if (status & MXC_UARTURXD_PRERR) { + umxc->port.icount.parity++; + } + if (status & MXC_UARTURXD_OVRRUN) { + umxc->port.icount.overrun++; + } + + status &= umxc->port.read_status_mask; + + if (status & MXC_UARTURXD_BRK) { + flag = TTY_BREAK; + } else if (status & MXC_UARTURXD_FRMERR) { + flag = TTY_FRAME; + } else if (status & MXC_UARTURXD_PRERR) { + flag = TTY_PARITY; + } + } + + if (uart_handle_sysrq_char(&umxc->port, ch)) { + goto ignore_char; + } + + uart_insert_char(&umxc->port, status, MXC_UARTURXD_OVRRUN, ch, + flag); + ignore_char: + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + } + tty_flip_buffer_push(umxc->port.info->port.tty); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the transmit fifo is emptied below its set threshold and + * requires data. The function pulls characters from the TTY layers write + * buffer and writes it out to the UART transmit fifo. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_tx_chars(uart_mxc_port * umxc) +{ + struct circ_buf *xmit = &umxc->port.info->xmit; + int count; + + /* + * Transmit the XON/XOFF character if required + */ + if (umxc->port.x_char) { + writel(umxc->port.x_char, umxc->port.membase + MXC_UARTUTXD); + umxc->port.icount.tx++; + umxc->port.x_char = 0; + return; + } + + /* + * Check to see if there is any data to be sent and that the + * port has not been currently stopped by anything. + */ + if (uart_circ_empty(xmit) || uart_tx_stopped(&umxc->port)) { + mxcuart_stop_tx(&umxc->port); + return; + } + + count = umxc->port.fifosize - umxc->tx_threshold; + do { + writel(xmit->buf[xmit->tail], + umxc->port.membase + MXC_UARTUTXD); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + umxc->port.icount.tx++; + if (uart_circ_empty(xmit)) { + break; + } + } while (--count > 0); + + /* + * Check to see if we have flushed enough characters to ask for more + * to be sent to us, if so, we notify the user space that we can + * accept more data + */ + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } + + if (uart_circ_empty(xmit)) { + mxcuart_stop_tx(&umxc->port); + } +} + +/*! + * This function is called from the interrupt service routine if there is a + * change in the modem signals. This function handles these signal changes and + * also clears the appropriate status register bits. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param sr1 contents of status register 1 + * @param sr2 contents of status register 2 + */ +static void mxcuart_modem_status(uart_mxc_port * umxc, unsigned int sr1, + unsigned int sr2) +{ + if (umxc->mode == MODE_DTE) { + if (sr2 & MXC_UARTUSR2_DCDDELT) { + uart_handle_dcd_change(&umxc->port, + !(sr2 & MXC_UARTUSR2_DCDIN)); + } + if (sr2 & MXC_UARTUSR2_RIDELT) { + umxc->port.icount.rng++; + } + } + if (sr1 & MXC_UARTUSR1_DTRD) { + umxc->port.icount.dsr++; + } + if ((umxc->hardware_flow == 0) && (sr1 & MXC_UARTUSR1_RTSD)) { + uart_handle_cts_change(&umxc->port, sr1 & MXC_UARTUSR1_RTSS); + } + + wake_up_interruptible(&umxc->port.info->delta_msr_wait); +} + +/*! + * Interrupt service routine registered to handle the muxed ANDed interrupts. + * This routine is registered only in the case where the UART interrupts are + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in \b include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + volatile unsigned int sr1, sr2, cr1, cr; + unsigned int pass_counter = MXC_ISR_PASS_LIMIT; + unsigned int term_cond = 0; + int handled = 0; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + + do { + /* Clear the bits that triggered the interrupt */ + writel(sr1, umxc->port.membase + MXC_UARTUSR1); + writel(sr2, umxc->port.membase + MXC_UARTUSR2); + /* + * Read if there is data available + */ + if (sr2 & MXC_UARTUSR2_RDR) { + mxcuart_rx_chars(umxc); + } + + if ((sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD)) || + (sr2 & (MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT))) { + mxcuart_modem_status(umxc, sr1, sr2); + } + + /* + * Send data if there is data to be sent + */ + if ((cr1 & MXC_UARTUCR1_TRDYEN) && (sr1 & MXC_UARTUSR1_TRDY)) { + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete intr to reenable RX */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + mxcuart_tx_chars(umxc); + } + + if (pass_counter-- == 0) { + break; + } + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + /* + * If there is no data to send or receive and if there is no + * change in the modem status signals then quit the routine + */ + term_cond = sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD); + term_cond |= sr2 & (MXC_UARTUSR2_RDR | MXC_UARTUSR2_DCDDELT); + term_cond |= !(sr2 & MXC_UARTUSR2_TXFE); + } while (term_cond > 0); + + handled = 1; + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the transmit interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_tx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr2, cr; + + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete to reenable receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + + mxcuart_tx_chars(umxc); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the receive interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_rx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + mxcuart_rx_chars(umxc); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the master interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_mint_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + /* Clear the modem status interrupt bits */ + writel(MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD, + umxc->port.membase + MXC_UARTUSR1); + writel(MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT, + umxc->port.membase + MXC_UARTUSR2); + mxcuart_modem_status(umxc, sr1, sr2); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * This function is called by the core driver to test whether the transmitter + * fifo and shift register for the UART port are empty. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns TIOCSER_TEMT if it is empty, else returns 0. + */ +static unsigned int mxcuart_tx_empty(struct uart_port *port) +{ + volatile unsigned int sr2; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + sr2 = readl(port->membase + MXC_UARTUSR2); + spin_unlock_irqrestore(&port->lock, flags); + + return sr2 & MXC_UARTUSR2_TXDC ? TIOCSER_TEMT : 0; +} + +/*! + * This function is called by the core driver to get the current status of the + * modem input signals. The state of the output signals is not collected. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns an integer that contains the ORed value of the + * status of all the modem input signals or error. + */ +static unsigned int mxcuart_get_mctrl(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + unsigned int result = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr1 & MXC_UARTUSR1_RTSS) { + result |= TIOCM_CTS; + } + if (umxc->mode == MODE_DTE) { + if (!(sr2 & MXC_UARTUSR2_DCDIN)) { + result |= TIOCM_CAR; + } + if (!(sr2 & MXC_UARTUSR2_RIIN)) { + result |= TIOCM_RI; + } + } + return result; +} + +/*! + * This function is called by the core driver to set the state of the modem + * control lines. + * + * @param port the port structure for the UART passed in by the core driver + * @param mctrl the state that the modem control lines should be changed to + */ +static void mxcuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr2 = 0, cr3 = 0, uts = 0; + + cr2 = readl(port->membase + MXC_UARTUCR2); + cr3 = readl(port->membase + MXC_UARTUCR3); + uts = readl(port->membase + MXC_UARTUTS); + + if (mctrl & TIOCM_RTS) { + /* + * Return to hardware-driven hardware flow control if the + * option is enabled + */ + if (umxc->hardware_flow == 1) { + cr2 |= MXC_UARTUCR2_CTSC; + } else { + cr2 |= MXC_UARTUCR2_CTS; + cr2 &= ~MXC_UARTUCR2_CTSC; + } + } else { + cr2 &= ~(MXC_UARTUCR2_CTS | MXC_UARTUCR2_CTSC); + } + writel(cr2, port->membase + MXC_UARTUCR2); + + if (mctrl & TIOCM_DTR) { + cr3 |= MXC_UARTUCR3_DSR; + } else { + cr3 &= ~MXC_UARTUCR3_DSR; + } + writel(cr3, port->membase + MXC_UARTUCR3); + + if (mctrl & TIOCM_LOOP) { + if (umxc->ir_mode == IRDA) { + echo_cancel = 0; + } else { + uts |= MXC_UARTUTS_LOOP; + } + } else { + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + } else { + uts &= ~MXC_UARTUTS_LOOP; + } + } + writel(uts, port->membase + MXC_UARTUTS); +} + +/*! + * This function is called by the core driver to control the transmission of + * the break signal. If break_state is non-zero, the break signal is + * transmitted, the signal is terminated when another call is made with + * break_state set to 0. + * + * @param port the port structure for the UART passed in by the core + * driver + * @param break_state the requested state of the break signal + */ +static void mxcuart_break_ctl(struct uart_port *port, int break_state) +{ + volatile unsigned int cr1; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + cr1 = readl(port->membase + MXC_UARTUCR1); + if (break_state == -1) { + cr1 |= MXC_UARTUCR1_SNDBRK; + } else { + cr1 &= ~MXC_UARTUCR1_SNDBRK; + } + writel(cr1, port->membase + MXC_UARTUCR1); + spin_unlock_irqrestore(&port->lock, flags); +} + +/*! + * The read DMA callback, this method is called when the DMA buffer has received its + * data. This functions copies the data to the tty buffer and updates the tty buffer + * pointers. It also queues the DMA buffer back to the DMA system. + * + * @param arg driver private data + * @param error any DMA error + * @param cnt amount of data that was transferred + */ +static void mxcuart_dmaread_callback(void *arg, int error, unsigned int cnt) +{ + uart_mxc_port *umxc = arg; + struct tty_struct *tty = umxc->port.info->port.tty; + int buff_id, flip_cnt, num_bufs; + mxc_dma_requestbuf_t readchnl_request; + mxc_uart_rxdmamap *rx_buf_elem = NULL; + unsigned int sr1, sr2; + char flag; + + num_bufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + + buff_id = umxc->dma_rxbuf_id; + flag = TTY_NORMAL; + + if ((umxc->dma_rxbuf_id += 1) >= num_bufs) { + umxc->dma_rxbuf_id = 0; + } + + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + buff_id); + + if (error == MXC_DMA_TRANSFER_ERROR) { + + sr1 = __raw_readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = __raw_readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr2 & MXC_UARTUSR2_BRCD) { + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto drop_data; + } + } else if (sr1 & MXC_UARTUSR1_PARITYERR) { + umxc->port.icount.parity++; + } else if (sr1 & MXC_UARTUSR1_FRAMERR) { + umxc->port.icount.frame++; + } else if (sr2 & MXC_UARTUSR2_ORE) { + umxc->port.icount.overrun++; + + } + + if (umxc->port.read_status_mask & MXC_UARTURXD_BRK) { + if (sr2 & MXC_UARTUSR2_BRCD) + flag = TTY_BREAK; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_PRERR) { + if (sr1 & MXC_UARTUSR1_PARITYERR) + flag = TTY_PARITY; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_FRMERR) { + if (sr1 & MXC_UARTUSR1_FRAMERR) + flag = TTY_FRAME; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_OVRRUN) { + if (sr2 & MXC_UARTUSR2_ORE) + flag = TTY_OVERRUN; + } +/* By default clearing all error bits in status reg */ + __raw_writel((MXC_UARTUSR2_BRCD | MXC_UARTUSR2_ORE), + umxc->port.membase + MXC_UARTUSR2); + __raw_writel((MXC_UARTUSR1_PARITYERR | MXC_UARTUSR1_FRAMERR), + umxc->port.membase + MXC_UARTUSR1); + } + + flip_cnt = tty_buffer_request_room(tty, cnt); + + /* Check for space availability in the TTY Flip buffer */ + if (flip_cnt <= 0) { + goto drop_data; + } + umxc->port.icount.rx += flip_cnt; + + tty_insert_flip_string(tty, rx_buf_elem->rx_buf, flip_cnt); + + if (flag != TTY_NORMAL) { + tty_insert_flip_char(tty, 0, flag); + } + + tty_flip_buffer_push(tty); + umxc->port.info->port.tty->real_raw = 1; + + drop_data: + readchnl_request.src_addr = umxc->port.mapbase; + readchnl_request.dst_addr = rx_buf_elem->rx_handle; + readchnl_request.num_of_bytes = RXDMA_BUFF_SIZE; + mxc_dma_config(dma_list[umxc->port.line].rd_channel, &readchnl_request, + 1, MXC_DMA_MODE_READ); + mxc_dma_enable(dma_list[umxc->port.line].rd_channel); +} + +/*! + * Allocates DMA read and write channels, creates DMA read and write buffers and + * sets the channel specific parameters. + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_initdma(dma_info * d_info, uart_mxc_port * umxc) +{ + int ret = 0, rxbufs, i, j; + mxc_dma_requestbuf_t *readchnl_reqelem; + mxc_uart_rxdmamap *rx_buf_elem; + + /* Request for the read and write channels */ + d_info->rd_channel = mxc_dma_request(umxc->dma_rx_id, "MXC UART Read"); + if (d_info->rd_channel < 0) { + printk(KERN_ERR "MXC UART: Cannot allocate DMA read channel\n"); + return -1; + } else { + d_info->wr_channel = + mxc_dma_request(umxc->dma_tx_id, "MXC UART Write"); + if (d_info->wr_channel < 0) { + mxc_dma_free(d_info->rd_channel); + printk(KERN_ERR + "MXC UART: Cannot allocate DMA write channel\n"); + return -1; + } + } + + /* Allocate the DMA Transmit Buffer */ + if ((umxc->tx_buf = kmalloc(TXDMA_BUFF_SIZE, GFP_KERNEL)) == NULL) { + ret = -1; + goto err_dma_tx_buff; + } + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Allocate the DMA Virtual Receive Buffer */ + if ((umxc->rx_dmamap = kmalloc(rxbufs * sizeof(mxc_uart_rxdmamap), + GFP_KERNEL)) == NULL) { + ret = -1; + goto err_dma_rx_buff; + } + + /* Allocate the DMA Receive Request structures */ + if ((readchnl_reqelem = + kmalloc(rxbufs * sizeof(mxc_dma_requestbuf_t), + GFP_KERNEL)) == NULL) { + ret = -1; + goto err_request; + } + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + rx_buf_elem->rx_buf = + dma_alloc_coherent(NULL, RXDMA_BUFF_SIZE, + &rx_buf_elem->rx_handle, GFP_DMA); + if (rx_buf_elem->rx_buf == NULL) { + for (j = 0; j < i; j++) { + rx_buf_elem = + (mxc_uart_rxdmamap *) (umxc->rx_dmamap + j); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, + rx_buf_elem->rx_handle); + } + ret = -1; + goto cleanup; + } + } + + umxc->dma_rxbuf_id = 0; + /* Setup the DMA read request structures */ + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + (readchnl_reqelem + i)->src_addr = umxc->port.mapbase; + (readchnl_reqelem + i)->dst_addr = rx_buf_elem->rx_handle; + (readchnl_reqelem + i)->num_of_bytes = RXDMA_BUFF_SIZE; + } + mxc_dma_config(d_info->rd_channel, readchnl_reqelem, rxbufs, + MXC_DMA_MODE_READ); + mxc_dma_callback_set(d_info->rd_channel, mxcuart_dmaread_callback, + umxc); + mxc_dma_callback_set(d_info->wr_channel, mxcuart_dma_writecallback, + umxc); + + /* Start the read channel */ + mxc_dma_enable(d_info->rd_channel); + kfree(readchnl_reqelem); + tasklet_init(&d_info->dma_tx_tasklet, dma_tx_do_tasklet, + (unsigned long)umxc); + d_info->dma_txchnl_inuse = 0; + return ret; + cleanup: + kfree(readchnl_reqelem); + err_request: + kfree(umxc->rx_dmamap); + err_dma_rx_buff: + kfree(umxc->tx_buf); + err_dma_tx_buff: + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); + + return ret; +} + +/*! + * Stops DMA and frees the DMA resources + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_freedma(dma_info * d_info, uart_mxc_port * umxc) +{ + int i, rxbufs; + mxc_uart_rxdmamap *rx_buf_elem; + + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, rx_buf_elem->rx_handle); + } + kfree(umxc->rx_dmamap); + kfree(umxc->tx_buf); + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); +} + +/*! + * This function is called to free the interrupts. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_free_interrupts(uart_mxc_port * umxc) +{ + free_irq(umxc->port.irq, umxc); + if (umxc->ints_muxed == 0) { + free_irq(umxc->irqs[0], umxc); + free_irq(umxc->irqs[1], umxc); + } +} + +/*! + * Calculate and set the UART port clock value + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param per_clk peripheral clock coming into the MXC UART module + * @param req_baud current baudrate requested + * @param div returns the reference frequency divider value + */ +static void mxcuart_set_ref_freq(uart_mxc_port * umxc, unsigned long per_clk, + unsigned int req_baud, int *div) +{ + unsigned int d = 1; + + /* + * Choose the smallest possible prescaler to maximize + * the chance of using integer scaling. Ensure that + * the calculation won't overflow. Limit the denom + * to 15 bits since a 16-bit denom doesn't work. + */ + if (req_baud < (1 << (31 - (4 + 15)))) + d = per_clk / (req_baud << (4 + 15)) + 1; + + umxc->port.uartclk = per_clk / d; + + /* + * Set the ONEMS register that is used by IR special case bit and + * the Escape character detect logic + */ + writel(umxc->port.uartclk / 1000, umxc->port.membase + MXC_UARTONEMS); + *div = d; +} + +/*! + * This function is called by the core driver to initialize the low-level + * driver. The function grabs the interrupt resources and registers its + * interrupt service routines. It then initializes the IOMUX registers to + * configure the pins for UART signals and finally initializes the various + * UART registers and enables the port for reception. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_startup(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + int retval; + volatile unsigned int cr, cr1 = 0, cr2 = 0, ufcr = 0; + + /* + * Some UARTs need separate registrations for the interrupts as + * they do not take the muxed interrupt output to the ARM core + */ + if (umxc->ints_muxed == 1) { + retval = request_irq(umxc->port.irq, mxcuart_int, 0, + "mxcintuart", umxc); + if (retval != 0) { + return retval; + } + } else { + retval = request_irq(umxc->port.irq, mxcuart_tx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + return retval; + } else { + retval = request_irq(umxc->irqs[0], mxcuart_rx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + return retval; + } else { + retval = + request_irq(umxc->irqs[1], mxcuart_mint_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + free_irq(umxc->irqs[0], umxc); + return retval; + } + } + } + } + + /* Initialize the DMA if we need SDMA data transfer */ + if (umxc->dma_enabled == 1) { + retval = mxcuart_initdma(dma_list + umxc->port.line, umxc); + if (retval != 0) { + printk + (KERN_ERR + "MXC UART: Failed to initialize DMA for UART %d\n", + umxc->port.line); + mxcuart_free_interrupts(umxc); + return retval; + } + /* Configure the GPR register to receive SDMA events */ + config_uartdma_event(umxc->port.line); + } + + /* + * Clear Status Registers 1 and 2 + */ + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + /* Configure the IOMUX for the UART */ + gpio_uart_active(umxc->port.line, umxc->ir_mode); + + /* + * Set the transceiver invert bits if required + */ + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + writel(umxc->ir_rx_inv | MXC_UARTUCR4_IRSC, umxc->port.membase + + MXC_UARTUCR4); + writel(umxc->rxd_mux | umxc->ir_tx_inv, + umxc->port.membase + MXC_UARTUCR3); + } else { + writel(umxc->rxd_mux, umxc->port.membase + MXC_UARTUCR3); + } + + /* + * Initialize UCR1,2 and UFCR registers + */ + if (umxc->dma_enabled == 1) { + cr2 = (MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } else { + cr2 = + (MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } + + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + if (umxc->mode == MODE_DTE) { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_DCEDTE | MXC_UARTUFCR_RFDIV | umxc-> + rx_threshold); + } else { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_RFDIV | umxc->rx_threshold); + } + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Finally enable the UART and the Receive interrupts + */ + if (umxc->ir_mode == IRDA) { + cr1 |= MXC_UARTUCR1_IREN; + } + if (umxc->dma_enabled == 1) { + cr1 |= (MXC_UARTUCR1_RXDMAEN | MXC_UARTUCR1_ATDMAEN | + MXC_UARTUCR1_UARTEN); + } else { + cr1 |= (MXC_UARTUCR1_RRDYEN | MXC_UARTUCR1_UARTEN); + } + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + + return 0; +} + +/*! + * This function is called by the core driver for the low-level driver to free + * its resources. The function frees all its interrupts and disables the UART. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_shutdown(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + /* Disable the IOMUX for the UART */ + gpio_uart_inactive(umxc->port.line, umxc->ir_mode); + mxcuart_free_interrupts(umxc); + /* Disable all interrupts, port and break condition */ + writel(0, umxc->port.membase + MXC_UARTUCR1); + writel(0, umxc->port.membase + MXC_UARTUCR3); + if (umxc->dma_enabled == 1) { + mxcuart_freedma(dma_list + umxc->port.line, umxc); + } +} + +/*! + * This function is called while changing the UART parameters. It is called to + * check if the Infrared special case bit (IRSC) in control register 4 should + * be set. + * + * @param baudrate the desired baudrate + * + * @return The functions returns 0 if the IRSC bit does not have to be set, + * else it returns a 1. + */ +/* +static int mxcuart_setir_special(u_int baudrate) +{ + u_int thresh_val; + + thresh_val = 1000000 / (8 * MIN_PULSE_DUR); + if (baudrate > thresh_val) { + return 0; + } + + return 1; +} +*/ + +/*! + * This function is called by the core driver to change the UART parameters, + * including baudrate, word length, parity, stop bits. The function also updates + * the port structures mask registers to indicate the types of events the user is + * interested in receiving. + * + * @param port the port structure for the UART passed in by the core driver + * @param termios the desired termios settings + * @param old old termios + */ +static void mxcuart_set_termios(struct uart_port *port, + struct ktermios *termios, struct ktermios *old) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr4 = 0, cr2 = 0, ufcr; + u_int num, denom, baud; + u_int cr2_mask; /* Used to add the changes to CR2 */ + unsigned long flags, per_clk; + int div; + + cr2_mask = ~(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTSC | MXC_UARTUCR2_PREN | + MXC_UARTUCR2_PROE | MXC_UARTUCR2_STPB | MXC_UARTUCR2_WS); + + per_clk = clk_get_rate(umxc->clk); + + /* + * Ask the core to get the baudrate, if requested baudrate is not + * between max and min, then either use the baudrate in old termios + * setting. If it's still invalid, we try 9600 baud. + */ + baud = uart_get_baud_rate(&umxc->port, termios, old, 0, per_clk / 16); + /* Set the Reference frequency divider */ + mxcuart_set_ref_freq(umxc, per_clk, baud, &div); + + /* Byte size, default is 8-bit mode */ + switch (termios->c_cflag & CSIZE) { + case CS7: + cr2 = 0; + break; + default: + cr2 = MXC_UARTUCR2_WS; + break; + } + /* Check to see if we need 2 Stop bits */ + if (termios->c_cflag & CSTOPB) { + cr2 |= MXC_UARTUCR2_STPB; + } + + /* Check to see if we need Parity checking */ + if (termios->c_cflag & PARENB) { + cr2 |= MXC_UARTUCR2_PREN; + if (termios->c_cflag & PARODD) { + cr2 |= MXC_UARTUCR2_PROE; + } + } + spin_lock_irqsave(&umxc->port.lock, flags); + + ufcr = readl(umxc->port.membase + MXC_UARTUFCR); + ufcr = (ufcr & (~MXC_UARTUFCR_RFDIV_MASK)) | + ((6 - div) << MXC_UARTUFCR_RFDIV_OFFSET); + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Update the per-port timeout + */ + uart_update_timeout(&umxc->port, termios->c_cflag, baud); + + umxc->port.read_status_mask = MXC_UARTURXD_OVRRUN; + /* + * Enable appropriate events to be passed to the TTY layer + */ + if (termios->c_iflag & INPCK) { + umxc->port.read_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & (BRKINT | PARMRK)) { + umxc->port.read_status_mask |= MXC_UARTURXD_BRK; + } + + /* + * Characters to ignore + */ + umxc->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & IGNBRK) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_BRK; + /* + * If we are ignoring parity and break indicators, + * ignore overruns too (for real raw support) + */ + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_OVRRUN; + } + } + + /* + * Ignore all characters if CREAD is not set, still receive characters + * from the port, but throw them away. + */ + if ((termios->c_cflag & CREAD) == 0) { + umxc->port.ignore_status_mask |= UART_CREAD_BIT; + } + + cr4 = readl(umxc->port.membase + MXC_UARTUCR4); + if (UART_ENABLE_MS(port, termios->c_cflag)) { + mxcuart_enable_ms(port); + if (umxc->hardware_flow == 1) { + cr4 = (cr4 & (~MXC_UARTUCR4_CTSTL_MASK)) | + (umxc->cts_threshold << MXC_UARTUCR4_CTSTL_OFFSET); + cr2 |= MXC_UARTUCR2_CTSC; + umxc->port.info->port.tty->hw_stopped = 0; + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + + /* Add Parity, character length and stop bits information */ + cr2 |= (readl(umxc->port.membase + MXC_UARTUCR2) & cr2_mask); + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* + if (umxc->ir_mode == IRDA) { + ret = mxcuart_setir_special(baud); + if (ret == 0) { + cr4 &= ~MXC_UARTUCR4_IRSC; + } else { + cr4 |= MXC_UARTUCR4_IRSC; + } + } */ + writel(cr4, umxc->port.membase + MXC_UARTUCR4); + + /* + * Set baud rate + */ + + /* Use integer scaling, if possible. Limit the denom to 15 bits. */ + num = 0; + denom = (umxc->port.uartclk + 8 * baud) / (16 * baud) - 1; + + /* Use fractional scaling if needed to limit the max error to 0.5% */ + if (denom < 100) { + u64 n64 = (u64) 16 * 0x8000 * baud + (umxc->port.uartclk / 2); + do_div(n64, umxc->port.uartclk); + num = (u_int) n64 - 1; + denom = 0x7fff; + } + writel(num, umxc->port.membase + MXC_UARTUBIR); + writel(denom, umxc->port.membase + MXC_UARTUBMR); + + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * This function is called by the core driver to know the UART type. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns a pointer to a string describing the UART port. + */ +static const char *mxcuart_type(struct uart_port *port) +{ + return port->type == PORT_IMX ? "Freescale i.MX" : NULL; +} + +/*! + * This function is called by the core driver to release the memory resources + * currently in use by the UART port. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, SZ_4K); +} + +/*! + * This function is called by the core driver to request memory resources for + * the UART port. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns \b -EBUSY on failure, else it returns 0. + */ +static int mxcuart_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, SZ_4K, "serial_mxc") + != NULL ? 0 : -EBUSY; +} + +/*! + * This function is called by the core driver to perform any autoconfiguration + * steps required for the UART port. This function sets the port->type field. + * + * @param port the port structure for the UART passed in by the core driver + * @param flags bit mask of the required configuration + */ +static void mxcuart_config_port(struct uart_port *port, int flags) +{ + if ((flags & UART_CONFIG_TYPE) && (mxcuart_request_port(port) == 0)) { + port->type = PORT_IMX; + } +} + +/*! + * This function is called by the core driver to verify that the new serial + * port information contained within \a ser is suitable for this UART port type. + * The function checks to see if the UART port type specified by the user + * application while setting the UART port information matches what is stored + * in the define \b PORT_MXC found in the header file include/linux/serial_core.h + * + * @param port the port structure for the UART passed in by the core driver + * @param ser the new serial port information + * + * @return The function returns 0 on success or \b -EINVAL if the port type + * specified is not equal to \b PORT_MXC. + */ +static int mxcuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) { + ret = -EINVAL; + } + return ret; +} + +/*! + * This function is used to send a high priority XON/XOFF character + * + * @param port the port structure for the UART passed in by the core driver + * @param ch the character to send + */ +static void mxcuart_send_xchar(struct uart_port *port, char ch) +{ + unsigned long flags; + + port->x_char = ch; + if (port->info->port.tty->hw_stopped) { + return; + } + + if (ch) { + spin_lock_irqsave(&port->lock, flags); + port->ops->start_tx(port); + spin_unlock_irqrestore(&port->lock, flags); + } +} + +/*! + * This function is used enable/disable the MXC UART clocks + * + * @param port the port structure for the UART passed in by the core driver + * @param state New PM state + * @param oldstate Current PM state + */ +static void +mxcuart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + if (state) + clk_disable(umxc->clk); + else + clk_enable(umxc->clk); +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core serial driver to access the UART hardware. The + * structure is passed to serial_core.c file during registration. + */ +static struct uart_ops mxc_ops = { + .tx_empty = mxcuart_tx_empty, + .set_mctrl = mxcuart_set_mctrl, + .get_mctrl = mxcuart_get_mctrl, + .stop_tx = mxcuart_stop_tx, + .start_tx = mxcuart_start_tx, + .stop_rx = mxcuart_stop_rx, + .enable_ms = mxcuart_enable_ms, + .break_ctl = mxcuart_break_ctl, + .startup = mxcuart_startup, + .shutdown = mxcuart_shutdown, + .set_termios = mxcuart_set_termios, + .type = mxcuart_type, + .pm = mxcuart_pm, + .release_port = mxcuart_release_port, + .request_port = mxcuart_request_port, + .config_port = mxcuart_config_port, + .verify_port = mxcuart_verify_port, + .send_xchar = mxcuart_send_xchar, +}; + +#ifdef CONFIG_SERIAL_MXC_CONSOLE + +/* + * Write out a character once the UART is ready + */ +static inline void mxcuart_console_write_char(struct uart_port *port, char ch) +{ + volatile unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +static void mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_ports[co->index]->port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + int i; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + /* + * Do each character + */ + for (i = 0; i < count; i++) { + mxcuart_console_write_char(port, s[i]); + if (s[i] == '\n') { + mxcuart_console_write_char(port, '\r'); + } + } + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +/*! + * Initializes the UART port to be used to print console message with the + * options specified. If no options are specified, then the function + * initializes the UART with the default options of baudrate=115200, 8 bit + * word size, no parity, no flow control. + * + * @param co The console structure + * @param options Any console options passed in from the command line + * + * @return The function returns 0 on success or error. + */ +static int __init mxcuart_console_setup(struct console *co, char *options) +{ + uart_mxc_port *umxc; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + volatile unsigned int cr = 0; + + /* + * Check whether an invalid uart number had been specified, and if + * so, search for the first available port that does have console + * support + */ + if (co->index >= MXC_UART_NR) { + co->index = 0; + } + umxc = mxc_ports[co->index]; + + if (umxc == NULL) { + return -ENODEV; + } + + clk_enable(umxc->clk); + + /* initialize port.lock else oops */ + spin_lock_init(&umxc->port.lock); + + /* + * Initialize the UART registers + */ + writel(MXC_UARTUCR1_UARTEN, umxc->port.membase + MXC_UARTUCR1); + /* Enable the transmitter and do a software reset */ + writel(MXC_UARTUCR2_TXEN, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + writel(0x0, umxc->port.membase + MXC_UARTUCR3); + writel(0x0, umxc->port.membase + MXC_UARTUCR4); + /* Set TXTL to 2, RXTL to 1 and RFDIV to 2 */ + cr = 0x0800 | MXC_UARTUFCR_RFDIV | 0x1; + if (umxc->mode == MODE_DTE) { + cr |= MXC_UARTUFCR_DCEDTE; + } + writel(cr, umxc->port.membase + MXC_UARTUFCR); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + if (options != NULL) { + uart_parse_options(options, &baud, &parity, &bits, &flow); + } + gpio_uart_active(umxc->port.line, umxc->ir_mode); + return uart_set_options(&umxc->port, co, baud, parity, bits, flow); +} + +static struct uart_driver mxc_reg; + +/*! + * This structure contains the pointers to the UART console functions. It is + * passed as an argument when registering the console. + */ +static struct console mxc_console = { + .name = "ttymxc", + .write = mxcuart_console_write, + .device = uart_console_device, + .setup = mxcuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &mxc_reg, +}; + +/*! + * This function registers the console callback functions with the kernel. + */ +static int __init mxcuart_console_init(void) +{ + register_console(&mxc_console); + return 0; +} + +console_initcall(mxcuart_console_init); + +static int __init find_port(struct uart_port *p) +{ + int line; + struct uart_port *port; + for (line = 0; line < MXC_UART_NR; line++) { + if (!mxc_ports[line]) + continue; + port = &mxc_ports[line]->port; + if (uart_match_port(p, port)) + return line; + } + return -ENODEV; +} + +int __init mxc_uart_start_console(struct uart_port *port, char *options) +{ + int line; + line = find_port(port); + if (line < 0) + return -ENODEV; + + add_preferred_console("ttymxc", line, options); + printk("Switching Console to ttymxc%d at %s 0x%lx (options '%s')\n", + line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port", + port->iotype == + UPIO_MEM ? (unsigned long)port->mapbase : (unsigned long)port-> + iobase, options); + + if (!(mxc_console.flags & CON_ENABLED)) { + mxc_console.flags &= ~CON_PRINTBUFFER; + register_console(&mxc_console); + } + return 0; +} + +#define MXC_CONSOLE &mxc_console +#else +#define MXC_CONSOLE NULL +#endif /* CONFIG_SERIAL_MXC_CONSOLE */ + +/*! + * This structure contains the information such as the name of the UART driver + * that appears in the /dev folder, major and minor numbers etc. This structure + * is passed to the serial_core.c file. + */ +static struct uart_driver mxc_reg = { + .owner = THIS_MODULE, + .driver_name = "ttymxc", + .dev_name = "ttymxc", + .major = SERIAL_MXC_MAJOR, + .minor = SERIAL_MXC_MINOR, + .nr = MXC_UART_NR, + .cons = MXC_CONSOLE, +}; + +/*! + * This function is called to put the UART in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_suspend(struct platform_device *pdev, pm_message_t state) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc->port.info && umxc->port.info->flags & UIF_INITIALIZED) + uart_suspend_port(&mxc_reg, &umxc->port); + + if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED) + umxc->port.info->port.tty->hw_stopped = 1; + + return 0; +} + +/*! + * This function is called to bring the UART back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to resume + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_resume(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED) { + umxc->port.info->port.tty->hw_stopped = 0; + uart_resume_port(&mxc_reg, &umxc->port); + } + + return 0; +} + +/*! + * This function is called during the driver binding process. Based on the UART + * that is being probed this function adds the appropriate UART port structure + * in the core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 if successful; -1 otherwise. + */ +static int mxcuart_probe(struct platform_device *pdev) +{ + int id = pdev->id; + + mxc_ports[id] = pdev->dev.platform_data; + mxc_ports[id]->port.ops = &mxc_ops; + + /* Do not use UARTs that are disabled during integration */ + if (mxc_ports[id]->enabled == 1) { + mxc_ports[id]->port.dev = &pdev->dev; + spin_lock_init(&mxc_ports[id]->port.lock); + /* Enable the low latency flag for DMA UART ports */ + if (mxc_ports[id]->dma_enabled == 1) { + mxc_ports[id]->port.flags |= UPF_LOW_LATENCY; + } + + mxc_ports[id]->clk = clk_get(&pdev->dev, "uart_clk"); + if (mxc_ports[id]->clk == NULL) + return -1; + + uart_add_one_port(&mxc_reg, &mxc_ports[id]->port); + platform_set_drvdata(pdev, mxc_ports[id]); + } + return 0; +} + +/*! + * Dissociates the driver from the UART device. Removes the appropriate UART + * port structure from the core driver. + * + * @param pdev the device structure used to give information on which UART + * to remove + * + * @return The function always returns 0. + */ +static int mxcuart_remove(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + if (umxc) { + uart_remove_one_port(&mxc_reg, &umxc->port); + } + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcuart_driver = { + .driver = { + .name = "mxcintuart", + }, + .probe = mxcuart_probe, + .remove = mxcuart_remove, + .suspend = mxcuart_suspend, + .resume = mxcuart_resume, +}; + +/*! + * This function is used to initialize the UART driver module. The function + * registers the power management callback functions with the kernel and also + * registers the UART callback functions with the core serial driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxcuart_init(void) +{ + int ret = 0; + + printk(KERN_INFO "Serial: MXC Internal UART driver\n"); + ret = uart_register_driver(&mxc_reg); + if (ret == 0) { + /* Register the device driver structure. */ + ret = platform_driver_register(&mxcuart_driver); + if (ret != 0) { + uart_unregister_driver(&mxc_reg); + } + } + return ret; +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxcuart_exit(void) +{ + platform_driver_unregister(&mxcuart_driver); + uart_unregister_driver(&mxc_reg); +} + +module_init(mxcuart_init); +module_exit(mxcuart_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC serial port driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/mxc_uart_early.c b/drivers/serial/mxc_uart_early.c new file mode 100644 index 000000000000..0b5ceaef3ec0 --- /dev/null +++ b/drivers/serial/mxc_uart_early.c @@ -0,0 +1,253 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart_early.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/8250_early.c, Copyright 2004 Hewlett-Packard Development Company, + * L.P. by Bjorn Helgaasby. + * + * Early serial console for MXC UARTS. + * + * This is for use before the serial driver has initialized, in + * particular, before the UARTs have been discovered and named. + * Instead of specifying the console device as, e.g., "ttymxc0", + * we locate the device directly by its MMIO or I/O port address. + * + * The user can specify the device directly, e.g., + * console=mxcuart,0x43f90000,115200n8 + * or platform code can call early_uart_console_init() to set + * the early UART device. + * + * After the normal serial driver starts, we try to locate the + * matching ttymxc device and start a console there. + */ + +/* + * Include Files + */ + +#include <linux/tty.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/console.h> +#include <linux/serial_core.h> +#include <linux/serial_reg.h> +#include <linux/clk.h> +#include <mach/mxc_uart.h> + +struct mxc_early_uart_device { + struct uart_port port; + char options[16]; /* e.g., 115200n8 */ + unsigned int baud; +}; + +int __init mxc_uart_start_console(struct uart_port *, char *); +static struct mxc_early_uart_device mxc_early_device __initdata; +static int mxc_early_uart_registered __initdata; +static struct clk *clk; + +/* + * Write out a character once the UART is ready + */ +static void __init mxcuart_console_write_char(struct uart_port *port, int ch) +{ + unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +void __init early_mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_early_device.port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + + /* Transmit string */ + uart_console_write(port, s, count, mxcuart_console_write_char); + + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +static unsigned int __init probe_baud(struct uart_port *port) +{ + /* FIXME Return Default Baud Rate */ + return 115200; +} + +static int __init parse_options(struct mxc_early_uart_device *device, + char *options) +{ + struct uart_port *port = &device->port; + int mapsize = 64; + int length; + + if (!options) + return -ENODEV; + + port->uartclk = 5600000; + port->iotype = UPIO_MEM; + port->mapbase = simple_strtoul(options, &options, 0); + port->membase = ioremap(port->mapbase, mapsize); + + if ((options = strchr(options, ','))) { + options++; + device->baud = simple_strtoul(options, NULL, 0); + length = min(strcspn(options, " "), sizeof(device->options)); + strncpy(device->options, options, length); + } else { + device->baud = probe_baud(port); + snprintf(device->options, sizeof(device->options), "%u", + device->baud); + } + printk(KERN_INFO + "MXC_Early serial console at MMIO 0x%x (options '%s')\n", + port->mapbase, device->options); + return 0; +} + +static int __init mxc_early_uart_setup(struct console *console, char *options) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + int err; + if (device->port.membase || device->port.iobase) + return 0; + if ((err = parse_options(device, options)) < 0) + return err; + return 0; +} + +static struct console mxc_early_uart_console __initdata = { + .name = "mxcuart", + .write = early_mxcuart_console_write, + .setup = mxc_early_uart_setup, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +static int __init mxc_early_uart_console_init(void) +{ + + if (!mxc_early_uart_registered) { + register_console(&mxc_early_uart_console); + mxc_early_uart_registered = 1; + } + + return 0; +} + +int __init mxc_early_serial_console_init(char *cmdline) +{ + char *options; + int err; + int uart_paddr; + + options = strstr(cmdline, "console=mxcuart"); + if (!options) + return -ENODEV; + + /* Extracting MXC UART Uart Port Address from cmdline */ + options = strchr(cmdline, ',') + 1; + uart_paddr = simple_strtoul(options, NULL, 16); + +#ifdef UART1_BASE_ADDR + if (uart_paddr == UART1_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.0"); +#endif +#ifdef UART2_BASE_ADDR + if (uart_paddr == UART2_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.1"); +#endif +#ifdef UART3_BASE_ADDR + if (uart_paddr == UART3_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.2"); +#endif + if (clk == NULL) + return -1; + + /* Enable Early MXC UART Clock */ + clk_enable(clk); + + options = strchr(cmdline, ',') + 1; + if ((err = mxc_early_uart_setup(NULL, options)) < 0) + return err; + return mxc_early_uart_console_init(); +} + +int __init mxc_early_uart_console_switch(void) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + struct uart_port *port = &device->port; + int mmio, line; + + if (!(mxc_early_uart_console.flags & CON_ENABLED)) + return 0; + /* Try to start the normal driver on a matching line. */ + mmio = (port->iotype == UPIO_MEM); + line = mxc_uart_start_console(port, device->options); + + if (line < 0) + printk("No ttymxc device at %s 0x%lx for console\n", + mmio ? "MMIO" : "I/O port", + mmio ? port->mapbase : (unsigned long)port->iobase); + + unregister_console(&mxc_early_uart_console); + if (mmio) + iounmap(port->membase); + + clk_disable(clk); + clk_put(clk); + + return 0; +} + +late_initcall(mxc_early_uart_console_switch); diff --git a/drivers/serial/mxc_uart_reg.h b/drivers/serial/mxc_uart_reg.h new file mode 100644 index 000000000000..c0d1e812fe6a --- /dev/null +++ b/drivers/serial/mxc_uart_reg.h @@ -0,0 +1,128 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_UART_REG_H__ +#define __MXC_UART_REG_H__ + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __MXC_UART_REG_H__ */ diff --git a/drivers/serial/stmp-app.c b/drivers/serial/stmp-app.c new file mode 100644 index 000000000000..b02d85721d3a --- /dev/null +++ b/drivers/serial/stmp-app.c @@ -0,0 +1,1081 @@ +/* + * Freescale STMP37XX/STMP378X Application UART driver + * + * Author: dmitry pervushin <dimka@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/wait.h> +#include <linux/tty.h> +#include <linux/tty_driver.h> +#include <linux/tty_flip.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/device.h> +#include <linux/clk.h> +#include <linux/cpufreq.h> +#include <linux/dma-mapping.h> +#include <linux/delay.h> +#include <linux/uaccess.h> + +#include <asm/cacheflush.h> +#include <mach/hardware.h> +#include <mach/regs-apbx.h> +#include <mach/regs-uartapp.h> +#include <mach/regs-pinctrl.h> +#include <mach/stmp3xxx.h> +#include <mach/platform.h> + +#include <asm/mach-types.h> + +#include "stmp-app.h" + +static int pio_mode /* = 0 */; /* PIO mode = 1, DMA mode = 0 */ + +static struct platform_driver stmp_appuart_driver = { + .probe = stmp_appuart_probe, + .remove = __devexit_p(stmp_appuart_remove), + .suspend = stmp_appuart_suspend, + .resume = stmp_appuart_resume, + .driver = { + .name = "stmp37xx-appuart", + .owner = THIS_MODULE, + }, +}; + +static struct uart_driver stmp_appuart_uart = { + .owner = THIS_MODULE, + .driver_name = "appuart", + .dev_name = "ttySP", + .major = 242, + .minor = 0, + .nr = 1, +}; + +static inline struct stmp_appuart_port *to_appuart(struct uart_port *u) +{ + return container_of(u, struct stmp_appuart_port, port); +} + +static struct uart_ops stmp_appuart_ops = { + .tx_empty = stmp_appuart_tx_empty, + .start_tx = stmp_appuart_start_tx, + .stop_tx = stmp_appuart_stop_tx, + .stop_rx = stmp_appuart_stop_rx, + .enable_ms = stmp_appuart_enable_ms, + .break_ctl = stmp_appuart_break_ctl, + .set_mctrl = stmp_appuart_set_mctrl, + .get_mctrl = stmp_appuart_get_mctrl, + .startup = stmp_appuart_startup, + .shutdown = stmp_appuart_shutdown, + .set_termios = stmp_appuart_settermios, + .type = stmp_appuart_type, + .release_port = stmp_appuart_release_port, + .request_port = stmp_appuart_request_port, + .config_port = stmp_appuart_config_port, + .verify_port = stmp_appuart_verify_port, +}; + +static inline int chr(int c) +{ + if (c < 0x20 || c > 0x7F) + return '#'; + return c; +} + +/* Allocate and initialize rx and tx DMA chains */ +static inline int stmp_appuart_dma_init(struct stmp_appuart_port *s) +{ + int err = 0; + struct stmp3xxx_dma_descriptor *t = &s->tx_desc; +#ifndef RX_CHAIN + struct stmp3xxx_dma_descriptor *r = &s->rx_desc; +#else + int i; +#endif + + err = stmp3xxx_dma_request(s->dma_rx, s->dev, dev_name(s->dev)); + if (err) + goto out; + err = stmp3xxx_dma_request(s->dma_tx, s->dev, dev_name(s->dev)); + if (err) + goto out1; + +#ifndef RX_CHAIN + err = stmp3xxx_dma_allocate_command(s->dma_rx, r); + if (err) + goto out2; +#endif + err = stmp3xxx_dma_allocate_command(s->dma_tx, t); + if (err) + goto out3; + t->virtual_buf_ptr = dma_alloc_coherent(s->dev, + TX_BUFFER_SIZE, + &t->command->buf_ptr, GFP_DMA); + if (!t->virtual_buf_ptr) + goto out4; +#ifdef DEBUG + memset(t->virtual_buf_ptr, 0x4B, TX_BUFFER_SIZE); +#endif + +#ifndef RX_CHAIN + r->virtual_buf_ptr = dma_alloc_coherent(s->dev, + RX_BUFFER_SIZE, + &r->command->buf_ptr, GFP_DMA); + if (!r->virtual_buf_ptr) + goto out5; +#ifdef DEBUG + memset(r->virtual_buf_ptr, 0x4C, RX_BUFFER_SIZE); +#endif +#else + stmp3xxx_dma_make_chain(s->dma_rx, &s->rx_chain, s->rxd, RX_CHAIN); + for (i = 0; i < RX_CHAIN; i++) { + struct stmp3xxx_dma_descriptor *r = s->rxd + i; + + r->command->cmd = + BF(RX_BUFFER_SIZE, APBX_CHn_CMD_XFER_COUNT) | + BF(1, APBX_CHn_CMD_CMDWORDS) | + BM_APBX_CHn_CMD_WAIT4ENDCMD | + BM_APBX_CHn_CMD_SEMAPHORE | + BM_APBX_CHn_CMD_IRQONCMPLT | + BM_APBX_CHn_CMD_CHAIN | + BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__DMA_WRITE); + r->virtual_buf_ptr = dma_alloc_coherent(s->dev, + RX_BUFFER_SIZE, + &r->command->buf_ptr, + GFP_DMA); + r->command->pio_words[0] = /* BM_UARTAPP_CTRL0_RUN | */ + BF(RX_BUFFER_SIZE, UARTAPP_CTRL0_XFER_COUNT) | + BM_UARTAPP_CTRL0_RXTO_ENABLE | + BF(3, UARTAPP_CTRL0_RXTIMEOUT); + } +#endif + return 0; + + /* + * would be necessary on other error paths + + dma_free_coherent( s->dev, RX_BUFFER_SIZE, r->virtual_buf_ptr, + r->command->buf_ptr); + */ +out5: + dma_free_coherent(s->dev, TX_BUFFER_SIZE, t->virtual_buf_ptr, + t->command->buf_ptr); +out4: + stmp3xxx_dma_free_command(s->dma_tx, t); +out3: +#ifndef RX_CHAIN + stmp3xxx_dma_free_command(s->dma_rx, r); +#endif +out2: + stmp3xxx_dma_release(s->dma_tx); +out1: + stmp3xxx_dma_release(s->dma_rx); +out: + WARN_ON(err); + return err; +} + + +static void stmp_appuart_on(struct platform_device *dev) +{ + struct stmp_appuart_port *s = platform_get_drvdata(dev); + + if (!pio_mode) { + /* + Tell DMA to select UART. + Both DMA channels are shared between app UART and IrDA. + Target id of 0 means UART, 1 means IrDA + */ + stmp3xxx_dma_set_alt_target(s->dma_rx, 0); + stmp3xxx_dma_set_alt_target(s->dma_tx, 0); + /* + Reset DMA channels + */ + stmp3xxx_dma_reset_channel(s->dma_rx); + stmp3xxx_dma_reset_channel(s->dma_tx); + stmp3xxx_dma_enable_interrupt(s->dma_rx); + stmp3xxx_dma_enable_interrupt(s->dma_tx); + } +} + +#ifdef CONFIG_CPU_FREQ +static int stmp_appuart_updateclk(struct device *dev, void *clkdata) +{ + struct stmp_appuart_port *s = dev_get_drvdata(dev); + + if (s) { + s->port.uartclk = clk_get_rate(s->clk) * 1000; + /* FIXME: perform actual update */ + } + return 0; +} + +static int stmp_appuart_notifier(struct notifier_block *self, + unsigned long phase, void *p) +{ + int r = 0; + + if ((phase == CPUFREQ_POSTCHANGE) || (phase == CPUFREQ_RESUMECHANGE)) { + /* get new uartclock and setspeed */ + r = driver_for_each_device(&stmp_appuart_driver.driver, + NULL, p, stmp_appuart_updateclk); + } + return (r == 0) ? NOTIFY_OK : NOTIFY_DONE; +} + +static struct notifier_block stmp_appuart_nb = { + .notifier_call = &stmp_appuart_notifier, +}; +#endif /* CONFIG_CPU_FREQ */ + +static int __devinit stmp_appuart_probe(struct platform_device *device) +{ + struct stmp_appuart_port *s; + int err = 0; + struct resource *r; + int i; + u32 version; + int (*pinctl)(int req, int id); + + s = kzalloc(sizeof(struct stmp_appuart_port), GFP_KERNEL); + if (!s) { + err = -ENOMEM; + goto out; + } + + spin_lock_init(&s->lock); + + s->clk = clk_get(NULL, "uart"); + if (IS_ERR(s->clk)) { + err = PTR_ERR(s->clk); + goto out_free; + } + clk_enable(s->clk); + r = platform_get_resource(device, IORESOURCE_MEM, 0); + if (!r) { + err = -ENXIO; + goto out_free_clk; + } + s->port.mapbase = r->start; + s->port.irq = platform_get_irq(device, 0); + s->port.ops = &stmp_appuart_ops; + s->port.iotype = UPIO_MEM; + s->port.line = device->id < 0 ? 0 : device->id; + s->port.fifosize = 16; + s->port.timeout = HZ/10; + s->port.uartclk = clk_get_rate(s->clk) * 1000; + s->port.type = PORT_IMX; + s->port.dev = s->dev = get_device(&device->dev); + s->ctrl = 0; + s->keep_irq = 0; + + r = platform_get_resource(device, IORESOURCE_MEM, 0); + if (!r) { + err = -ENXIO; + goto out_free_clk; + } + + dev_dbg(s->dev, "%s\n", __func__); + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + s->irq[i] = platform_get_irq(device, i); + dev_dbg(s->dev, "Resources: irq[%d] = %d\n", i, s->irq[i]); + if (s->irq[i] < 0) { + err = s->irq[i]; + goto out_free_clk; + } + } + + r = platform_get_resource(device, IORESOURCE_DMA, 0); + if (!r) { + err = -ENXIO; + goto out_free; + } + s->dma_rx = r->start; + + r = platform_get_resource(device, IORESOURCE_DMA, 1); + if (!r) { + err = -ENXIO; + goto out_free; + } + s->dma_tx = r->start; + + r = platform_get_resource(device, IORESOURCE_MEM, 0); + if (!r) { + err = -ENXIO; + goto out_free; + } + s->mem = (void __iomem *)(r->start - STMP3XXX_REGS_PHBASE + + (u32)STMP3XXX_REGS_BASE); + s->memsize = r->end - r->start; + +#ifdef CONFIG_CPU_FREQ + cpufreq_register_notifier(&stmp_appuart_nb, + CPUFREQ_TRANSITION_NOTIFIER); +#endif + platform_set_drvdata(device, s); + + device_init_wakeup(&device->dev, 1); + + stmp_appuart_dma_init(s); + stmp_appuart_on(device); + + pinctl = device->dev.platform_data; + if (pinctl) { + err = pinctl(1, device->id); + if (err) + goto out_free_clk; + } + + err = uart_add_one_port(&stmp_appuart_uart, &s->port); + if (err) + goto out_free_pins; + + version = __raw_readl(REGS_UARTAPP1_BASE + HW_UARTAPP_VERSION); + printk(KERN_INFO "Found APPUART %d.%d.%d\n", + (version >> 24) & 0xFF, + (version >> 16) & 0xFF, version & 0xFFFF); + return 0; + +out_free_pins: + if (pinctl) + pinctl(0, device->id); +out_free_clk: + clk_put(s->clk); +out_free: + platform_set_drvdata(device, NULL); + kfree(s); +out: + return err; +} + +static int __devexit stmp_appuart_remove(struct platform_device *device) +{ + struct stmp_appuart_port *s; + void (*pinctl)(int req, int id); + + s = platform_get_drvdata(device); + if (s) { + pinctl = device->dev.platform_data; + put_device(s->dev); + clk_disable(s->clk); + clk_put(s->clk); + uart_remove_one_port(&stmp_appuart_uart, &s->port); + if (pinctl) + pinctl(0, device->id); + kfree(s); + platform_set_drvdata(device, NULL); + } + + return 0; +} + +static int stmp_appuart_suspend(struct platform_device *device, + pm_message_t state) +{ +#ifdef CONFIG_PM + struct stmp_appuart_port *s = platform_get_drvdata(device); + + if (!s) + return 0; + s->keep_irq = device_may_wakeup(&device->dev); + uart_suspend_port(&stmp_appuart_uart, &s->port); + if (!s->keep_irq) + clk_disable(s->clk); +#endif + return 0; +} + +static int stmp_appuart_resume(struct platform_device *device) +{ +#ifdef CONFIG_PM + struct stmp_appuart_port *s = platform_get_drvdata(device); + + if (!s) + return 0; + + if (!s->keep_irq) + clk_enable(s->clk); + stmp_appuart_on(device); + uart_resume_port(&stmp_appuart_uart, &s->port); + s->keep_irq = 0; +#endif + return 0; +} + +static int __init stmp_appuart_init() +{ + int r; + + r = uart_register_driver(&stmp_appuart_uart); + if (r) + goto out; + r = platform_driver_register(&stmp_appuart_driver); + if (r) + goto out_err; + return 0; +out_err: + uart_unregister_driver(&stmp_appuart_uart); +out: + return r; +} + +static void __exit stmp_appuart_exit() +{ + platform_driver_unregister(&stmp_appuart_driver); + uart_unregister_driver(&stmp_appuart_uart); +} + +module_init(stmp_appuart_init) +module_exit(stmp_appuart_exit) + +static void stmp_appuart_stop_rx(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); + stmp3xxx_clearl(BM_UARTAPP_CTRL2_RXE, s->mem); +} + +static void stmp_appuart_break_ctl(struct uart_port *u, int ctl) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s: break = %s\n", __func__, ctl ? "on" : "off"); + if (ctl) + stmp3xxx_setl(BM_UARTAPP_LINECTRL_BRK, + s->mem + HW_UARTAPP_LINECTRL); + else + stmp3xxx_clearl(BM_UARTAPP_LINECTRL_BRK, + s->mem + HW_UARTAPP_LINECTRL); +} + +static void stmp_appuart_enable_ms(struct uart_port *port) +{ + /* just empty */ +} + +static void stmp_appuart_set_mctrl(struct uart_port *u, unsigned mctrl) +{ + struct stmp_appuart_port *s = to_appuart(u); + + u32 ctrl = __raw_readl(s->mem + HW_UARTAPP_CTRL2); + + dev_dbg(s->dev, "%s (%x)\n", __func__, mctrl); + ctrl &= ~BM_UARTAPP_CTRL2_RTS; + if (mctrl & TIOCM_RTS) { + dev_dbg(s->dev, "...RTS\n"); + ctrl |= BM_UARTAPP_CTRL2_RTS; + } + s->ctrl = mctrl; + dev_dbg(s->dev, "...%x; ctrl = %x\n", s->ctrl, ctrl); + __raw_writel(ctrl, s->mem + HW_UARTAPP_CTRL2); +} + +static u32 stmp_appuart_get_mctrl(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + u32 stat = __raw_readl(s->mem + HW_UARTAPP_STAT); + int ctrl2 = __raw_readl(s->mem + HW_UARTAPP_CTRL2); + u32 mctrl = s->ctrl; + + dev_dbg(s->dev, "%s:\n", __func__); + mctrl &= ~TIOCM_CTS; + if (stat & BM_UARTAPP_STAT_CTS) { + dev_dbg(s->dev, "CTS"); + mctrl |= TIOCM_CTS; + } + if (ctrl2 & BM_UARTAPP_CTRL2_RTS) { + dev_dbg(s->dev, "RTS"); + mctrl |= TIOCM_RTS; + } + dev_dbg(s->dev, "...%x\n", mctrl); + return mctrl; +} + +static int stmp_appuart_request_port(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + int err = 0; + + if (!request_mem_region((u32)s->mem, s->memsize, dev_name(s->dev))) + err = -ENXIO; + return err; + +} + +static void stmp_appuart_release_port(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + release_mem_region((u32)s->mem, s->memsize); +} + +static int stmp_appuart_verify_port(struct uart_port *u, + struct serial_struct *ser) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); + return 0; +} + +static void stmp_appuart_config_port(struct uart_port *u, int flags) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); +} + +static const char *stmp_appuart_type(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); + return dev_name(s->dev); +} + +static void stmp_appuart_settermios(struct uart_port *u, + struct ktermios *nw, struct ktermios *old) +{ + static struct ktermios saved; + struct stmp_appuart_port *s = to_appuart(u); + unsigned int cflag; + u32 bm, ctrl, ctrl2, div; + int err = 0; + unsigned baud; + + dev_dbg(s->dev, "%s\n", __func__); + + if (nw) + memcpy(&saved, nw, sizeof *nw); + else + nw = old = &saved; + + cflag = nw->c_cflag; + + ctrl = BM_UARTAPP_LINECTRL_FEN; + ctrl2 = __raw_readl(s->mem + HW_UARTAPP_CTRL2); + + /* byte size */ + switch (cflag & CSIZE) { + case CS5: + bm = 0; + break; + case CS6: + bm = 1; + break; + case CS7: + bm = 2; + break; + case CS8: + bm = 3; + break; + default: + err = -EINVAL; + break; + } + if (err) + goto out; + + dev_dbg(s->dev, "Byte size %d bytes, mask %x\n", + bm + 5, BF(bm, UARTAPP_LINECTRL_WLEN)); + ctrl |= BF(bm, UARTAPP_LINECTRL_WLEN); + + /* parity */ + if (cflag & PARENB) { + dev_dbg(s->dev, "Parity check enabled\n"); + ctrl |= BM_UARTAPP_LINECTRL_PEN | BM_UARTAPP_LINECTRL_SPS; + if ((cflag & PARODD) == 0) { + dev_dbg(s->dev, "(Even) mask = %x\n", + BM_UARTAPP_LINECTRL_PEN | + BM_UARTAPP_LINECTRL_SPS | + BM_UARTAPP_LINECTRL_EPS); + ctrl |= BM_UARTAPP_LINECTRL_EPS; + } else + dev_dbg(s->dev, "(Odd) mask = %x\n", + BM_UARTAPP_LINECTRL_PEN | + BM_UARTAPP_LINECTRL_SPS); + } else + dev_dbg(s->dev, "Parity check disabled.\n"); + + /* figure out the stop bits requested */ + if (cflag & CSTOPB) { + dev_dbg(s->dev, "Stop bits, mask = %x\n", + BM_UARTAPP_LINECTRL_STP2); + ctrl |= BM_UARTAPP_LINECTRL_STP2; + } else + dev_dbg(s->dev, "No stop bits\n"); + + /* figure out the hardware flow control settings */ + if (cflag & CRTSCTS) { + dev_dbg(s->dev, "RTS/CTS flow control\n"); + ctrl2 |= BM_UARTAPP_CTRL2_CTSEN /* | BM_UARTAPP_CTRL2_RTSEN */ ; + } else { + dev_dbg(s->dev, "RTS/CTS disabled\n"); + ctrl2 &= ~BM_UARTAPP_CTRL2_CTSEN; + } + + /* set baud rate */ + baud = uart_get_baud_rate(u, nw, old, 0, u->uartclk); + dev_dbg(s->dev, "Baud rate requested: %d (clk = %d)\n", + baud, u->uartclk); + div = u->uartclk * 32 / baud; + ctrl |= BF(div & 0x3F, UARTAPP_LINECTRL_BAUD_DIVFRAC); + ctrl |= BF(div >> 6, UARTAPP_LINECTRL_BAUD_DIVINT); + + if ((cflag & CREAD) != 0) { + dev_dbg(s->dev, "RX started\n"); + ctrl2 |= BM_UARTAPP_CTRL2_RXE | BM_UARTAPP_CTRL2_RXDMAE; + } + + if (!err) { + dev_dbg(s->dev, "CTRLS = %x + %x\n", ctrl, ctrl2); + __raw_writel(ctrl, + s->mem + HW_UARTAPP_LINECTRL); + __raw_writel(ctrl2, + s->mem + HW_UARTAPP_CTRL2); + } +out: + return /* err */ ; +} + +static int stmp_appuart_free_irqs(struct stmp_appuart_port *s) +{ + int irqn = 0; + + if (s->keep_irq) { + dev_dbg(s->dev, "keep_irq != 0, ignoring\n"); + return 0; + } + for (irqn = 0; irqn < ARRAY_SIZE(s->irq); irqn++) + free_irq(s->irq[irqn], s); + return 0; +} + +void stmp_appuart_rx(struct stmp_appuart_port *s, u8 * rx_buffer, int count) +{ + u8 c; + int flag; + struct tty_struct *tty = s->port.info->port.tty; + u32 stat; + + spin_lock(&s->lock); + stat = __raw_readl(s->mem + HW_UARTAPP_STAT); + + if (count < 0) { + count = + __raw_readl(s->mem + + HW_UARTAPP_STAT) & BM_UARTAPP_STAT_RXCOUNT; + dev_dbg(s->dev, "count = %d\n", count); + } + + for (;;) { + if (!rx_buffer) { + if (stat & BM_UARTAPP_STAT_RXFE) + break; + c = __raw_readl(s->mem + HW_UARTAPP_DATA) & 0xFF; + } else { + if (count-- <= 0) + break; + c = *rx_buffer++; + dev_dbg(s->dev, "Received: %x(%c)\n", c, chr(c)); + } + + flag = TTY_NORMAL; + if (stat & BM_UARTAPP_STAT_BERR) { + stat &= ~BM_UARTAPP_STAT_BERR; + s->port.icount.brk++; + if (uart_handle_break(&s->port)) + goto ignore; + flag = TTY_BREAK; + } else if (stat & BM_UARTAPP_STAT_PERR) { + stat &= ~BM_UARTAPP_STAT_PERR; + s->port.icount.parity++; + flag = TTY_PARITY; + } else if (stat & BM_UARTAPP_STAT_FERR) { + stat &= ~BM_UARTAPP_STAT_FERR; + s->port.icount.frame++; + flag = TTY_FRAME; + } + + if (stat & BM_UARTAPP_STAT_OERR) + s->port.icount.overrun++; + + if (uart_handle_sysrq_char(&s->port, c)) + goto ignore; + + uart_insert_char(&s->port, stat, BM_UARTAPP_STAT_OERR, c, flag); +ignore: + if (pio_mode) { + __raw_writel(stat, s->mem + HW_UARTAPP_STAT); + stat = + __raw_readl(s->mem + HW_UARTAPP_STAT); + } + } + + __raw_writel(stat, s->mem + HW_UARTAPP_STAT); + tty_flip_buffer_push(tty); + spin_unlock(&s->lock); +} + +static inline void stmp_appuart_submit_rx(struct stmp_appuart_port *s) +{ +#ifndef RX_CHAIN + struct stmp3xxx_dma_descriptor *r = &s->rx_desc; + + dev_dbg(s->dev, "Submitting RX DMA request\n"); + r->command->cmd = + BM_APBX_CHn_CMD_HALTONTERMINATE | + BF(RX_BUFFER_SIZE, APBX_CHn_CMD_XFER_COUNT) | + BF(1, APBX_CHn_CMD_CMDWORDS) | + BM_APBX_CHn_CMD_WAIT4ENDCMD | + BM_APBX_CHn_CMD_SEMAPHORE | + BM_APBX_CHn_CMD_IRQONCMPLT | + BF(BV_APBX_CHn_CMD_COMMAND__DMA_WRITE, APBX_CHn_CMD_COMMAND); + r->command->pio_words[0] = + __raw_readl(REGS_UARTAPP1_BASE + + HW_UARTAPP_CTRL0) | BF(RX_BUFFER_SIZE, + UARTAPP_CTRL0_XFER_COUNT) | + BM_UARTAPP_CTRL0_RXTO_ENABLE | BF(3, UARTAPP_CTRL0_RXTIMEOUT); + r->command->pio_words[0] &= ~BM_UARTAPP_CTRL0_RUN; + + stmp3xxx_dma_reset_channel(s->dma_rx); + stmp3xxx_dma_go(s->dma_rx, r, 1); +#endif +} + +static irqreturn_t stmp_appuart_irq_int(int irq, void *context) +{ + u32 istatus; + struct stmp_appuart_port *s = context; + u32 stat = __raw_readl(s->mem + HW_UARTAPP_STAT); + + istatus = __raw_readl(s->mem + HW_UARTAPP_INTR); + dev_dbg(s->dev, "IRQ: int(%d), status = %08X\n", irq, istatus); + + if (istatus & BM_UARTAPP_INTR_CTSMIS) { + uart_handle_cts_change(&s->port, stat & BM_UARTAPP_STAT_CTS); + dev_dbg(s->dev, "CTS change: %x\n", stat & BM_UARTAPP_STAT_CTS); + stmp3xxx_clearl(BM_UARTAPP_INTR_CTSMIS, + s->mem + HW_UARTAPP_INTR); + } + + else if (istatus & BM_UARTAPP_INTR_RTIS) { + dev_dbg(s->dev, "RX timeout, draining out\n"); + stmp_appuart_submit_rx(s); + } + + else + dev_info(s->dev, "Unhandled status %x\n", istatus); + + stmp3xxx_clearl(istatus & 0xFFFF, + s->mem + HW_UARTAPP_INTR); + + return IRQ_HANDLED; +} + +static irqreturn_t stmp_appuart_irq_rx(int irq, void *context) +{ + struct stmp_appuart_port *s = context; + int count = -1; + + stmp3xxx_dma_clear_interrupt(s->dma_rx); + dev_dbg(s->dev, "%s(%d), count = %d\n", __func__, irq, count); + +#ifndef RX_CHAIN + stmp_appuart_rx(s, s->rx_desc.virtual_buf_ptr, count); + stmp_appuart_submit_rx(s); +#else + if (circ_advance_cooked(&s->rx_chain) == 0) { + BUG(); + return IRQ_HANDLED; + } + + circ_advance_active(&s->rx_chain, 1); + while (s->rx_chain.cooked_count) { + stmp_appuart_rx(s, + stmp3xxx_dma_circ_get_cooked_head(&s-> + rx_chain)->virtual_buf_ptr, + -1); + circ_advance_free(&s->rx_chain, 1); + } +#endif + return IRQ_HANDLED; +} + +static void stmp_appuart_submit_tx(struct stmp_appuart_port *s, int size) +{ + struct stmp3xxx_dma_descriptor *d = &s->tx_desc; + + dev_dbg(s->dev, "Submitting TX DMA request, %d bytes\n", size); + d->command->pio_words[0] = + /* BM_UARTAPP_CTRL1_RUN | */ BF(size, UARTAPP_CTRL1_XFER_COUNT); + d->command->cmd = BF(size, APBX_CHn_CMD_XFER_COUNT) | + BF(1, APBX_CHn_CMD_CMDWORDS) | + BM_APBX_CHn_CMD_WAIT4ENDCMD | + BM_APBX_CHn_CMD_SEMAPHORE | + BM_APBX_CHn_CMD_IRQONCMPLT | + BF(BV_APBX_CHn_CMD_COMMAND__DMA_READ, APBX_CHn_CMD_COMMAND); + stmp3xxx_dma_go(s->dma_tx, d, 1); +} + +static irqreturn_t stmp_appuart_irq_tx(int irq, void *context) +{ + struct stmp_appuart_port *s = context; + struct uart_port *u = &s->port; + int bytes; + + stmp3xxx_dma_clear_interrupt(s->dma_tx); + dev_dbg(s->dev, "%s(%d)\n", __func__, irq); + + bytes = stmp_appuart_copy_tx(u, s->tx_desc.virtual_buf_ptr, + TX_BUFFER_SIZE); + if (bytes > 0) { + dev_dbg(s->dev, "Sending %d bytes\n", bytes); + stmp_appuart_submit_tx(s, bytes); + } + return IRQ_HANDLED; +} + +static int stmp_appuart_request_irqs(struct stmp_appuart_port *s) +{ + int err = 0; + + /* + * order counts. resources should be listed in the same order + */ + irq_handler_t handlers[] = { + stmp_appuart_irq_int, + stmp_appuart_irq_rx, + stmp_appuart_irq_tx, + }; + char *handlers_names[] = { + "appuart internal", + "appuart rx", + "appuart tx", + }; + int irqn; + + if (s->keep_irq) { + dev_dbg(s->dev, "keep_irq is set, skipping request_irq"); + return 0; + } + for (irqn = 0; irqn < ARRAY_SIZE(handlers); irqn++) { + err = request_irq(s->irq[irqn], handlers[irqn], + 0, handlers_names[irqn], s); + dev_dbg(s->dev, "Requested IRQ %d with status %d\n", + s->irq[irqn], err); + if (err) + goto out; + } + return 0; +out: + stmp_appuart_free_irqs(s); + return err; +} + +static struct timer_list timer_task; + +static void stmp_appuart_check_rx(unsigned long data) +{ + stmp_appuart_rx((struct stmp_appuart_port *)data, NULL, -1); + mod_timer(&timer_task, jiffies + 2 * HZ); +} + +static int stmp_appuart_startup(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + int err; + + dev_dbg(s->dev, "%s\n", __func__); + + s->tx_buffer_index = 0; + + err = stmp_appuart_request_irqs(s); + if (err) + goto out; + + if (!s->keep_irq) + /* Release the block from reset and start the clocks. */ + stmp3xxx_reset_block(s->mem, 0); + + stmp3xxx_setl(BM_UARTAPP_CTRL2_UARTEN, + s->mem + HW_UARTAPP_CTRL2); + /* Enable the Application UART DMA bits. */ + if (!pio_mode) { + stmp3xxx_setl(BM_UARTAPP_CTRL2_TXDMAE | BM_UARTAPP_CTRL2_RXDMAE + | BM_UARTAPP_CTRL2_DMAONERR, + s->mem + HW_UARTAPP_CTRL2); + /* clear any pending interrupts */ + __raw_writel(0, s->mem + HW_UARTAPP_INTR); + + /* reset all dma channels */ + stmp3xxx_dma_reset_channel(s->dma_tx); + stmp3xxx_dma_reset_channel(s->dma_rx); + } else { + __raw_writel(BM_UARTAPP_INTR_RXIEN | + BM_UARTAPP_INTR_RTIEN, + s->mem + HW_UARTAPP_INTR); + } + stmp3xxx_setl(BM_UARTAPP_INTR_CTSMIEN, + s->mem + HW_UARTAPP_INTR); + + /* + * Enable fifo so all four bytes of a DMA word are written to + * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) + */ + stmp3xxx_setl(BM_UARTAPP_LINECTRL_FEN, s->mem + HW_UARTAPP_LINECTRL); + + if (!pio_mode) { +#ifndef RX_CHAIN + stmp_appuart_submit_rx(s); +#else + circ_clear_chain(&s->rx_chain); + stmp3xxx_dma_go(s->dma_rx, &s->rxd[0], 0); + circ_advance_active(&s->rx_chain, 1); +#endif + } else { + init_timer(&timer_task); + timer_task.function = stmp_appuart_check_rx; + timer_task.expires = jiffies + HZ; + timer_task.data = (unsigned long)s; + add_timer(&timer_task); + } + +out: + return err; +} + +static void stmp_appuart_shutdown(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); + + if (!s->keep_irq) + /* set the IP block to RESET; this should disable clock too. */ + stmp3xxx_setl( + BM_UARTAPP_CTRL0_SFTRST, s->mem + HW_UARTAPP_CTRL0); + + if (!pio_mode) { + /* reset all dma channels */ + stmp3xxx_dma_reset_channel(s->dma_tx); + stmp3xxx_dma_reset_channel(s->dma_rx); + } else { + del_timer(&timer_task); + } + stmp_appuart_free_irqs(s); +} + +static unsigned int stmp_appuart_tx_empty(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + if (pio_mode) + if (__raw_readl(s->mem + HW_UARTAPP_STAT) & + BM_UARTAPP_STAT_TXFE) + return TIOCSER_TEMT; + else + return 0; + else + return stmp3xxx_dma_running(s->dma_tx) ? 0 : TIOCSER_TEMT; +} + +static void stmp_appuart_start_tx(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + int bytes; + + dev_dbg(s->dev, "%s\n", __func__); + + /* enable transmitter */ + stmp3xxx_setl(BM_UARTAPP_CTRL2_TXE, s->mem + HW_UARTAPP_CTRL2); + + if (!pio_mode) { + if (stmp3xxx_dma_running(s->dma_tx)) + return; + bytes = stmp_appuart_copy_tx(u, s->tx_desc.virtual_buf_ptr, + TX_BUFFER_SIZE); + if (bytes <= 0) + return; + + dev_dbg(s->dev, "Started DMA transfer with descriptor %p, " + "command %p, %d bytes long\n", + &s->tx_desc, s->tx_desc.command, bytes); + stmp_appuart_submit_tx(s, bytes); + } else { + int count = 0; + u8 c; + + while (! + (__raw_readl + (s->mem + HW_UARTAPP_STAT) & BM_UARTAPP_STAT_TXFF)) { + if (stmp_appuart_copy_tx(u, &c, 1) <= 0) + break; + dev_dbg(s->dev, "%d: '%c'/%x\n", ++count, chr(c), c); + __raw_writel(c, s->mem + HW_UARTAPP_DATA); + } + } +} + +static void stmp_appuart_stop_tx(struct uart_port *u) +{ + struct stmp_appuart_port *s = to_appuart(u); + + dev_dbg(s->dev, "%s\n", __func__); + stmp3xxx_clearl(BM_UARTAPP_CTRL2_TXE, s->mem + HW_UARTAPP_CTRL2); +} + +static int stmp_appuart_copy_tx(struct uart_port *u, u8 * target, + int tx_buffer_size) +{ + int last = 0, portion; + struct circ_buf *xmit = &u->info->xmit; + + while (last < tx_buffer_size) { /* let's fill the only descriptor */ + if (u->x_char) { + target[last++] = u->x_char; + u->x_char = 0; + } else if (!uart_circ_empty(xmit) && !uart_tx_stopped(u)) { + portion = min((u32) tx_buffer_size, + (u32) uart_circ_chars_pending(xmit)); + portion = min((u32) portion, + (u32) CIRC_CNT_TO_END(xmit->head, + xmit->tail, + UART_XMIT_SIZE)); + memcpy(target + last, &xmit->buf[xmit->tail], portion); + xmit->tail = (xmit->tail + portion) & + (UART_XMIT_SIZE - 1); + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(u); + last += portion; + } else { /* All tx data copied into buffer */ + return last; + } + } + return last; +} + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("stmp3xxx app uart driver"); +MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>"); +module_param(pio_mode, int, 0); diff --git a/drivers/serial/stmp-app.h b/drivers/serial/stmp-app.h new file mode 100644 index 000000000000..938c89bc5214 --- /dev/null +++ b/drivers/serial/stmp-app.h @@ -0,0 +1,82 @@ +/* + * Freescale STMP37XX/STMP378X Application UART driver + * + * Author: dmitry pervushin <dimka@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __STMP_APPUART_H +#define __STMP_APPUART_H + +#define RX_BUFFER_SIZE 4 +#define TX_BUFFER_SIZE 0xFFF0 + +#include <mach/dma.h> + +/* #define RX_CHAIN 2 */ + +struct stmp_appuart_port { + int keep_irq; + int irq[3]; + void __iomem *mem; + u32 memsize; + int dma_rx, dma_tx; + struct clk *clk; + struct device *dev; + struct uart_port port; + unsigned tx_buffer_index; + struct stmp3xxx_dma_descriptor tx_desc; +#ifndef RX_CHAIN + struct stmp3xxx_dma_descriptor rx_desc; +#else + struct stmp3xxx_dma_descriptor rxd[RX_CHAIN]; + struct stmp37xx_circ_dma_chain rx_chain; +#endif + + u32 ctrl; + u8 running; + spinlock_t lock; /* protects irq handler */ +}; + +#ifdef CONFIG_CPU_FREQ +static int stmp_appuart_updateclk(struct device *dev, void *clkdata); +static int stmp_appuart_notifier(struct notifier_block *self, + unsigned long phase, void *p); +#endif /* CONFIG_CPU_FREQ */ +static int __init stmp_appuart_probe(struct platform_device *device); +static int stmp_appuart_remove(struct platform_device *device); +static int stmp_appuart_suspend(struct platform_device *device, + pm_message_t state); +static int stmp_appuart_resume(struct platform_device *device); +static int __init stmp_appuart_init(void); +static void __exit stmp_appuart_exit(void); +static int stmp_appuart_request_port(struct uart_port *u); +static void stmp_appuart_release_port(struct uart_port *u); +static int stmp_appuart_verify_port(struct uart_port *u, + struct serial_struct *); +static void stmp_appuart_config_port(struct uart_port *u, int flags); +static const char *stmp_appuart_type(struct uart_port *u); +static void stmp_appuart_settermios(struct uart_port *u, + struct ktermios *nw, struct ktermios *old); +static void stmp_appuart_shutdown(struct uart_port *u); +static int stmp_appuart_startup(struct uart_port *u); +static u32 stmp_appuart_get_mctrl(struct uart_port *u); +static void stmp_appuart_set_mctrl(struct uart_port *u, unsigned mctrl); +static void stmp_appuart_enable_ms(struct uart_port *port); +static void stmp_appuart_break_ctl(struct uart_port *port, int ctl); +static unsigned int stmp_appuart_tx_empty(struct uart_port *u); +static void stmp_appuart_stop_rx(struct uart_port *u); +static void stmp_appuart_start_tx(struct uart_port *u); +static void stmp_appuart_stop_tx(struct uart_port *u); +static int stmp_appuart_copy_tx(struct uart_port *u, u8 *target, int size); +#endif diff --git a/drivers/serial/stmp-dbg.c b/drivers/serial/stmp-dbg.c new file mode 100644 index 000000000000..c8c21b57281e --- /dev/null +++ b/drivers/serial/stmp-dbg.c @@ -0,0 +1,840 @@ +/* + * Freescale STMP37XX/STMP378X Debug UART driver + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Modifications for STMP36XX Debug Serial (c) 2005 Sigmatel Inc + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/autoconf.h> + +#if defined(CONFIG_SERIAL_STMP_DBG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/sysrq.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> +#include <linux/serial_core.h> +#include <linux/serial.h> +#include <linux/io.h> +#include <linux/irq.h> + +#include <mach/regs-uartdbg.h> + +#include <mach/stmp3xxx.h> +#include <mach/platform.h> + +#include "stmp-dbg.h" + +/* treated as variable unless submitted to open-source */ +#define PORT_STMPDBG 100 +#define UART_NR 1 +#define SERIAL_STMPDBG_MAJOR 204 +#define SERIAL_STMPDBG_MINOR 16 + +#define ISR_PASS_LIMIT 256 + +#define STMPDBG_DEVID "Debug UART" + + +static int force_cd = 1; + +static struct uart_driver stmpdbg_reg; + +/* + * We wrap our port structure around the generic uart_port. + */ +struct uart_stmpdbg_port { + struct uart_port port; + struct clk *clk; + unsigned int im; /* interrupt mask */ + unsigned int old_status; + int suspended; +}; + + +static void stmpdbg_stop_tx(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + + uap->im &= ~UART011_TXIM; + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); +} + +static void stmpdbg_start_tx(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + + uap->im |= UART011_TXIM; + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); +} + +static void stmpdbg_stop_rx(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + + uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| + UART011_PEIM|UART011_BEIM|UART011_OEIM); + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); +} + +static void stmpdbg_enable_ms(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + + uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); +} + +static void stmpdbg_rx_chars(struct uart_stmpdbg_port *uap) +{ + struct tty_struct *tty = uap->port.info->port.tty; + unsigned int status, ch, flag, rsr, max_count = 256; + + status = __raw_readl(uap->port.membase + UART01x_FR); + while ((status & UART01x_FR_RXFE) == 0 && max_count--) { +#if 0 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) { + if (tty->low_latency) + tty_flip_buffer_push(tty); + /* + * If this failed then we will throw away the + * bytes but must do so to clear interrupts + */ + } +#endif + + ch = __raw_readl(uap->port.membase + UART01x_DR); + flag = TTY_NORMAL; + uap->port.icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + rsr = __raw_readl(uap->port.membase + UART01x_RSR) + | UART_DUMMY_RSR_RX; + if (unlikely(rsr & UART01x_RSR_ANY)) { + if (rsr & UART01x_RSR_BE) { + rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); + uap->port.icount.brk++; + if (uart_handle_break(&uap->port)) + goto ignore_char; + } else if (rsr & UART01x_RSR_PE) + uap->port.icount.parity++; + else if (rsr & UART01x_RSR_FE) + uap->port.icount.frame++; + if (rsr & UART01x_RSR_OE) + uap->port.icount.overrun++; + + rsr &= uap->port.read_status_mask; + + if (rsr & UART01x_RSR_BE) + flag = TTY_BREAK; + else if (rsr & UART01x_RSR_PE) + flag = TTY_PARITY; + else if (rsr & UART01x_RSR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&uap->port, ch)) + goto ignore_char; + + uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); + +ignore_char: + status = __raw_readl(uap->port.membase + UART01x_FR); + } + tty_flip_buffer_push(tty); + return; +} + +static void stmpdbg_tx_chars(struct uart_stmpdbg_port *uap) +{ + struct circ_buf *xmit = &uap->port.info->xmit; + int count; + + if (uap->port.x_char) { + __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR); + uap->port.icount.tx++; + uap->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { + stmpdbg_stop_tx(&uap->port); + return; + } + + count = uap->port.fifosize >> 1; + do { + __raw_writel(xmit->buf[xmit->tail], + uap->port.membase + UART01x_DR); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + uap->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&uap->port); + + if (uart_circ_empty(xmit)) + stmpdbg_stop_tx(&uap->port); +} + +static void stmpdbg_modem_status(struct uart_stmpdbg_port *uap) +{ + unsigned int status, delta; + + status = __raw_readl(uap->port.membase + UART01x_FR) & + UART01x_FR_MODEM_ANY; + + delta = status ^ uap->old_status; + uap->old_status = status; + + if (!delta) + return; + + if (delta & UART01x_FR_DCD) + uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); + + if (delta & UART01x_FR_DSR) + uap->port.icount.dsr++; + + if (delta & UART01x_FR_CTS) + uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); + + wake_up_interruptible(&uap->port.info->delta_msr_wait); +} + +static irqreturn_t stmpdbg_int(int irq, void *dev_id) +{ + struct uart_stmpdbg_port *uap = dev_id; + unsigned int status, pass_counter = ISR_PASS_LIMIT; + int handled = 0; + + spin_lock(&uap->port.lock); + + status = __raw_readl(uap->port.membase + UART011_MIS); + if (status) { + do { + __raw_writel(status & ~(UART011_TXIS|UART011_RTIS| + UART011_RXIS), + uap->port.membase + UART011_ICR); + + if (status & (UART011_RTIS|UART011_RXIS)) + stmpdbg_rx_chars(uap); + if (status & (UART011_DSRMIS|UART011_DCDMIS| + UART011_CTSMIS|UART011_RIMIS)) + stmpdbg_modem_status(uap); + if (status & UART011_TXIS) + stmpdbg_tx_chars(uap); + + if (pass_counter-- == 0) + break; + + status = __raw_readl(uap->port.membase + UART011_MIS); + } while (status != 0); + handled = 1; + } + + spin_unlock(&uap->port.lock); + + return IRQ_RETVAL(handled); +} + +static unsigned int stmpdbg_tx_empty(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + unsigned int status = __raw_readl(uap->port.membase + UART01x_FR); + return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; +} + +static unsigned int stmpdbg_get_mctrl(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + unsigned int result = 0; + unsigned int status = __raw_readl(uap->port.membase + UART01x_FR); + +#define TEST_AND_SET_BIT(uartbit, tiocmbit) do { \ + if (status & uartbit) \ + result |= tiocmbit; \ + } while (0) + + TEST_AND_SET_BIT(UART01x_FR_DCD, TIOCM_CAR); + TEST_AND_SET_BIT(UART01x_FR_DSR, TIOCM_DSR); + TEST_AND_SET_BIT(UART01x_FR_CTS, TIOCM_CTS); + TEST_AND_SET_BIT(UART011_FR_RI, TIOCM_RNG); +#undef TEST_AND_SET_BIT + if (force_cd) + result |= TIOCM_CAR; + return result; +} + +static void stmpdbg_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + unsigned int cr; + + cr = __raw_readl(uap->port.membase + UART011_CR); + +#define TEST_AND_SET_BIT(tiocmbit, uartbit) do { \ + if (mctrl & tiocmbit) \ + cr |= uartbit; \ + else \ + cr &= ~uartbit; \ + } while (0) + + TEST_AND_SET_BIT(TIOCM_RTS, UART011_CR_RTS); + TEST_AND_SET_BIT(TIOCM_DTR, UART011_CR_DTR); + TEST_AND_SET_BIT(TIOCM_OUT1, UART011_CR_OUT1); + TEST_AND_SET_BIT(TIOCM_OUT2, UART011_CR_OUT2); + TEST_AND_SET_BIT(TIOCM_LOOP, UART011_CR_LBE); +#undef TEST_AND_SET_BIT + + __raw_writel(cr, uap->port.membase + UART011_CR); +} + +static void stmpdbg_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + unsigned long flags; + unsigned int lcr_h; + + spin_lock_irqsave(&uap->port.lock, flags); + lcr_h = __raw_readl(uap->port.membase + UART011_LCRH); + if (break_state == -1) + lcr_h |= UART01x_LCRH_BRK; + else + lcr_h &= ~UART01x_LCRH_BRK; + __raw_writel(lcr_h, uap->port.membase + UART011_LCRH); + spin_unlock_irqrestore(&uap->port.lock, flags); +} + +static int stmpdbg_startup(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + u32 cr, lcr; + int retval; + + /* + * Allocate the IRQ + */ + retval = request_irq(uap->port.irq, stmpdbg_int, 0, STMPDBG_DEVID, uap); + if (retval) + return retval; + + __raw_writel(0, uap->port.membase + UART01x_DR); /* wake up the UART */ + + __raw_writel(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, + uap->port.membase + UART011_IFLS); + + /* + * Provoke TX FIFO interrupt into asserting. + */ + cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + __raw_writel(cr, uap->port.membase + UART011_CR); + + lcr = __raw_readl(uap->port.membase + UART011_LCRH); + lcr |= UART01x_LCRH_FEN; + __raw_writel(lcr, uap->port.membase + UART011_LCRH); + + /* + * initialise the old status of the modem signals + */ + uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & + UART01x_FR_MODEM_ANY; + + /* + * Finally, enable interrupts + */ + spin_lock_irq(&uap->port.lock); + uap->im = UART011_RXIM | UART011_RTIM; + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); + spin_unlock_irq(&uap->port.lock); + + return 0; +} + +static void stmpdbg_shutdown(struct uart_port *port) +{ + struct uart_stmpdbg_port *uap = (struct uart_stmpdbg_port *)port; + unsigned long val; + + /* + * disable all interrupts + */ + spin_lock_irq(&uap->port.lock); + uap->im = 0; + __raw_writel(uap->im, uap->port.membase + UART011_IMSC); + __raw_writel(0xffff, uap->port.membase + UART011_ICR); + spin_unlock_irq(&uap->port.lock); + + free_irq(uap->port.irq, uap); + + /* + * disable the port + */ + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE, + uap->port.membase + UART011_CR); + + /* + * disable break condition and fifos + */ + val = __raw_readl(uap->port.membase + UART011_LCRH); + val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); + __raw_writel(val, uap->port.membase + UART011_LCRH); +} + +static void +stmpdbg_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + unsigned int lcr_h, old_cr; + unsigned long flags; + unsigned int baud, quot; + + /* + * Ask the core to calculate the divisor for us. + */ + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); + quot = port->uartclk * 4 / baud; + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr_h = UART01x_LCRH_WLEN_5; + break; + case CS6: + lcr_h = UART01x_LCRH_WLEN_6; + break; + case CS7: + lcr_h = UART01x_LCRH_WLEN_7; + break; + default: /* CS8 */ + lcr_h = UART01x_LCRH_WLEN_8; + break; + } + if (termios->c_cflag & CSTOPB) + lcr_h |= UART01x_LCRH_STP2; + if (termios->c_cflag & PARENB) { + lcr_h |= UART01x_LCRH_PEN; + if (!(termios->c_cflag & PARODD)) + lcr_h |= UART01x_LCRH_EPS; + } + lcr_h |= UART01x_LCRH_FEN; + + spin_lock_irqsave(&port->lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + port->read_status_mask = UART01x_RSR_OE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= UART01x_RSR_BE; + + /* + * Characters to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= UART01x_RSR_BE; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART01x_RSR_OE; + } + + /* + * Ignore all characters if CREAD is not set. + */ + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_RSR_RX; + + if (UART_ENABLE_MS(port, termios->c_cflag)) + stmpdbg_enable_ms(port); + + /* first, disable everything */ + old_cr = __raw_readl(port->membase + UART011_CR); + __raw_writel(0, port->membase + UART011_CR); + + /* Set baud rate */ + __raw_writel(quot & 0x3f, port->membase + UART011_FBRD); + __raw_writel(quot >> 6, port->membase + UART011_IBRD); + + /* + * ----------v----------v----------v----------v----- + * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * ----------^----------^----------^----------^----- + */ + __raw_writel(lcr_h, port->membase + UART011_LCRH); + __raw_writel(old_cr, port->membase + UART011_CR); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *stmpdbg_type(struct uart_port *port) +{ + return port->type == PORT_STMPDBG ? STMPDBG_DEVID : NULL; +} + + +/* + * Release the memory region(s) being used by 'port' + */ +static void stmpdbg_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, UART_PORT_SIZE); +} + +/* + * Request the memory region(s) being used by 'port' + */ +static int stmpdbg_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, UART_PORT_SIZE, STMPDBG_DEVID) + != NULL ? 0 : -EBUSY; +} + +/* + * Configure/autoconfigure the port. + */ +static void stmpdbg_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_STMPDBG; + stmpdbg_request_port(port); + } +} + +/* + * verify the new serial_struct (for TIOCSSERIAL). + */ +static int stmpdbg_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_STMPDBG) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= NR_IRQS) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops stmpdbg_pops = { + .tx_empty = stmpdbg_tx_empty, + .set_mctrl = stmpdbg_set_mctrl, + .get_mctrl = stmpdbg_get_mctrl, + .stop_tx = stmpdbg_stop_tx, + .start_tx = stmpdbg_start_tx, + .stop_rx = stmpdbg_stop_rx, + .enable_ms = stmpdbg_enable_ms, + .break_ctl = stmpdbg_break_ctl, + .startup = stmpdbg_startup, + .shutdown = stmpdbg_shutdown, + .set_termios = stmpdbg_set_termios, + .type = stmpdbg_type, + .release_port = stmpdbg_release_port, + .request_port = stmpdbg_request_port, + .config_port = stmpdbg_config_port, + .verify_port = stmpdbg_verify_port, +}; + +static struct uart_stmpdbg_port stmpdbg_ports[UART_NR] = { + { + .port = { + /* This *is* the virtual address */ + .membase = (void *)REGS_UARTDBG_BASE + HW_UARTDBGDR, + .mapbase = REGS_UARTDBG_PHYS + HW_UARTDBGDR, + .iotype = SERIAL_IO_MEM, + .irq = IRQ_DEBUG_UART, + .fifosize = 16, + .ops = &stmpdbg_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + .uartclk = 24000000, + }, + } +}; + +#ifdef CONFIG_SERIAL_STMP_DBG_CONSOLE + +static void +stmpdbg_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_port *port = &stmpdbg_ports[co->index].port; + unsigned int status, old_cr; + int i; + + /* + * First save the CR then disable the interrupts + */ + old_cr = UART_GET_CR(port); + UART_PUT_CR(port, UART01x_CR_UARTEN); + + /* + * Now, do each character + */ + for (i = 0; i < count; i++) { + do { + status = UART_GET_FR(port); + } while (!UART_TX_READY(status)); + UART_PUT_CHAR(port, s[i]); + if (s[i] == '\n') { + do { + status = UART_GET_FR(port); + } while (!UART_TX_READY(status)); + UART_PUT_CHAR(port, '\r'); + } + } + + /* + * Finally, wait for transmitter to become empty + * and restore the TCR + */ + do { + status = UART_GET_FR(port); + } while (status & UART01x_FR_BUSY); + UART_PUT_CR(port, old_cr); +} + +static void __init +stmpdbg_console_get_options(struct uart_port *port, int *baud, + int *parity, int *bits) +{ + if (UART_GET_CR(port) & UART01x_CR_UARTEN) { + unsigned int lcr_h, quot; + lcr_h = UART_GET_LCRH(port); + + *parity = 'n'; + if (lcr_h & UART01x_LCRH_PEN) { + if (lcr_h & UART01x_LCRH_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) + *bits = 7; + else + *bits = 8; + + quot = UART_GET_LCRL(port) | UART_GET_LCRM(port) << 8; + *baud = port->uartclk / (16 * (quot + 1)); + } +} + +static int __init stmpdbg_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= UART_NR) + co->index = 0; + port = &stmpdbg_ports[co->index].port; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + stmpdbg_console_get_options(port, &baud, &parity, &bits); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + + +static struct console stmpdbg_console = { + .name = "ttyAM", + .write = stmpdbg_console_write, + .device = uart_console_device, + .setup = stmpdbg_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &stmpdbg_reg, +}; + +static int __init stmpdbg_console_init(void) +{ + /* + * All port initializations are done statically + */ + register_console(&stmpdbg_console); + return 0; +} +console_initcall(stmpdbg_console_init); + +static int __init stmpdbg_late_console_init(void) +{ + if (!(stmpdbg_console.flags & CON_ENABLED)) + register_console(&stmpdbg_console); + return 0; +} +late_initcall(stmpdbg_late_console_init); + +#endif + +static struct uart_driver stmpdbg_reg = { + .owner = THIS_MODULE, + .driver_name = "ttyAM", + .dev_name = "ttyAM", + .major = SERIAL_STMPDBG_MAJOR, + .minor = SERIAL_STMPDBG_MINOR, + .nr = UART_NR, +#ifdef CONFIG_SERIAL_STMP_DBG_CONSOLE + .cons = &stmpdbg_console, +#endif +}; + +static int __devinit stmpdbguart_probe(struct platform_device *device) +{ + int ret = 0; + int i; + void (*cfg)(int request, int port) = NULL; + + if (device->dev.platform_data) + cfg = device->dev.platform_data; + + device_init_wakeup(&device->dev, 1); + + for (i = 0; i < UART_NR; i++) { + stmpdbg_ports[i].clk = clk_get(NULL, "uart"); + if (IS_ERR(stmpdbg_ports[i].clk)) + continue; + stmpdbg_ports[i].suspended = 0; + stmpdbg_ports[i].port.dev = &device->dev; + stmpdbg_ports[i].port.uartclk = + clk_get_rate(stmpdbg_ports[i].clk) * 1000; + if (cfg) + (*cfg)(1, i); + uart_add_one_port(&stmpdbg_reg, &stmpdbg_ports[i].port); + } + return ret; +} + +static int __devexit stmpdbguart_remove(struct platform_device *device) +{ + int i; + void (*cfg)(int request, int port) = NULL; + + if (device->dev.platform_data) + cfg = device->dev.platform_data; + for (i = 0; i < UART_NR; i++) { + clk_put(stmpdbg_ports[i].clk); + uart_remove_one_port(&stmpdbg_reg, &stmpdbg_ports[0].port); + if (cfg) + (*cfg)(0, i); + } + return 0; +} + +static int stmpdbguart_suspend(struct platform_device *device, + pm_message_t state) +{ +#ifdef CONFIG_PM + int i; + int deep_sleep = (stmp37xx_pm_get_target() != PM_SUSPEND_STANDBY); + + for (i = 0; i < UART_NR; i++) { + if (deep_sleep) { + uart_suspend_port(&stmpdbg_reg, + &stmpdbg_ports[i].port); + clk_disable(stmpdbg_ports[i].clk); + stmpdbg_ports[i].suspended = 1; + } + } +#endif + return 0; +} + +static int stmpdbguart_resume(struct platform_device *device) +{ + int ret = 0; +#ifdef CONFIG_PM + int i; + + for (i = 0; i < UART_NR; i++) { + if (stmpdbg_ports[i].suspended) { + clk_enable(stmpdbg_ports[i].clk); + uart_resume_port(&stmpdbg_reg, &stmpdbg_ports[i].port); + } + stmpdbg_ports[i].suspended = 0; + } +#endif + return ret; +} + +static struct platform_driver stmpdbguart_driver = { + .probe = stmpdbguart_probe, + .remove = __devexit_p(stmpdbguart_remove), + .suspend = stmpdbguart_suspend, + .resume = stmpdbguart_resume, + .driver = { + .name = "stmp3xxx-dbguart", + .owner = THIS_MODULE, + }, +}; + +static int __init stmpdbg_init(void) +{ + int ret; + + ret = uart_register_driver(&stmpdbg_reg); + if (ret) + goto out; + + ret = platform_driver_register(&stmpdbguart_driver); + if (ret) + uart_unregister_driver(&stmpdbg_reg); +out: + return ret; +} + +static void __exit stmpdbg_exit(void) +{ + platform_driver_unregister(&stmpdbguart_driver); + uart_unregister_driver(&stmpdbg_reg); +} + +module_init(stmpdbg_init); +module_exit(stmpdbg_exit); +module_param(force_cd, int, 0644); +MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd/Sigmatel Inc"); +MODULE_DESCRIPTION("STMP37xx debug uart"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/stmp-dbg.h b/drivers/serial/stmp-dbg.h new file mode 100644 index 000000000000..38f3e6747fb3 --- /dev/null +++ b/drivers/serial/stmp-dbg.h @@ -0,0 +1,180 @@ +/* + * Freescale STMP37XX/STMP378X Debug UART driver + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __STMP_DBG_H +#define __STMP_DBG_H +/* + * UART register offsets + */ +#define UART01x_DR 0x00 /* Data read or written */ +#define UART01x_RSR 0x04 /* Receive status register */ +#define UART01x_ECR 0x04 /* Error clear register (write) */ +#define UART010_LCRH 0x08 /* Line control register, MSB */ +#define UART010_LCRM 0x0C /* Line control register, */ +#define UART010_LCRL 0x10 /* Line control register, LSB */ +#define UART010_CR 0x14 /* Control register. */ +#define UART01x_FR 0x18 /* Flag register (Read only). */ +#define UART010_IIR 0x1C /* Interrupt identification */ +#define UART010_ICR 0x1C /* Interrupt clear register */ +#define UART01x_ILPR 0x20 /* IrDA low power counter */ +#define UART011_IBRD 0x24 /* Integer baud rate divisor */ +#define UART011_FBRD 0x28 /* Fractional baud rate divisor */ +#define UART011_LCRH 0x2c /* Line control */ +#define UART011_CR 0x30 /* Control */ +#define UART011_IFLS 0x34 /* Interrupt fifo level select */ +#define UART011_IMSC 0x38 /* Interrupt mask */ +#define UART011_RIS 0x3c /* Raw */ +#define UART011_MIS 0x40 /* Masked */ +#define UART011_ICR 0x44 /* Interrupt clear register */ +#define UART011_DMACR 0x48 /* DMA control register */ + +#define UART011_DR_OE (1 << 11) +#define UART011_DR_BE (1 << 10) +#define UART011_DR_PE (1 << 9) +#define UART011_DR_FE (1 << 8) + +#define UART01x_RSR_OE 0x08 +#define UART01x_RSR_BE 0x04 +#define UART01x_RSR_PE 0x02 +#define UART01x_RSR_FE 0x01 + +#define UART011_FR_RI 0x100 +#define UART011_FR_TXFE 0x080 +#define UART011_FR_RXFF 0x040 +#define UART01x_FR_TXFF 0x020 +#define UART01x_FR_RXFE 0x010 +#define UART01x_FR_BUSY 0x008 +#define UART01x_FR_DCD 0x004 +#define UART01x_FR_DSR 0x002 +#define UART01x_FR_CTS 0x001 +#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) + +#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ +#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */ +#define UART011_CR_OUT2 0x2000 /* OUT2 */ +#define UART011_CR_OUT1 0x1000 /* OUT1 */ +#define UART011_CR_RTS 0x0800 /* RTS */ +#define UART011_CR_DTR 0x0400 /* DTR */ +#define UART011_CR_RXE 0x0200 /* receive enable */ +#define UART011_CR_TXE 0x0100 /* transmit enable */ +#define UART011_CR_LBE 0x0080 /* loopback enable */ +#define UART010_CR_RTIE 0x0040 +#define UART010_CR_TIE 0x0020 +#define UART010_CR_RIE 0x0010 +#define UART010_CR_MSIE 0x0008 +#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ +#define UART01x_CR_SIREN 0x0002 /* SIR enable */ +#define UART01x_CR_UARTEN 0x0001 /* UART enable */ + +#define UART011_LCRH_SPS 0x80 +#define UART01x_LCRH_WLEN_8 0x60 +#define UART01x_LCRH_WLEN_7 0x40 +#define UART01x_LCRH_WLEN_6 0x20 +#define UART01x_LCRH_WLEN_5 0x00 +#define UART01x_LCRH_FEN 0x10 +#define UART01x_LCRH_STP2 0x08 +#define UART01x_LCRH_EPS 0x04 +#define UART01x_LCRH_PEN 0x02 +#define UART01x_LCRH_BRK 0x01 + +#define UART010_IIR_RTIS 0x08 +#define UART010_IIR_TIS 0x04 +#define UART010_IIR_RIS 0x02 +#define UART010_IIR_MIS 0x01 + +#define UART011_IFLS_RX1_8 (0 << 3) +#define UART011_IFLS_RX2_8 (1 << 3) +#define UART011_IFLS_RX4_8 (2 << 3) +#define UART011_IFLS_RX6_8 (3 << 3) +#define UART011_IFLS_RX7_8 (4 << 3) +#define UART011_IFLS_TX1_8 (0 << 0) +#define UART011_IFLS_TX2_8 (1 << 0) +#define UART011_IFLS_TX4_8 (2 << 0) +#define UART011_IFLS_TX6_8 (3 << 0) +#define UART011_IFLS_TX7_8 (4 << 0) + +/* Interrupt masks */ +#define UART011_OEIM (1 << 10) /* overrun error */ +#define UART011_BEIM (1 << 9) /* break error */ +#define UART011_PEIM (1 << 8) /* parity error */ +#define UART011_FEIM (1 << 7) /* framing error */ +#define UART011_RTIM (1 << 6) /* receive timeout */ +#define UART011_TXIM (1 << 5) /* transmit */ +#define UART011_RXIM (1 << 4) /* receive */ +#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */ +#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */ +#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */ +#define UART011_RIMIM (1 << 0) /* RI interrupt mask */ + +/* Interrupt statuses */ +#define UART011_OEIS (1 << 10) /* overrun error */ +#define UART011_BEIS (1 << 9) /* break error */ +#define UART011_PEIS (1 << 8) /* parity error */ +#define UART011_FEIS (1 << 7) /* framing error */ +#define UART011_RTIS (1 << 6) /* receive timeout */ +#define UART011_TXIS (1 << 5) /* transmit */ +#define UART011_RXIS (1 << 4) /* receive */ +#define UART011_DSRMIS (1 << 3) /* DSR */ +#define UART011_DCDMIS (1 << 2) /* DCD */ +#define UART011_CTSMIS (1 << 1) /* CTS */ +#define UART011_RIMIS (1 << 0) /* RI */ + +/* Interrupt clear masks */ +#define UART011_OEIC (1 << 10) /* overrun error */ +#define UART011_BEIC (1 << 9) /* break error */ +#define UART011_PEIC (1 << 8) /* parity error */ +#define UART011_FEIC (1 << 7) /* framing error */ +#define UART011_RTIC (1 << 6) /* receive timeout */ +#define UART011_TXIC (1 << 5) /* transmit */ +#define UART011_RXIC (1 << 4) /* receive */ +#define UART011_DSRMIC (1 << 3) /* DSR */ +#define UART011_DCDMIC (1 << 2) /* DCD */ +#define UART011_CTSMIC (1 << 1) /* CTS */ +#define UART011_RIMIC (1 << 0) /* RI */ + +#define UART011_DMAONERR (1 << 2) /* disable dma on error */ +#define UART011_TXDMAE (1 << 1) /* enable transmit dma */ +#define UART011_RXDMAE (1 << 0) /* enable receive dma */ + +#define UART01x_RSR_ANY (UART01x_RSR_OE | UART01x_RSR_BE | \ + UART01x_RSR_PE | UART01x_RSR_FE) +#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD | UART01x_FR_DSR | \ + UART01x_FR_CTS) + +/* + * Access macros for the AMBA UARTs + */ +#define UART_GET_INT_STATUS(p) readb((p)->membase + UART010_IIR) +#define UART_PUT_ICR(p, c) writel((c), (p)->membase + UART010_ICR) +#define UART_GET_FR(p) readb((p)->membase + UART01x_FR) +#define UART_GET_CHAR(p) readb((p)->membase + UART01x_DR) +#define UART_PUT_CHAR(p, c) writel((c), (p)->membase + UART01x_DR) +#define UART_GET_RSR(p) readb((p)->membase + UART01x_RSR) +#define UART_GET_CR(p) readb((p)->membase + UART010_CR) +#define UART_PUT_CR(p, c) writel((c), (p)->membase + UART010_CR) +#define UART_GET_LCRL(p) readb((p)->membase + UART010_LCRL) +#define UART_PUT_LCRL(p, c) writel((c), (p)->membase + UART010_LCRL) +#define UART_GET_LCRM(p) readb((p)->membase + UART010_LCRM) +#define UART_PUT_LCRM(p, c) writel((c), (p)->membase + UART010_LCRM) +#define UART_GET_LCRH(p) readb((p)->membase + UART010_LCRH) +#define UART_PUT_LCRH(p, c) writel((c), (p)->membase + UART010_LCRH) +#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) +#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) +#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART01x_FR_TMSK) == 0) + +#define UART_DUMMY_RSR_RX /*256*/0 +#define UART_PORT_SIZE 64 + +#endif /* STMP_DBG_H */ |