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-rw-r--r--drivers/tty/serial/68328serial.c25
-rw-r--r--drivers/tty/serial/68328serial.h1
-rw-r--r--drivers/tty/serial/68360serial.c6
-rw-r--r--drivers/tty/serial/8250.c33
-rw-r--r--drivers/tty/serial/Kconfig31
-rw-r--r--drivers/tty/serial/Makefile2
-rw-r--r--drivers/tty/serial/altera_jtaguart.c85
-rw-r--r--drivers/tty/serial/altera_uart.c22
-rw-r--r--drivers/tty/serial/atmel_serial.c16
-rw-r--r--drivers/tty/serial/bfin_sport_uart.c2
-rw-r--r--drivers/tty/serial/crisv10.c7
-rw-r--r--drivers/tty/serial/ifx6x60.c68
-rw-r--r--drivers/tty/serial/ifx6x60.h6
-rw-r--r--drivers/tty/serial/mfd.c73
-rw-r--r--drivers/tty/serial/mrst_max3110.c2
-rw-r--r--drivers/tty/serial/msm_serial_hs.c1880
-rw-r--r--drivers/tty/serial/msm_smd_tty.c236
-rw-r--r--drivers/tty/serial/of_serial.c18
-rw-r--r--drivers/tty/serial/omap-serial.c11
-rw-r--r--drivers/tty/serial/pch_uart.c329
-rw-r--r--drivers/tty/serial/serial_core.c22
21 files changed, 2571 insertions, 304 deletions
diff --git a/drivers/tty/serial/68328serial.c b/drivers/tty/serial/68328serial.c
index de0160e3f8c4..d5bfd41707e7 100644
--- a/drivers/tty/serial/68328serial.c
+++ b/drivers/tty/serial/68328serial.c
@@ -393,28 +393,6 @@ static void do_softint(struct work_struct *work)
#endif
}
-/*
- * This routine is called from the scheduler tqueue when the interrupt
- * routine has signalled that a hangup has occurred. The path of
- * hangup processing is:
- *
- * serial interrupt routine -> (scheduler tqueue) ->
- * do_serial_hangup() -> tty->hangup() -> rs_hangup()
- *
- */
-static void do_serial_hangup(struct work_struct *work)
-{
- struct m68k_serial *info = container_of(work, struct m68k_serial, tqueue_hangup);
- struct tty_struct *tty;
-
- tty = info->tty;
- if (!tty)
- return;
-
- tty_hangup(tty);
-}
-
-
static int startup(struct m68k_serial * info)
{
m68328_uart *uart = &uart_addr[info->line];
@@ -967,7 +945,7 @@ static void send_break(struct m68k_serial * info, unsigned int duration)
local_irq_restore(flags);
}
-static int rs_ioctl(struct tty_struct *tty, struct file * file,
+static int rs_ioctl(struct tty_struct *tty,
unsigned int cmd, unsigned long arg)
{
struct m68k_serial * info = (struct m68k_serial *)tty->driver_data;
@@ -1347,7 +1325,6 @@ rs68328_init(void)
info->count = 0;
info->blocked_open = 0;
INIT_WORK(&info->tqueue, do_softint);
- INIT_WORK(&info->tqueue_hangup, do_serial_hangup);
init_waitqueue_head(&info->open_wait);
init_waitqueue_head(&info->close_wait);
info->line = i;
diff --git a/drivers/tty/serial/68328serial.h b/drivers/tty/serial/68328serial.h
index 664ceb0a158c..8c9c3c0745db 100644
--- a/drivers/tty/serial/68328serial.h
+++ b/drivers/tty/serial/68328serial.h
@@ -159,7 +159,6 @@ struct m68k_serial {
int xmit_tail;
int xmit_cnt;
struct work_struct tqueue;
- struct work_struct tqueue_hangup;
wait_queue_head_t open_wait;
wait_queue_head_t close_wait;
};
diff --git a/drivers/tty/serial/68360serial.c b/drivers/tty/serial/68360serial.c
index bc21eeae8fde..0a3e8787ed50 100644
--- a/drivers/tty/serial/68360serial.c
+++ b/drivers/tty/serial/68360serial.c
@@ -1240,7 +1240,7 @@ static int get_lsr_info(struct async_struct * info, unsigned int *value)
}
#endif
-static int rs_360_tiocmget(struct tty_struct *tty, struct file *file)
+static int rs_360_tiocmget(struct tty_struct *tty)
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
unsigned int result = 0;
@@ -1271,7 +1271,7 @@ static int rs_360_tiocmget(struct tty_struct *tty, struct file *file)
return result;
}
-static int rs_360_tiocmset(struct tty_struct *tty, struct file *file,
+static int rs_360_tiocmset(struct tty_struct *tty,
unsigned int set, unsigned int clear)
{
#ifdef modem_control
@@ -1405,7 +1405,7 @@ static int rs_360_get_icount(struct tty_struct *tty,
return 0;
}
-static int rs_360_ioctl(struct tty_struct *tty, struct file * file,
+static int rs_360_ioctl(struct tty_struct *tty,
unsigned int cmd, unsigned long arg)
{
int error;
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 3975df6f7fdb..b3b881bc4712 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -954,6 +954,23 @@ static int broken_efr(struct uart_8250_port *up)
return 0;
}
+static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
+{
+ unsigned char status;
+
+ status = serial_in(up, 0x04); /* EXCR2 */
+#define PRESL(x) ((x) & 0x30)
+ if (PRESL(status) == 0x10) {
+ /* already in high speed mode */
+ return 0;
+ } else {
+ status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
+ status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
+ serial_outp(up, 0x04, status);
+ }
+ return 1;
+}
+
/*
* We know that the chip has FIFOs. Does it have an EFR? The
* EFR is located in the same register position as the IIR and
@@ -1025,12 +1042,8 @@ static void autoconfig_16550a(struct uart_8250_port *up)
quot = serial_dl_read(up);
quot <<= 3;
- status1 = serial_in(up, 0x04); /* EXCR2 */
- status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
- status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
- serial_outp(up, 0x04, status1);
-
- serial_dl_write(up, quot);
+ if (ns16550a_goto_highspeed(up))
+ serial_dl_write(up, quot);
serial_outp(up, UART_LCR, 0);
@@ -3025,17 +3038,13 @@ void serial8250_resume_port(int line)
struct uart_8250_port *up = &serial8250_ports[line];
if (up->capabilities & UART_NATSEMI) {
- unsigned char tmp;
-
/* Ensure it's still in high speed mode */
serial_outp(up, UART_LCR, 0xE0);
- tmp = serial_in(up, 0x04); /* EXCR2 */
- tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
- tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
- serial_outp(up, 0x04, tmp);
+ ns16550a_goto_highspeed(up);
serial_outp(up, UART_LCR, 0);
+ up->port.uartclk = 921600*16;
}
uart_resume_port(&serial8250_reg, &up->port);
}
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 2b8334601c8b..d9ccbf825095 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1319,6 +1319,18 @@ config SERIAL_MSM_CONSOLE
depends on SERIAL_MSM=y
select SERIAL_CORE_CONSOLE
+config SERIAL_MSM_HS
+ tristate "MSM UART High Speed: Serial Driver"
+ depends on ARCH_MSM
+ select SERIAL_CORE
+ help
+ If you have a machine based on MSM family of SoCs, you
+ can enable its onboard high speed serial port by enabling
+ this option.
+
+ Choose M here to compile it as a module. The module will be
+ called msm_serial_hs.
+
config SERIAL_VT8500
bool "VIA VT8500 on-chip serial port support"
depends on ARM && ARCH_VT8500
@@ -1588,12 +1600,25 @@ config SERIAL_IFX6X60
Support for the IFX6x60 modem devices on Intel MID platforms.
config SERIAL_PCH_UART
- tristate "Intel EG20T PCH UART"
- depends on PCI && DMADEVICES
+ tristate "Intel EG20T PCH UART/OKI SEMICONDUCTOR ML7213 IOH"
+ depends on PCI
select SERIAL_CORE
- select PCH_DMA
help
This driver is for PCH(Platform controller Hub) UART of Intel EG20T
which is an IOH(Input/Output Hub) for x86 embedded processor.
Enabling PCH_DMA, this PCH UART works as DMA mode.
+
+ This driver also can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/
+ Output Hub) which is for IVI(In-Vehicle Infotainment) use.
+ ML7213 is companion chip for Intel Atom E6xx series.
+ ML7213 is completely compatible for Intel EG20T PCH.
+
+config SERIAL_MSM_SMD
+ bool "Enable tty device interface for some SMD ports"
+ default n
+ depends on MSM_SMD
+ help
+ Enables userspace clients to read and write to some streaming SMD
+ ports via tty device interface for MSM chipset.
+
endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 8ea92e9c73b0..d94dc005c8a6 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
+obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
@@ -92,3 +93,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
+obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o
diff --git a/drivers/tty/serial/altera_jtaguart.c b/drivers/tty/serial/altera_jtaguart.c
index f9b49b5ff5e1..8f014bb916b7 100644
--- a/drivers/tty/serial/altera_jtaguart.c
+++ b/drivers/tty/serial/altera_jtaguart.c
@@ -305,28 +305,6 @@ static struct altera_jtaguart altera_jtaguart_ports[ALTERA_JTAGUART_MAXPORTS];
#if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE)
-int __init early_altera_jtaguart_setup(struct altera_jtaguart_platform_uart
- *platp)
-{
- struct uart_port *port;
- int i;
-
- for (i = 0; i < ALTERA_JTAGUART_MAXPORTS && platp[i].mapbase; i++) {
- port = &altera_jtaguart_ports[i].port;
-
- port->line = i;
- port->type = PORT_ALTERA_JTAGUART;
- port->mapbase = platp[i].mapbase;
- port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE);
- port->iotype = SERIAL_IO_MEM;
- port->irq = platp[i].irq;
- port->flags = ASYNC_BOOT_AUTOCONF;
- port->ops = &altera_jtaguart_ops;
- }
-
- return 0;
-}
-
#if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS)
static void altera_jtaguart_console_putc(struct console *co, const char c)
{
@@ -384,7 +362,7 @@ static int __init altera_jtaguart_console_setup(struct console *co,
if (co->index < 0 || co->index >= ALTERA_JTAGUART_MAXPORTS)
return -EINVAL;
port = &altera_jtaguart_ports[co->index].port;
- if (port->membase == 0)
+ if (port->membase == NULL)
return -ENODEV;
return 0;
}
@@ -431,22 +409,45 @@ static int __devinit altera_jtaguart_probe(struct platform_device *pdev)
{
struct altera_jtaguart_platform_uart *platp = pdev->dev.platform_data;
struct uart_port *port;
- int i;
+ struct resource *res_irq, *res_mem;
+ int i = pdev->id;
- for (i = 0; i < ALTERA_JTAGUART_MAXPORTS && platp[i].mapbase; i++) {
- port = &altera_jtaguart_ports[i].port;
+ /* -1 emphasizes that the platform must have one port, no .N suffix */
+ if (i == -1)
+ i = 0;
- port->line = i;
- port->type = PORT_ALTERA_JTAGUART;
- port->mapbase = platp[i].mapbase;
- port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE);
- port->iotype = SERIAL_IO_MEM;
- port->irq = platp[i].irq;
- port->ops = &altera_jtaguart_ops;
- port->flags = ASYNC_BOOT_AUTOCONF;
+ if (i >= ALTERA_JTAGUART_MAXPORTS)
+ return -EINVAL;
- uart_add_one_port(&altera_jtaguart_driver, port);
- }
+ port = &altera_jtaguart_ports[i].port;
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res_mem)
+ port->mapbase = res_mem->start;
+ else if (platp)
+ port->mapbase = platp->mapbase;
+ else
+ return -ENODEV;
+
+ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res_irq)
+ port->irq = res_irq->start;
+ else if (platp)
+ port->irq = platp->irq;
+ else
+ return -ENODEV;
+
+ port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE);
+ if (!port->membase)
+ return -ENOMEM;
+
+ port->line = i;
+ port->type = PORT_ALTERA_JTAGUART;
+ port->iotype = SERIAL_IO_MEM;
+ port->ops = &altera_jtaguart_ops;
+ port->flags = UPF_BOOT_AUTOCONF;
+
+ uart_add_one_port(&altera_jtaguart_driver, port);
return 0;
}
@@ -454,13 +455,13 @@ static int __devinit altera_jtaguart_probe(struct platform_device *pdev)
static int __devexit altera_jtaguart_remove(struct platform_device *pdev)
{
struct uart_port *port;
- int i;
+ int i = pdev->id;
- for (i = 0; i < ALTERA_JTAGUART_MAXPORTS; i++) {
- port = &altera_jtaguart_ports[i].port;
- if (port)
- uart_remove_one_port(&altera_jtaguart_driver, port);
- }
+ if (i == -1)
+ i = 0;
+
+ port = &altera_jtaguart_ports[i].port;
+ uart_remove_one_port(&altera_jtaguart_driver, port);
return 0;
}
diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c
index 721216292a50..3a573528555e 100644
--- a/drivers/tty/serial/altera_uart.c
+++ b/drivers/tty/serial/altera_uart.c
@@ -86,16 +86,12 @@ struct altera_uart {
static u32 altera_uart_readl(struct uart_port *port, int reg)
{
- struct altera_uart_platform_uart *platp = port->private_data;
-
- return readl(port->membase + (reg << platp->bus_shift));
+ return readl(port->membase + (reg << port->regshift));
}
static void altera_uart_writel(struct uart_port *port, u32 dat, int reg)
{
- struct altera_uart_platform_uart *platp = port->private_data;
-
- writel(dat, port->membase + (reg << platp->bus_shift));
+ writel(dat, port->membase + (reg << port->regshift));
}
static unsigned int altera_uart_tx_empty(struct uart_port *port)
@@ -546,13 +542,17 @@ static int __devinit altera_uart_probe(struct platform_device *pdev)
if (!port->membase)
return -ENOMEM;
+ if (platp)
+ port->regshift = platp->bus_shift;
+ else
+ port->regshift = 0;
+
port->line = i;
port->type = PORT_ALTERA_UART;
port->iotype = SERIAL_IO_MEM;
port->uartclk = platp->uartclk;
port->ops = &altera_uart_ops;
port->flags = UPF_BOOT_AUTOCONF;
- port->private_data = platp;
uart_add_one_port(&altera_uart_driver, port);
@@ -561,9 +561,15 @@ static int __devinit altera_uart_probe(struct platform_device *pdev)
static int __devexit altera_uart_remove(struct platform_device *pdev)
{
- struct uart_port *port = &altera_uart_ports[pdev->id].port;
+ struct uart_port *port;
+ int i = pdev->id;
+ if (i == -1)
+ i = 0;
+
+ port = &altera_uart_ports[i].port;
uart_remove_one_port(&altera_uart_driver, port);
+
return 0;
}
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 2a1d52fb4936..f119d1761106 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -1240,6 +1240,21 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
spin_unlock_irqrestore(&port->lock, flags);
}
+static void atmel_set_ldisc(struct uart_port *port, int new)
+{
+ int line = port->line;
+
+ if (line >= port->state->port.tty->driver->num)
+ return;
+
+ if (port->state->port.tty->ldisc->ops->num == N_PPS) {
+ port->flags |= UPF_HARDPPS_CD;
+ atmel_enable_ms(port);
+ } else {
+ port->flags &= ~UPF_HARDPPS_CD;
+ }
+}
+
/*
* Return string describing the specified port
*/
@@ -1380,6 +1395,7 @@ static struct uart_ops atmel_pops = {
.shutdown = atmel_shutdown,
.flush_buffer = atmel_flush_buffer,
.set_termios = atmel_set_termios,
+ .set_ldisc = atmel_set_ldisc,
.type = atmel_type,
.release_port = atmel_release_port,
.request_port = atmel_request_port,
diff --git a/drivers/tty/serial/bfin_sport_uart.c b/drivers/tty/serial/bfin_sport_uart.c
index e95c524d9d18..c3ec0a61d859 100644
--- a/drivers/tty/serial/bfin_sport_uart.c
+++ b/drivers/tty/serial/bfin_sport_uart.c
@@ -788,7 +788,7 @@ static int __devinit sport_uart_probe(struct platform_device *pdev)
sport->port.mapbase = res->start;
sport->port.irq = platform_get_irq(pdev, 0);
- if (sport->port.irq < 0) {
+ if ((int)sport->port.irq < 0) {
dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
ret = -ENOENT;
goto out_error_unmap;
diff --git a/drivers/tty/serial/crisv10.c b/drivers/tty/serial/crisv10.c
index bcc31f2140ac..225123b37f19 100644
--- a/drivers/tty/serial/crisv10.c
+++ b/drivers/tty/serial/crisv10.c
@@ -3581,8 +3581,7 @@ rs_break(struct tty_struct *tty, int break_state)
}
static int
-rs_tiocmset(struct tty_struct *tty, struct file *file,
- unsigned int set, unsigned int clear)
+rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
{
struct e100_serial *info = (struct e100_serial *)tty->driver_data;
unsigned long flags;
@@ -3614,7 +3613,7 @@ rs_tiocmset(struct tty_struct *tty, struct file *file,
}
static int
-rs_tiocmget(struct tty_struct *tty, struct file *file)
+rs_tiocmget(struct tty_struct *tty)
{
struct e100_serial *info = (struct e100_serial *)tty->driver_data;
unsigned int result;
@@ -3648,7 +3647,7 @@ rs_tiocmget(struct tty_struct *tty, struct file *file)
static int
-rs_ioctl(struct tty_struct *tty, struct file * file,
+rs_ioctl(struct tty_struct *tty,
unsigned int cmd, unsigned long arg)
{
struct e100_serial * info = (struct e100_serial *)tty->driver_data;
diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
index ab93763862d5..8ee5a41d340d 100644
--- a/drivers/tty/serial/ifx6x60.c
+++ b/drivers/tty/serial/ifx6x60.c
@@ -8,7 +8,7 @@
* Jan Dumon <j.dumon@option.com>
*
* Copyright (C) 2009, 2010 Intel Corp
- * Russ Gorby <richardx.r.gorby@intel.com>
+ * Russ Gorby <russ.gorby@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -67,6 +67,7 @@
#define IFX_SPI_MORE_MASK 0x10
#define IFX_SPI_MORE_BIT 12 /* bit position in u16 */
#define IFX_SPI_CTS_BIT 13 /* bit position in u16 */
+#define IFX_SPI_MODE SPI_MODE_1
#define IFX_SPI_TTY_ID 0
#define IFX_SPI_TIMEOUT_SEC 2
#define IFX_SPI_HEADER_0 (-1)
@@ -76,7 +77,7 @@
static void ifx_spi_handle_srdy(struct ifx_spi_device *ifx_dev);
/* local variables */
-static int spi_b16 = 1; /* 8 or 16 bit word length */
+static int spi_bpw = 16; /* 8, 16 or 32 bit word length */
static struct tty_driver *tty_drv;
static struct ifx_spi_device *saved_ifx_dev;
static struct lock_class_key ifx_spi_key;
@@ -244,7 +245,7 @@ static void ifx_spi_timeout(unsigned long arg)
* Map the signal state into Linux modem flags and report the value
* in Linux terms
*/
-static int ifx_spi_tiocmget(struct tty_struct *tty, struct file *filp)
+static int ifx_spi_tiocmget(struct tty_struct *tty)
{
unsigned int value;
struct ifx_spi_device *ifx_dev = tty->driver_data;
@@ -262,7 +263,6 @@ static int ifx_spi_tiocmget(struct tty_struct *tty, struct file *filp)
/**
* ifx_spi_tiocmset - set modem bits
* @tty: the tty structure
- * @filp: file handle issuing the request
* @set: bits to set
* @clear: bits to clear
*
@@ -271,7 +271,7 @@ static int ifx_spi_tiocmget(struct tty_struct *tty, struct file *filp)
*
* FIXME: do we need to kick the tranfers when we do this ?
*/
-static int ifx_spi_tiocmset(struct tty_struct *tty, struct file *filp,
+static int ifx_spi_tiocmset(struct tty_struct *tty,
unsigned int set, unsigned int clear)
{
struct ifx_spi_device *ifx_dev = tty->driver_data;
@@ -722,9 +722,9 @@ static void ifx_spi_io(unsigned long data)
/* note len is BYTES, not transfers */
ifx_dev->spi_xfer.len = IFX_SPI_TRANSFER_SIZE;
ifx_dev->spi_xfer.cs_change = 0;
- ifx_dev->spi_xfer.speed_hz = 12500000;
+ ifx_dev->spi_xfer.speed_hz = ifx_dev->spi_dev->max_speed_hz;
/* ifx_dev->spi_xfer.speed_hz = 390625; */
- ifx_dev->spi_xfer.bits_per_word = spi_b16 ? 16 : 8;
+ ifx_dev->spi_xfer.bits_per_word = spi_bpw;
ifx_dev->spi_xfer.tx_buf = ifx_dev->tx_buffer;
ifx_dev->spi_xfer.rx_buf = ifx_dev->rx_buffer;
@@ -732,7 +732,7 @@ static void ifx_spi_io(unsigned long data)
/*
* setup dma pointers
*/
- if (ifx_dev->is_6160) {
+ if (ifx_dev->use_dma) {
ifx_dev->spi_msg.is_dma_mapped = 1;
ifx_dev->tx_dma = ifx_dev->tx_bus;
ifx_dev->rx_dma = ifx_dev->rx_bus;
@@ -798,8 +798,8 @@ static int ifx_spi_create_port(struct ifx_spi_device *ifx_dev)
goto error_ret;
}
- pport->ops = &ifx_tty_port_ops;
tty_port_init(pport);
+ pport->ops = &ifx_tty_port_ops;
ifx_dev->minor = IFX_SPI_TTY_ID;
ifx_dev->tty_dev = tty_register_device(tty_drv, ifx_dev->minor,
&ifx_dev->spi_dev->dev);
@@ -960,7 +960,7 @@ static int ifx_spi_spi_probe(struct spi_device *spi)
{
int ret;
int srdy;
- struct ifx_modem_platform_data *pl_data = NULL;
+ struct ifx_modem_platform_data *pl_data;
struct ifx_spi_device *ifx_dev;
if (saved_ifx_dev) {
@@ -968,6 +968,12 @@ static int ifx_spi_spi_probe(struct spi_device *spi)
return -ENODEV;
}
+ pl_data = (struct ifx_modem_platform_data *)spi->dev.platform_data;
+ if (!pl_data) {
+ dev_err(&spi->dev, "missing platform data!");
+ return -ENODEV;
+ }
+
/* initialize structure to hold our device variables */
ifx_dev = kzalloc(sizeof(struct ifx_spi_device), GFP_KERNEL);
if (!ifx_dev) {
@@ -983,14 +989,25 @@ static int ifx_spi_spi_probe(struct spi_device *spi)
init_timer(&ifx_dev->spi_timer);
ifx_dev->spi_timer.function = ifx_spi_timeout;
ifx_dev->spi_timer.data = (unsigned long)ifx_dev;
- ifx_dev->is_6160 = pl_data->is_6160;
+ ifx_dev->modem = pl_data->modem_type;
+ ifx_dev->use_dma = pl_data->use_dma;
+ ifx_dev->max_hz = pl_data->max_hz;
+ /* initialize spi mode, etc */
+ spi->max_speed_hz = ifx_dev->max_hz;
+ spi->mode = IFX_SPI_MODE | (SPI_LOOP & spi->mode);
+ spi->bits_per_word = spi_bpw;
+ ret = spi_setup(spi);
+ if (ret) {
+ dev_err(&spi->dev, "SPI setup wasn't successful %d", ret);
+ return -ENODEV;
+ }
/* ensure SPI protocol flags are initialized to enable transfer */
ifx_dev->spi_more = 0;
ifx_dev->spi_slave_cts = 0;
/*initialize transfer and dma buffers */
- ifx_dev->tx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
+ ifx_dev->tx_buffer = dma_alloc_coherent(ifx_dev->spi_dev->dev.parent,
IFX_SPI_TRANSFER_SIZE,
&ifx_dev->tx_bus,
GFP_KERNEL);
@@ -999,7 +1016,7 @@ static int ifx_spi_spi_probe(struct spi_device *spi)
ret = -ENOMEM;
goto error_ret;
}
- ifx_dev->rx_buffer = dma_alloc_coherent(&ifx_dev->spi_dev->dev,
+ ifx_dev->rx_buffer = dma_alloc_coherent(ifx_dev->spi_dev->dev.parent,
IFX_SPI_TRANSFER_SIZE,
&ifx_dev->rx_bus,
GFP_KERNEL);
@@ -1025,18 +1042,11 @@ static int ifx_spi_spi_probe(struct spi_device *spi)
goto error_ret;
}
- pl_data = (struct ifx_modem_platform_data *)spi->dev.platform_data;
- if (pl_data) {
- ifx_dev->gpio.reset = pl_data->rst_pmu;
- ifx_dev->gpio.po = pl_data->pwr_on;
- ifx_dev->gpio.mrdy = pl_data->mrdy;
- ifx_dev->gpio.srdy = pl_data->srdy;
- ifx_dev->gpio.reset_out = pl_data->rst_out;
- } else {
- dev_err(&spi->dev, "missing platform data!");
- ret = -ENODEV;
- goto error_ret;
- }
+ ifx_dev->gpio.reset = pl_data->rst_pmu;
+ ifx_dev->gpio.po = pl_data->pwr_on;
+ ifx_dev->gpio.mrdy = pl_data->mrdy;
+ ifx_dev->gpio.srdy = pl_data->srdy;
+ ifx_dev->gpio.reset_out = pl_data->rst_out;
dev_info(&spi->dev, "gpios %d, %d, %d, %d, %d",
ifx_dev->gpio.reset, ifx_dev->gpio.po, ifx_dev->gpio.mrdy,
@@ -1322,9 +1332,9 @@ static const struct spi_device_id ifx_id_table[] = {
MODULE_DEVICE_TABLE(spi, ifx_id_table);
/* spi operations */
-static const struct spi_driver ifx_spi_driver_6160 = {
+static const struct spi_driver ifx_spi_driver = {
.driver = {
- .name = "ifx6160",
+ .name = DRVNAME,
.bus = &spi_bus_type,
.pm = &ifx_spi_pm,
.owner = THIS_MODULE},
@@ -1346,7 +1356,7 @@ static void __exit ifx_spi_exit(void)
{
/* unregister */
tty_unregister_driver(tty_drv);
- spi_unregister_driver((void *)&ifx_spi_driver_6160);
+ spi_unregister_driver((void *)&ifx_spi_driver);
}
/**
@@ -1388,7 +1398,7 @@ static int __init ifx_spi_init(void)
return result;
}
- result = spi_register_driver((void *)&ifx_spi_driver_6160);
+ result = spi_register_driver((void *)&ifx_spi_driver);
if (result) {
pr_err("%s: spi_register_driver failed(%d)",
DRVNAME, result);
diff --git a/drivers/tty/serial/ifx6x60.h b/drivers/tty/serial/ifx6x60.h
index deb7b8d977dc..e8464baf9e75 100644
--- a/drivers/tty/serial/ifx6x60.h
+++ b/drivers/tty/serial/ifx6x60.h
@@ -29,8 +29,6 @@
#define DRVNAME "ifx6x60"
#define TTYNAME "ttyIFX"
-/* #define IFX_THROTTLE_CODE */
-
#define IFX_SPI_MAX_MINORS 1
#define IFX_SPI_TRANSFER_SIZE 2048
#define IFX_SPI_FIFO_SIZE 4096
@@ -88,7 +86,9 @@ struct ifx_spi_device {
dma_addr_t rx_dma;
dma_addr_t tx_dma;
- int is_6160; /* Modem type */
+ int modem; /* Modem type */
+ int use_dma; /* provide dma-able addrs in SPI msg */
+ long max_hz; /* max SPI frequency */
spinlock_t write_lock;
int write_pending;
diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c
index d40010a22ecd..c111f36f5d21 100644
--- a/drivers/tty/serial/mfd.c
+++ b/drivers/tty/serial/mfd.c
@@ -16,9 +16,7 @@
* 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
* are used for RX, odd chans for TX
*
- * 2. In A0 stepping, UART will not support TX half empty flag
- *
- * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
+ * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
* asserted, only when the HW is reset the DDCD and DDSR will
* be triggered
*/
@@ -41,8 +39,6 @@
#include <linux/io.h>
#include <linux/debugfs.h>
-#define MFD_HSU_A0_STEPPING 1
-
#define HSU_DMA_BUF_SIZE 2048
#define chan_readl(chan, offset) readl(chan->reg + offset)
@@ -51,7 +47,10 @@
#define mfd_readl(obj, offset) readl(obj->reg + offset)
#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
-#define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
+static int hsu_dma_enable;
+module_param(hsu_dma_enable, int, 0);
+MODULE_PARM_DESC(hsu_dma_enable, "It is a bitmap to set working mode, if \
+bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
struct hsu_dma_buffer {
u8 *buf;
@@ -65,7 +64,6 @@ struct hsu_dma_chan {
enum dma_data_direction dirt;
struct uart_hsu_port *uport;
void __iomem *reg;
- struct timer_list rx_timer; /* only needed by RX channel */
};
struct uart_hsu_port {
@@ -355,8 +353,6 @@ void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf
| (0x1 << 24) /* timeout bit, see HSU Errata 1 */
);
chan_writel(rxc, HSU_CH_CR, 0x3);
-
- mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
}
/* Protected by spin_lock_irqsave(port->lock) */
@@ -420,7 +416,6 @@ void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
chan_writel(chan, HSU_CH_CR, 0x3);
return;
}
- del_timer(&chan->rx_timer);
dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
dbuf->dma_size, DMA_FROM_DEVICE);
@@ -448,8 +443,6 @@ void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
tty_flip_buffer_push(tty);
chan_writel(chan, HSU_CH_CR, 0x3);
- chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
- add_timer(&chan->rx_timer);
}
@@ -551,16 +544,9 @@ static void transmit_chars(struct uart_hsu_port *up)
return;
}
-#ifndef MFD_HSU_A0_STEPPING
+ /* The IRQ is for TX FIFO half-empty */
count = up->port.fifosize / 2;
-#else
- /*
- * A0 only supports fully empty IRQ, and the first char written
- * into it won't clear the EMPT bit, so we may need be cautious
- * by useing a shorter buffer
- */
- count = up->port.fifosize - 4;
-#endif
+
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -769,9 +755,8 @@ static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
/*
* What special to do:
* 1. chose the 64B fifo mode
- * 2. make sure not to select half empty mode for A0 stepping
- * 3. start dma or pio depends on configuration
- * 4. we only allocate dma memory when needed
+ * 2. start dma or pio depends on configuration
+ * 3. we only allocate dma memory when needed
*/
static int serial_hsu_startup(struct uart_port *port)
{
@@ -870,8 +855,6 @@ static void serial_hsu_shutdown(struct uart_port *port)
container_of(port, struct uart_hsu_port, port);
unsigned long flags;
- del_timer_sync(&up->rxc->rx_timer);
-
/* Disable interrupts from this port */
up->ier = 0;
serial_out(up, UART_IER, 0);
@@ -977,10 +960,6 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
fcr |= UART_FCR_HSU_64B_FIFO;
-#ifdef MFD_HSU_A0_STEPPING
- /* A0 doesn't support half empty IRQ */
- fcr |= UART_FCR_FULL_EMPT_TXI;
-#endif
/*
* Ok, we're now changing the port state. Do it with
@@ -1343,28 +1322,6 @@ err_disable:
return ret;
}
-static void hsu_dma_rx_timeout(unsigned long data)
-{
- struct hsu_dma_chan *chan = (void *)data;
- struct uart_hsu_port *up = chan->uport;
- struct hsu_dma_buffer *dbuf = &up->rxbuf;
- int count = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&up->port.lock, flags);
-
- count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
-
- if (!count) {
- mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
- goto exit;
- }
-
- hsu_dma_rx(up, 0);
-exit:
- spin_unlock_irqrestore(&up->port.lock, flags);
-}
-
static void hsu_global_init(void)
{
struct hsu_port *hsu;
@@ -1415,6 +1372,12 @@ static void hsu_global_init(void)
serial_hsu_ports[i] = uport;
uport->index = i;
+
+ if (hsu_dma_enable & (1<<i))
+ uport->use_dma = 1;
+ else
+ uport->use_dma = 0;
+
uport++;
}
@@ -1427,12 +1390,6 @@ static void hsu_global_init(void)
dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
i * HSU_DMA_CHANS_REG_LENGTH;
- /* Work around for RX */
- if (dchan->dirt == DMA_FROM_DEVICE) {
- init_timer(&dchan->rx_timer);
- dchan->rx_timer.function = hsu_dma_rx_timeout;
- dchan->rx_timer.data = (unsigned long)dchan;
- }
dchan++;
}
diff --git a/drivers/tty/serial/mrst_max3110.c b/drivers/tty/serial/mrst_max3110.c
index b62857bf2fdb..37e13c3d91d9 100644
--- a/drivers/tty/serial/mrst_max3110.c
+++ b/drivers/tty/serial/mrst_max3110.c
@@ -51,7 +51,7 @@
struct uart_max3110 {
struct uart_port port;
struct spi_device *spi;
- char name[24];
+ char name[SPI_NAME_SIZE];
wait_queue_head_t wq;
struct task_struct *main_thread;
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
new file mode 100644
index 000000000000..2e7fc9cee9cc
--- /dev/null
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -0,0 +1,1880 @@
+/*
+ * MSM 7k/8k High speed uart driver
+ *
+ * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008 Google Inc.
+ * Modified: Nick Pelly <npelly@google.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * Has optional support for uart power management independent of linux
+ * suspend/resume:
+ *
+ * RX wakeup.
+ * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
+ * UART RX pin). This should only be used if there is not a wakeup
+ * GPIO on the UART CTS, and the first RX byte is known (for example, with the
+ * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
+ * always be lost. RTS will be asserted even while the UART is off in this mode
+ * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
+ */
+
+#include <linux/module.h>
+
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <linux/atomic.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <linux/platform_data/msm_serial_hs.h>
+
+/* HSUART Registers */
+#define UARTDM_MR1_ADDR 0x0
+#define UARTDM_MR2_ADDR 0x4
+
+/* Data Mover result codes */
+#define RSLT_FIFO_CNTR_BMSK (0xE << 28)
+#define RSLT_VLD BIT(1)
+
+/* write only register */
+#define UARTDM_CSR_ADDR 0x8
+#define UARTDM_CSR_115200 0xFF
+#define UARTDM_CSR_57600 0xEE
+#define UARTDM_CSR_38400 0xDD
+#define UARTDM_CSR_28800 0xCC
+#define UARTDM_CSR_19200 0xBB
+#define UARTDM_CSR_14400 0xAA
+#define UARTDM_CSR_9600 0x99
+#define UARTDM_CSR_7200 0x88
+#define UARTDM_CSR_4800 0x77
+#define UARTDM_CSR_3600 0x66
+#define UARTDM_CSR_2400 0x55
+#define UARTDM_CSR_1200 0x44
+#define UARTDM_CSR_600 0x33
+#define UARTDM_CSR_300 0x22
+#define UARTDM_CSR_150 0x11
+#define UARTDM_CSR_75 0x00
+
+/* write only register */
+#define UARTDM_TF_ADDR 0x70
+#define UARTDM_TF2_ADDR 0x74
+#define UARTDM_TF3_ADDR 0x78
+#define UARTDM_TF4_ADDR 0x7C
+
+/* write only register */
+#define UARTDM_CR_ADDR 0x10
+#define UARTDM_IMR_ADDR 0x14
+
+#define UARTDM_IPR_ADDR 0x18
+#define UARTDM_TFWR_ADDR 0x1c
+#define UARTDM_RFWR_ADDR 0x20
+#define UARTDM_HCR_ADDR 0x24
+#define UARTDM_DMRX_ADDR 0x34
+#define UARTDM_IRDA_ADDR 0x38
+#define UARTDM_DMEN_ADDR 0x3c
+
+/* UART_DM_NO_CHARS_FOR_TX */
+#define UARTDM_NCF_TX_ADDR 0x40
+
+#define UARTDM_BADR_ADDR 0x44
+
+#define UARTDM_SIM_CFG_ADDR 0x80
+/* Read Only register */
+#define UARTDM_SR_ADDR 0x8
+
+/* Read Only register */
+#define UARTDM_RF_ADDR 0x70
+#define UARTDM_RF2_ADDR 0x74
+#define UARTDM_RF3_ADDR 0x78
+#define UARTDM_RF4_ADDR 0x7C
+
+/* Read Only register */
+#define UARTDM_MISR_ADDR 0x10
+
+/* Read Only register */
+#define UARTDM_ISR_ADDR 0x14
+#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
+
+#define UARTDM_RXFS_ADDR 0x50
+
+/* Register field Mask Mapping */
+#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
+#define UARTDM_SR_OVERRUN_BMSK BIT(4)
+#define UARTDM_SR_TXEMT_BMSK BIT(3)
+#define UARTDM_SR_TXRDY_BMSK BIT(2)
+#define UARTDM_SR_RXRDY_BMSK BIT(0)
+
+#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
+#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
+#define UARTDM_CR_TX_EN_BMSK BIT(2)
+#define UARTDM_CR_RX_EN_BMSK BIT(0)
+
+/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
+#define RESET_RX 0x10
+#define RESET_TX 0x20
+#define RESET_ERROR_STATUS 0x30
+#define RESET_BREAK_INT 0x40
+#define START_BREAK 0x50
+#define STOP_BREAK 0x60
+#define RESET_CTS 0x70
+#define RESET_STALE_INT 0x80
+#define RFR_LOW 0xD0
+#define RFR_HIGH 0xE0
+#define CR_PROTECTION_EN 0x100
+#define STALE_EVENT_ENABLE 0x500
+#define STALE_EVENT_DISABLE 0x600
+#define FORCE_STALE_EVENT 0x400
+#define CLEAR_TX_READY 0x300
+#define RESET_TX_ERROR 0x800
+#define RESET_TX_DONE 0x810
+
+#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
+#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
+#define UARTDM_MR1_CTS_CTL_BMSK 0x40
+#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
+
+#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
+#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
+
+/* bits per character configuration */
+#define FIVE_BPC (0 << 4)
+#define SIX_BPC (1 << 4)
+#define SEVEN_BPC (2 << 4)
+#define EIGHT_BPC (3 << 4)
+
+#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
+#define STOP_BIT_ONE (1 << 2)
+#define STOP_BIT_TWO (3 << 2)
+
+#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
+
+/* Parity configuration */
+#define NO_PARITY 0x0
+#define EVEN_PARITY 0x1
+#define ODD_PARITY 0x2
+#define SPACE_PARITY 0x3
+
+#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
+#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
+
+/* These can be used for both ISR and IMR register */
+#define UARTDM_ISR_TX_READY_BMSK BIT(7)
+#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
+#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
+#define UARTDM_ISR_RXLEV_BMSK BIT(4)
+#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
+#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
+#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
+#define UARTDM_ISR_TXLEV_BMSK BIT(0)
+
+/* Field definitions for UART_DM_DMEN*/
+#define UARTDM_TX_DM_EN_BMSK 0x1
+#define UARTDM_RX_DM_EN_BMSK 0x2
+
+#define UART_FIFOSIZE 64
+#define UARTCLK 7372800
+
+/* Rx DMA request states */
+enum flush_reason {
+ FLUSH_NONE,
+ FLUSH_DATA_READY,
+ FLUSH_DATA_INVALID, /* values after this indicate invalid data */
+ FLUSH_IGNORE = FLUSH_DATA_INVALID,
+ FLUSH_STOP,
+ FLUSH_SHUTDOWN,
+};
+
+/* UART clock states */
+enum msm_hs_clk_states_e {
+ MSM_HS_CLK_PORT_OFF, /* port not in use */
+ MSM_HS_CLK_OFF, /* clock disabled */
+ MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
+ MSM_HS_CLK_ON, /* clock enabled */
+};
+
+/* Track the forced RXSTALE flush during clock off sequence.
+ * These states are only valid during MSM_HS_CLK_REQUEST_OFF */
+enum msm_hs_clk_req_off_state_e {
+ CLK_REQ_OFF_START,
+ CLK_REQ_OFF_RXSTALE_ISSUED,
+ CLK_REQ_OFF_FLUSH_ISSUED,
+ CLK_REQ_OFF_RXSTALE_FLUSHED,
+};
+
+/**
+ * struct msm_hs_tx
+ * @tx_ready_int_en: ok to dma more tx?
+ * @dma_in_flight: tx dma in progress
+ * @xfer: top level DMA command pointer structure
+ * @command_ptr: third level command struct pointer
+ * @command_ptr_ptr: second level command list struct pointer
+ * @mapped_cmd_ptr: DMA view of third level command struct
+ * @mapped_cmd_ptr_ptr: DMA view of second level command list struct
+ * @tx_count: number of bytes to transfer in DMA transfer
+ * @dma_base: DMA view of UART xmit buffer
+ *
+ * This structure describes a single Tx DMA transaction. MSM DMA
+ * commands have two levels of indirection. The top level command
+ * ptr points to a list of command ptr which in turn points to a
+ * single DMA 'command'. In our case each Tx transaction consists
+ * of a single second level pointer pointing to a 'box type' command.
+ */
+struct msm_hs_tx {
+ unsigned int tx_ready_int_en;
+ unsigned int dma_in_flight;
+ struct msm_dmov_cmd xfer;
+ dmov_box *command_ptr;
+ u32 *command_ptr_ptr;
+ dma_addr_t mapped_cmd_ptr;
+ dma_addr_t mapped_cmd_ptr_ptr;
+ int tx_count;
+ dma_addr_t dma_base;
+};
+
+/**
+ * struct msm_hs_rx
+ * @flush: Rx DMA request state
+ * @xfer: top level DMA command pointer structure
+ * @cmdptr_dmaaddr: DMA view of second level command structure
+ * @command_ptr: third level DMA command pointer structure
+ * @command_ptr_ptr: second level DMA command list pointer
+ * @mapped_cmd_ptr: DMA view of the third level command structure
+ * @wait: wait for DMA completion before shutdown
+ * @buffer: destination buffer for RX DMA
+ * @rbuffer: DMA view of buffer
+ * @pool: dma pool out of which coherent rx buffer is allocated
+ * @tty_work: private work-queue for tty flip buffer push task
+ *
+ * This structure describes a single Rx DMA transaction. Rx DMA
+ * transactions use box mode DMA commands.
+ */
+struct msm_hs_rx {
+ enum flush_reason flush;
+ struct msm_dmov_cmd xfer;
+ dma_addr_t cmdptr_dmaaddr;
+ dmov_box *command_ptr;
+ u32 *command_ptr_ptr;
+ dma_addr_t mapped_cmd_ptr;
+ wait_queue_head_t wait;
+ dma_addr_t rbuffer;
+ unsigned char *buffer;
+ struct dma_pool *pool;
+ struct work_struct tty_work;
+};
+
+/**
+ * struct msm_hs_rx_wakeup
+ * @irq: IRQ line to be configured as interrupt source on Rx activity
+ * @ignore: boolean value. 1 = ignore the wakeup interrupt
+ * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
+ * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character
+ *
+ * This is an optional structure required for UART Rx GPIO IRQ based
+ * wakeup from low power state. UART wakeup can be triggered by RX activity
+ * (using a wakeup GPIO on the UART RX pin). This should only be used if
+ * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
+ * known (eg., with the Bluetooth Texas Instruments HCILL protocol),
+ * since the first RX byte will always be lost. RTS will be asserted even
+ * while the UART is clocked off in this mode of operation.
+ */
+struct msm_hs_rx_wakeup {
+ int irq; /* < 0 indicates low power wakeup disabled */
+ unsigned char ignore;
+ unsigned char inject_rx;
+ char rx_to_inject;
+};
+
+/**
+ * struct msm_hs_port
+ * @uport: embedded uart port structure
+ * @imr_reg: shadow value of UARTDM_IMR
+ * @clk: uart input clock handle
+ * @tx: Tx transaction related data structure
+ * @rx: Rx transaction related data structure
+ * @dma_tx_channel: Tx DMA command channel
+ * @dma_rx_channel Rx DMA command channel
+ * @dma_tx_crci: Tx channel rate control interface number
+ * @dma_rx_crci: Rx channel rate control interface number
+ * @clk_off_timer: Timer to poll DMA event completion before clock off
+ * @clk_off_delay: clk_off_timer poll interval
+ * @clk_state: overall clock state
+ * @clk_req_off_state: post flush clock states
+ * @rx_wakeup: optional rx_wakeup feature related data
+ * @exit_lpm_cb: optional callback to exit low power mode
+ *
+ * Low level serial port structure.
+ */
+struct msm_hs_port {
+ struct uart_port uport;
+ unsigned long imr_reg;
+ struct clk *clk;
+ struct msm_hs_tx tx;
+ struct msm_hs_rx rx;
+
+ int dma_tx_channel;
+ int dma_rx_channel;
+ int dma_tx_crci;
+ int dma_rx_crci;
+
+ struct hrtimer clk_off_timer;
+ ktime_t clk_off_delay;
+ enum msm_hs_clk_states_e clk_state;
+ enum msm_hs_clk_req_off_state_e clk_req_off_state;
+
+ struct msm_hs_rx_wakeup rx_wakeup;
+ void (*exit_lpm_cb)(struct uart_port *);
+};
+
+#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
+#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
+#define UARTDM_RX_BUF_SIZE 512
+
+#define UARTDM_NR 2
+
+static struct msm_hs_port q_uart_port[UARTDM_NR];
+static struct platform_driver msm_serial_hs_platform_driver;
+static struct uart_driver msm_hs_driver;
+static struct uart_ops msm_hs_ops;
+static struct workqueue_struct *msm_hs_workqueue;
+
+#define UARTDM_TO_MSM(uart_port) \
+ container_of((uart_port), struct msm_hs_port, uport)
+
+static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
+ *msm_uport)
+{
+ return (msm_uport->rx_wakeup.irq >= 0);
+}
+
+static unsigned int msm_hs_read(struct uart_port *uport,
+ unsigned int offset)
+{
+ return ioread32(uport->membase + offset);
+}
+
+static void msm_hs_write(struct uart_port *uport, unsigned int offset,
+ unsigned int value)
+{
+ iowrite32(value, uport->membase + offset);
+}
+
+static void msm_hs_release_port(struct uart_port *port)
+{
+ iounmap(port->membase);
+}
+
+static int msm_hs_request_port(struct uart_port *port)
+{
+ port->membase = ioremap(port->mapbase, PAGE_SIZE);
+ if (unlikely(!port->membase))
+ return -ENOMEM;
+
+ /* configure the CR Protection to Enable */
+ msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN);
+ return 0;
+}
+
+static int __devexit msm_hs_remove(struct platform_device *pdev)
+{
+
+ struct msm_hs_port *msm_uport;
+ struct device *dev;
+
+ if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
+ printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
+ return -EINVAL;
+ }
+
+ msm_uport = &q_uart_port[pdev->id];
+ dev = msm_uport->uport.dev;
+
+ dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
+ DMA_TO_DEVICE);
+ dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
+ msm_uport->rx.rbuffer);
+ dma_pool_destroy(msm_uport->rx.pool);
+
+ dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32 *),
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32 *),
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
+ DMA_TO_DEVICE);
+
+ uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
+ clk_put(msm_uport->clk);
+
+ /* Free the tx resources */
+ kfree(msm_uport->tx.command_ptr);
+ kfree(msm_uport->tx.command_ptr_ptr);
+
+ /* Free the rx resources */
+ kfree(msm_uport->rx.command_ptr);
+ kfree(msm_uport->rx.command_ptr_ptr);
+
+ iounmap(msm_uport->uport.membase);
+
+ return 0;
+}
+
+static int msm_hs_init_clk_locked(struct uart_port *uport)
+{
+ int ret;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ ret = clk_enable(msm_uport->clk);
+ if (ret) {
+ printk(KERN_ERR "Error could not turn on UART clk\n");
+ return ret;
+ }
+
+ /* Set up the MREG/NREG/DREG/MNDREG */
+ ret = clk_set_rate(msm_uport->clk, uport->uartclk);
+ if (ret) {
+ printk(KERN_WARNING "Error setting clock rate on UART\n");
+ clk_disable(msm_uport->clk);
+ return ret;
+ }
+
+ msm_uport->clk_state = MSM_HS_CLK_ON;
+ return 0;
+}
+
+/* Enable and Disable clocks (Used for power management) */
+static void msm_hs_pm(struct uart_port *uport, unsigned int state,
+ unsigned int oldstate)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ if (use_low_power_rx_wakeup(msm_uport) ||
+ msm_uport->exit_lpm_cb)
+ return; /* ignore linux PM states,
+ use msm_hs_request_clock API */
+
+ switch (state) {
+ case 0:
+ clk_enable(msm_uport->clk);
+ break;
+ case 3:
+ clk_disable(msm_uport->clk);
+ break;
+ default:
+ dev_err(uport->dev, "msm_serial: Unknown PM state %d\n",
+ state);
+ }
+}
+
+/*
+ * programs the UARTDM_CSR register with correct bit rates
+ *
+ * Interrupts should be disabled before we are called, as
+ * we modify Set Baud rate
+ * Set receive stale interrupt level, dependant on Bit Rate
+ * Goal is to have around 8 ms before indicate stale.
+ * roundup (((Bit Rate * .008) / 10) + 1
+ */
+static void msm_hs_set_bps_locked(struct uart_port *uport,
+ unsigned int bps)
+{
+ unsigned long rxstale;
+ unsigned long data;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ switch (bps) {
+ case 300:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75);
+ rxstale = 1;
+ break;
+ case 600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150);
+ rxstale = 1;
+ break;
+ case 1200:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300);
+ rxstale = 1;
+ break;
+ case 2400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600);
+ rxstale = 1;
+ break;
+ case 4800:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200);
+ rxstale = 1;
+ break;
+ case 9600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
+ rxstale = 2;
+ break;
+ case 14400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600);
+ rxstale = 3;
+ break;
+ case 19200:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800);
+ rxstale = 4;
+ break;
+ case 28800:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200);
+ rxstale = 6;
+ break;
+ case 38400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600);
+ rxstale = 8;
+ break;
+ case 57600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400);
+ rxstale = 16;
+ break;
+ case 76800:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200);
+ rxstale = 16;
+ break;
+ case 115200:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800);
+ rxstale = 31;
+ break;
+ case 230400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600);
+ rxstale = 31;
+ break;
+ case 460800:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
+ rxstale = 31;
+ break;
+ case 4000000:
+ case 3686400:
+ case 3200000:
+ case 3500000:
+ case 3000000:
+ case 2500000:
+ case 1500000:
+ case 1152000:
+ case 1000000:
+ case 921600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
+ rxstale = 31;
+ break;
+ default:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
+ /* default to 9600 */
+ bps = 9600;
+ rxstale = 2;
+ break;
+ }
+ if (bps > 460800)
+ uport->uartclk = bps * 16;
+ else
+ uport->uartclk = UARTCLK;
+
+ if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
+ printk(KERN_WARNING "Error setting clock rate on UART\n");
+ return;
+ }
+
+ data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
+ data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
+
+ msm_hs_write(uport, UARTDM_IPR_ADDR, data);
+}
+
+/*
+ * termios : new ktermios
+ * oldtermios: old ktermios previous setting
+ *
+ * Configure the serial port
+ */
+static void msm_hs_set_termios(struct uart_port *uport,
+ struct ktermios *termios,
+ struct ktermios *oldtermios)
+{
+ unsigned int bps;
+ unsigned long data;
+ unsigned long flags;
+ unsigned int c_cflag = termios->c_cflag;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ spin_lock_irqsave(&uport->lock, flags);
+ clk_enable(msm_uport->clk);
+
+ /* 300 is the minimum baud support by the driver */
+ bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000);
+
+ /* Temporary remapping 200 BAUD to 3.2 mbps */
+ if (bps == 200)
+ bps = 3200000;
+
+ msm_hs_set_bps_locked(uport, bps);
+
+ data = msm_hs_read(uport, UARTDM_MR2_ADDR);
+ data &= ~UARTDM_MR2_PARITY_MODE_BMSK;
+ /* set parity */
+ if (PARENB == (c_cflag & PARENB)) {
+ if (PARODD == (c_cflag & PARODD))
+ data |= ODD_PARITY;
+ else if (CMSPAR == (c_cflag & CMSPAR))
+ data |= SPACE_PARITY;
+ else
+ data |= EVEN_PARITY;
+ }
+
+ /* Set bits per char */
+ data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
+
+ switch (c_cflag & CSIZE) {
+ case CS5:
+ data |= FIVE_BPC;
+ break;
+ case CS6:
+ data |= SIX_BPC;
+ break;
+ case CS7:
+ data |= SEVEN_BPC;
+ break;
+ default:
+ data |= EIGHT_BPC;
+ break;
+ }
+ /* stop bits */
+ if (c_cflag & CSTOPB) {
+ data |= STOP_BIT_TWO;
+ } else {
+ /* otherwise 1 stop bit */
+ data |= STOP_BIT_ONE;
+ }
+ data |= UARTDM_MR2_ERROR_MODE_BMSK;
+ /* write parity/bits per char/stop bit configuration */
+ msm_hs_write(uport, UARTDM_MR2_ADDR, data);
+
+ /* Configure HW flow control */
+ data = msm_hs_read(uport, UARTDM_MR1_ADDR);
+
+ data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
+
+ if (c_cflag & CRTSCTS) {
+ data |= UARTDM_MR1_CTS_CTL_BMSK;
+ data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
+ }
+
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+
+ uport->ignore_status_mask = termios->c_iflag & INPCK;
+ uport->ignore_status_mask |= termios->c_iflag & IGNPAR;
+ uport->read_status_mask = (termios->c_cflag & CREAD);
+
+ msm_hs_write(uport, UARTDM_IMR_ADDR, 0);
+
+ /* Set Transmit software time out */
+ uart_update_timeout(uport, c_cflag, bps);
+
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
+
+ if (msm_uport->rx.flush == FLUSH_NONE) {
+ msm_uport->rx.flush = FLUSH_IGNORE;
+ msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
+ }
+
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+
+ clk_disable(msm_uport->clk);
+ spin_unlock_irqrestore(&uport->lock, flags);
+}
+
+/*
+ * Standard API, Transmitter
+ * Any character in the transmit shift register is sent
+ */
+static unsigned int msm_hs_tx_empty(struct uart_port *uport)
+{
+ unsigned int data;
+ unsigned int ret = 0;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ clk_enable(msm_uport->clk);
+
+ data = msm_hs_read(uport, UARTDM_SR_ADDR);
+ if (data & UARTDM_SR_TXEMT_BMSK)
+ ret = TIOCSER_TEMT;
+
+ clk_disable(msm_uport->clk);
+
+ return ret;
+}
+
+/*
+ * Standard API, Stop transmitter.
+ * Any character in the transmit shift register is sent as
+ * well as the current data mover transfer .
+ */
+static void msm_hs_stop_tx_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ msm_uport->tx.tx_ready_int_en = 0;
+}
+
+/*
+ * Standard API, Stop receiver as soon as possible.
+ *
+ * Function immediately terminates the operation of the
+ * channel receiver and any incoming characters are lost. None
+ * of the receiver status bits are affected by this command and
+ * characters that are already in the receive FIFO there.
+ */
+static void msm_hs_stop_rx_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ unsigned int data;
+
+ clk_enable(msm_uport->clk);
+
+ /* disable dlink */
+ data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
+ data &= ~UARTDM_RX_DM_EN_BMSK;
+ msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
+
+ /* Disable the receiver */
+ if (msm_uport->rx.flush == FLUSH_NONE)
+ msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
+
+ if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
+ msm_uport->rx.flush = FLUSH_STOP;
+
+ clk_disable(msm_uport->clk);
+}
+
+/* Transmit the next chunk of data */
+static void msm_hs_submit_tx_locked(struct uart_port *uport)
+{
+ int left;
+ int tx_count;
+ dma_addr_t src_addr;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ struct msm_hs_tx *tx = &msm_uport->tx;
+ struct circ_buf *tx_buf = &msm_uport->uport.state->xmit;
+
+ if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) {
+ msm_hs_stop_tx_locked(uport);
+ return;
+ }
+
+ tx->dma_in_flight = 1;
+
+ tx_count = uart_circ_chars_pending(tx_buf);
+
+ if (UARTDM_TX_BUF_SIZE < tx_count)
+ tx_count = UARTDM_TX_BUF_SIZE;
+
+ left = UART_XMIT_SIZE - tx_buf->tail;
+
+ if (tx_count > left)
+ tx_count = left;
+
+ src_addr = tx->dma_base + tx_buf->tail;
+ dma_sync_single_for_device(uport->dev, src_addr, tx_count,
+ DMA_TO_DEVICE);
+
+ tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) |
+ ((tx_count + 15) >> 4);
+ tx->command_ptr->src_row_addr = src_addr;
+
+ dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr,
+ sizeof(dmov_box), DMA_TO_DEVICE);
+
+ *tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr);
+
+ dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
+ sizeof(u32 *), DMA_TO_DEVICE);
+
+ /* Save tx_count to use in Callback */
+ tx->tx_count = tx_count;
+ msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count);
+
+ /* Disable the tx_ready interrupt */
+ msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
+}
+
+/* Start to receive the next chunk of data */
+static void msm_hs_start_rx_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
+ msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE);
+ msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE);
+ msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+
+ msm_uport->rx.flush = FLUSH_NONE;
+ msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer);
+
+ /* might have finished RX and be ready to clock off */
+ hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay,
+ HRTIMER_MODE_REL);
+}
+
+/* Enable the transmitter Interrupt */
+static void msm_hs_start_tx_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ clk_enable(msm_uport->clk);
+
+ if (msm_uport->exit_lpm_cb)
+ msm_uport->exit_lpm_cb(uport);
+
+ if (msm_uport->tx.tx_ready_int_en == 0) {
+ msm_uport->tx.tx_ready_int_en = 1;
+ msm_hs_submit_tx_locked(uport);
+ }
+
+ clk_disable(msm_uport->clk);
+}
+
+/*
+ * This routine is called when we are done with a DMA transfer
+ *
+ * This routine is registered with Data mover when we set
+ * up a Data Mover transfer. It is called from Data mover ISR
+ * when the DMA transfer is done.
+ */
+static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr,
+ unsigned int result,
+ struct msm_dmov_errdata *err)
+{
+ unsigned long flags;
+ struct msm_hs_port *msm_uport;
+
+ /* DMA did not finish properly */
+ WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) &&
+ !(result & RSLT_VLD));
+
+ msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
+
+ spin_lock_irqsave(&msm_uport->uport.lock, flags);
+ clk_enable(msm_uport->clk);
+
+ msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
+ msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+
+ clk_disable(msm_uport->clk);
+ spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
+}
+
+/*
+ * This routine is called when we are done with a DMA transfer or the
+ * a flush has been sent to the data mover driver.
+ *
+ * This routine is registered with Data mover when we set up a Data Mover
+ * transfer. It is called from Data mover ISR when the DMA transfer is done.
+ */
+static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr,
+ unsigned int result,
+ struct msm_dmov_errdata *err)
+{
+ int retval;
+ int rx_count;
+ unsigned long status;
+ unsigned int error_f = 0;
+ unsigned long flags;
+ unsigned int flush;
+ struct tty_struct *tty;
+ struct uart_port *uport;
+ struct msm_hs_port *msm_uport;
+
+ msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
+ uport = &msm_uport->uport;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ clk_enable(msm_uport->clk);
+
+ tty = uport->state->port.tty;
+
+ msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
+
+ status = msm_hs_read(uport, UARTDM_SR_ADDR);
+
+ /* overflow is not connect to data in a FIFO */
+ if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
+ (uport->read_status_mask & CREAD))) {
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ uport->icount.buf_overrun++;
+ error_f = 1;
+ }
+
+ if (!(uport->ignore_status_mask & INPCK))
+ status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
+
+ if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
+ /* Can not tell difference between parity & frame error */
+ uport->icount.parity++;
+ error_f = 1;
+ if (uport->ignore_status_mask & IGNPAR)
+ tty_insert_flip_char(tty, 0, TTY_PARITY);
+ }
+
+ if (error_f)
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
+
+ if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED)
+ msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED;
+
+ flush = msm_uport->rx.flush;
+ if (flush == FLUSH_IGNORE)
+ msm_hs_start_rx_locked(uport);
+ if (flush == FLUSH_STOP)
+ msm_uport->rx.flush = FLUSH_SHUTDOWN;
+ if (flush >= FLUSH_DATA_INVALID)
+ goto out;
+
+ rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
+
+ if (0 != (uport->read_status_mask & CREAD)) {
+ retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
+ rx_count);
+ BUG_ON(retval != rx_count);
+ }
+
+ msm_hs_start_rx_locked(uport);
+
+out:
+ clk_disable(msm_uport->clk);
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ if (flush < FLUSH_DATA_INVALID)
+ queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
+}
+
+static void msm_hs_tty_flip_buffer_work(struct work_struct *work)
+{
+ struct msm_hs_port *msm_uport =
+ container_of(work, struct msm_hs_port, rx.tty_work);
+ struct tty_struct *tty = msm_uport->uport.state->port.tty;
+
+ tty_flip_buffer_push(tty);
+}
+
+/*
+ * Standard API, Current states of modem control inputs
+ *
+ * Since CTS can be handled entirely by HARDWARE we always
+ * indicate clear to send and count on the TX FIFO to block when
+ * it fills up.
+ *
+ * - TIOCM_DCD
+ * - TIOCM_CTS
+ * - TIOCM_DSR
+ * - TIOCM_RI
+ * (Unsupported) DCD and DSR will return them high. RI will return low.
+ */
+static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport)
+{
+ return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
+}
+
+/*
+ * True enables UART auto RFR, which indicates we are ready for data if the RX
+ * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
+ * we are not ready for data. Must be called with UART clock on.
+ */
+static void set_rfr_locked(struct uart_port *uport, int auto_rfr)
+{
+ unsigned int data;
+
+ data = msm_hs_read(uport, UARTDM_MR1_ADDR);
+
+ if (auto_rfr) {
+ /* enable auto ready-for-receiving */
+ data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+ } else {
+ /* disable auto ready-for-receiving */
+ data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+ /* RFR is active low, set high */
+ msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
+ }
+}
+
+/*
+ * Standard API, used to set or clear RFR
+ */
+static void msm_hs_set_mctrl_locked(struct uart_port *uport,
+ unsigned int mctrl)
+{
+ unsigned int auto_rfr;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ clk_enable(msm_uport->clk);
+
+ auto_rfr = TIOCM_RTS & mctrl ? 1 : 0;
+ set_rfr_locked(uport, auto_rfr);
+
+ clk_disable(msm_uport->clk);
+}
+
+/* Standard API, Enable modem status (CTS) interrupt */
+static void msm_hs_enable_ms_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ clk_enable(msm_uport->clk);
+
+ /* Enable DELTA_CTS Interrupt */
+ msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+
+ clk_disable(msm_uport->clk);
+
+}
+
+/*
+ * Standard API, Break Signal
+ *
+ * Control the transmission of a break signal. ctl eq 0 => break
+ * signal terminate ctl ne 0 => start break signal
+ */
+static void msm_hs_break_ctl(struct uart_port *uport, int ctl)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ clk_enable(msm_uport->clk);
+ msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK);
+ clk_disable(msm_uport->clk);
+}
+
+static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ if (cfg_flags & UART_CONFIG_TYPE) {
+ uport->type = PORT_MSM;
+ msm_hs_request_port(uport);
+ }
+ spin_unlock_irqrestore(&uport->lock, flags);
+}
+
+/* Handle CTS changes (Called from interrupt handler) */
+static void msm_hs_handle_delta_cts(struct uart_port *uport)
+{
+ unsigned long flags;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ spin_lock_irqsave(&uport->lock, flags);
+ clk_enable(msm_uport->clk);
+
+ /* clear interrupt */
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
+ uport->icount.cts++;
+
+ clk_disable(msm_uport->clk);
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ /* clear the IOCTL TIOCMIWAIT if called */
+ wake_up_interruptible(&uport->state->port.delta_msr_wait);
+}
+
+/* check if the TX path is flushed, and if so clock off
+ * returns 0 did not clock off, need to retry (still sending final byte)
+ * -1 did not clock off, do not retry
+ * 1 if we clocked off
+ */
+static int msm_hs_check_clock_off_locked(struct uart_port *uport)
+{
+ unsigned long sr_status;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ struct circ_buf *tx_buf = &uport->state->xmit;
+
+ /* Cancel if tx tty buffer is not empty, dma is in flight,
+ * or tx fifo is not empty, or rx fifo is not empty */
+ if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF ||
+ !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight ||
+ (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||
+ !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) {
+ return -1;
+ }
+
+ /* Make sure the uart is finished with the last byte */
+ sr_status = msm_hs_read(uport, UARTDM_SR_ADDR);
+ if (!(sr_status & UARTDM_SR_TXEMT_BMSK))
+ return 0; /* retry */
+
+ /* Make sure forced RXSTALE flush complete */
+ switch (msm_uport->clk_req_off_state) {
+ case CLK_REQ_OFF_START:
+ msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED;
+ msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT);
+ return 0; /* RXSTALE flush not complete - retry */
+ case CLK_REQ_OFF_RXSTALE_ISSUED:
+ case CLK_REQ_OFF_FLUSH_ISSUED:
+ return 0; /* RXSTALE flush not complete - retry */
+ case CLK_REQ_OFF_RXSTALE_FLUSHED:
+ break; /* continue */
+ }
+
+ if (msm_uport->rx.flush != FLUSH_SHUTDOWN) {
+ if (msm_uport->rx.flush == FLUSH_NONE)
+ msm_hs_stop_rx_locked(uport);
+ return 0; /* come back later to really clock off */
+ }
+
+ /* we really want to clock off */
+ clk_disable(msm_uport->clk);
+ msm_uport->clk_state = MSM_HS_CLK_OFF;
+
+ if (use_low_power_rx_wakeup(msm_uport)) {
+ msm_uport->rx_wakeup.ignore = 1;
+ enable_irq(msm_uport->rx_wakeup.irq);
+ }
+ return 1;
+}
+
+static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer)
+{
+ unsigned long flags;
+ int ret = HRTIMER_NORESTART;
+ struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port,
+ clk_off_timer);
+ struct uart_port *uport = &msm_uport->uport;
+
+ spin_lock_irqsave(&uport->lock, flags);
+
+ if (!msm_hs_check_clock_off_locked(uport)) {
+ hrtimer_forward_now(timer, msm_uport->clk_off_delay);
+ ret = HRTIMER_RESTART;
+ }
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ return ret;
+}
+
+static irqreturn_t msm_hs_isr(int irq, void *dev)
+{
+ unsigned long flags;
+ unsigned long isr_status;
+ struct msm_hs_port *msm_uport = dev;
+ struct uart_port *uport = &msm_uport->uport;
+ struct circ_buf *tx_buf = &uport->state->xmit;
+ struct msm_hs_tx *tx = &msm_uport->tx;
+ struct msm_hs_rx *rx = &msm_uport->rx;
+
+ spin_lock_irqsave(&uport->lock, flags);
+
+ isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR);
+
+ /* Uart RX starting */
+ if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
+ msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ }
+ /* Stale rx interrupt */
+ if (isr_status & UARTDM_ISR_RXSTALE_BMSK) {
+ msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
+
+ if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED)
+ msm_uport->clk_req_off_state =
+ CLK_REQ_OFF_FLUSH_ISSUED;
+ if (rx->flush == FLUSH_NONE) {
+ rx->flush = FLUSH_DATA_READY;
+ msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
+ }
+ }
+ /* tx ready interrupt */
+ if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
+ /* Clear TX Ready */
+ msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY);
+
+ if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) {
+ msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR,
+ msm_uport->imr_reg);
+ }
+
+ /* Complete DMA TX transactions and submit new transactions */
+ tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
+
+ tx->dma_in_flight = 0;
+
+ uport->icount.tx += tx->tx_count;
+ if (tx->tx_ready_int_en)
+ msm_hs_submit_tx_locked(uport);
+
+ if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS)
+ uart_write_wakeup(uport);
+ }
+ if (isr_status & UARTDM_ISR_TXLEV_BMSK) {
+ /* TX FIFO is empty */
+ msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ if (!msm_hs_check_clock_off_locked(uport))
+ hrtimer_start(&msm_uport->clk_off_timer,
+ msm_uport->clk_off_delay,
+ HRTIMER_MODE_REL);
+ }
+
+ /* Change in CTS interrupt */
+ if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK)
+ msm_hs_handle_delta_cts(uport);
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void msm_hs_request_clock_off_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ if (msm_uport->clk_state == MSM_HS_CLK_ON) {
+ msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
+ msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
+ if (!use_low_power_rx_wakeup(msm_uport))
+ set_rfr_locked(uport, 0);
+ msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ }
+}
+
+/**
+ * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
+ * clock once pending TX is flushed and Rx DMA command is terminated.
+ * @uport: uart_port structure for the device instance.
+ *
+ * This functions puts the device into a partially active low power mode. It
+ * waits to complete all pending tx transactions, flushes ongoing Rx DMA
+ * command and terminates UART side Rx transaction, puts UART HW in non DMA
+ * mode and then clocks off the device. A client calls this when no UART
+ * data is expected. msm_request_clock_on() must be called before any further
+ * UART can be sent or received.
+ */
+void msm_hs_request_clock_off(struct uart_port *uport)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ msm_hs_request_clock_off_locked(uport);
+ spin_unlock_irqrestore(&uport->lock, flags);
+}
+
+void msm_hs_request_clock_on_locked(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ unsigned int data;
+
+ switch (msm_uport->clk_state) {
+ case MSM_HS_CLK_OFF:
+ clk_enable(msm_uport->clk);
+ disable_irq_nosync(msm_uport->rx_wakeup.irq);
+ /* fall-through */
+ case MSM_HS_CLK_REQUEST_OFF:
+ if (msm_uport->rx.flush == FLUSH_STOP ||
+ msm_uport->rx.flush == FLUSH_SHUTDOWN) {
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
+ data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
+ data |= UARTDM_RX_DM_EN_BMSK;
+ msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
+ }
+ hrtimer_try_to_cancel(&msm_uport->clk_off_timer);
+ if (msm_uport->rx.flush == FLUSH_SHUTDOWN)
+ msm_hs_start_rx_locked(uport);
+ if (!use_low_power_rx_wakeup(msm_uport))
+ set_rfr_locked(uport, 1);
+ if (msm_uport->rx.flush == FLUSH_STOP)
+ msm_uport->rx.flush = FLUSH_IGNORE;
+ msm_uport->clk_state = MSM_HS_CLK_ON;
+ break;
+ case MSM_HS_CLK_ON:
+ break;
+ case MSM_HS_CLK_PORT_OFF:
+ break;
+ }
+}
+
+/**
+ * msm_hs_request_clock_on - Switch the device from partially active low
+ * power mode to fully active (i.e. clock on) mode.
+ * @uport: uart_port structure for the device.
+ *
+ * This function switches on the input clock, puts UART HW into DMA mode
+ * and enqueues an Rx DMA command if the device was in partially active
+ * mode. It has no effect if called with the device in inactive state.
+ */
+void msm_hs_request_clock_on(struct uart_port *uport)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ msm_hs_request_clock_on_locked(uport);
+ spin_unlock_irqrestore(&uport->lock, flags);
+}
+
+static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev)
+{
+ unsigned int wakeup = 0;
+ unsigned long flags;
+ struct msm_hs_port *msm_uport = dev;
+ struct uart_port *uport = &msm_uport->uport;
+ struct tty_struct *tty = NULL;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
+ /* ignore the first irq - it is a pending irq that occured
+ * before enable_irq() */
+ if (msm_uport->rx_wakeup.ignore)
+ msm_uport->rx_wakeup.ignore = 0;
+ else
+ wakeup = 1;
+ }
+
+ if (wakeup) {
+ /* the uart was clocked off during an rx, wake up and
+ * optionally inject char into tty rx */
+ msm_hs_request_clock_on_locked(uport);
+ if (msm_uport->rx_wakeup.inject_rx) {
+ tty = uport->state->port.tty;
+ tty_insert_flip_char(tty,
+ msm_uport->rx_wakeup.rx_to_inject,
+ TTY_NORMAL);
+ queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
+ }
+ }
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static const char *msm_hs_type(struct uart_port *port)
+{
+ return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL;
+}
+
+/* Called when port is opened */
+static int msm_hs_startup(struct uart_port *uport)
+{
+ int ret;
+ int rfr_level;
+ unsigned long flags;
+ unsigned int data;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ struct circ_buf *tx_buf = &uport->state->xmit;
+ struct msm_hs_tx *tx = &msm_uport->tx;
+ struct msm_hs_rx *rx = &msm_uport->rx;
+
+ rfr_level = uport->fifosize;
+ if (rfr_level > 16)
+ rfr_level -= 16;
+
+ tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE,
+ DMA_TO_DEVICE);
+
+ /* do not let tty layer execute RX in global workqueue, use a
+ * dedicated workqueue managed by this driver */
+ uport->state->port.tty->low_latency = 1;
+
+ /* turn on uart clk */
+ ret = msm_hs_init_clk_locked(uport);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "Turning uartclk failed!\n");
+ goto err_msm_hs_init_clk;
+ }
+
+ /* Set auto RFR Level */
+ data = msm_hs_read(uport, UARTDM_MR1_ADDR);
+ data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
+ data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
+ data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2));
+ data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level);
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+
+ /* Make sure RXSTALE count is non-zero */
+ data = msm_hs_read(uport, UARTDM_IPR_ADDR);
+ if (!data) {
+ data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK;
+ msm_hs_write(uport, UARTDM_IPR_ADDR, data);
+ }
+
+ /* Enable Data Mover Mode */
+ data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK;
+ msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
+
+ /* Reset TX */
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
+ msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW);
+ /* Turn on Uart Receiver */
+ msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK);
+
+ /* Turn on Uart Transmitter */
+ msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK);
+
+ /* Initialize the tx */
+ tx->tx_ready_int_en = 0;
+ tx->dma_in_flight = 0;
+
+ tx->xfer.complete_func = msm_hs_dmov_tx_callback;
+ tx->xfer.execute_func = NULL;
+
+ tx->command_ptr->cmd = CMD_LC |
+ CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
+
+ tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
+ | (MSM_UARTDM_BURST_SIZE);
+
+ tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16);
+
+ tx->command_ptr->dst_row_addr =
+ msm_uport->uport.mapbase + UARTDM_TF_ADDR;
+
+
+ /* Turn on Uart Receive */
+ rx->xfer.complete_func = msm_hs_dmov_rx_callback;
+ rx->xfer.execute_func = NULL;
+
+ rx->command_ptr->cmd = CMD_LC |
+ CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
+
+ rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
+ | (MSM_UARTDM_BURST_SIZE);
+ rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
+ rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
+
+
+ msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
+ /* Enable reading the current CTS, no harm even if CTS is ignored */
+ msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
+
+ msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */
+
+
+ ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
+ "msm_hs_uart", msm_uport);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n");
+ goto err_request_irq;
+ }
+ if (use_low_power_rx_wakeup(msm_uport)) {
+ ret = request_irq(msm_uport->rx_wakeup.irq,
+ msm_hs_rx_wakeup_isr,
+ IRQF_TRIGGER_FALLING,
+ "msm_hs_rx_wakeup", msm_uport);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n");
+ free_irq(uport->irq, msm_uport);
+ goto err_request_irq;
+ }
+ disable_irq(msm_uport->rx_wakeup.irq);
+ }
+
+ spin_lock_irqsave(&uport->lock, flags);
+
+ msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
+ msm_hs_start_rx_locked(uport);
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+ ret = pm_runtime_set_active(uport->dev);
+ if (ret)
+ dev_err(uport->dev, "set active error:%d\n", ret);
+ pm_runtime_enable(uport->dev);
+
+ return 0;
+
+err_request_irq:
+err_msm_hs_init_clk:
+ dma_unmap_single(uport->dev, tx->dma_base,
+ UART_XMIT_SIZE, DMA_TO_DEVICE);
+ return ret;
+}
+
+/* Initialize tx and rx data structures */
+static int __devinit uartdm_init_port(struct uart_port *uport)
+{
+ int ret = 0;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ struct msm_hs_tx *tx = &msm_uport->tx;
+ struct msm_hs_rx *rx = &msm_uport->rx;
+
+ /* Allocate the command pointer. Needs to be 64 bit aligned */
+ tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
+ if (!tx->command_ptr)
+ return -ENOMEM;
+
+ tx->command_ptr_ptr = kmalloc(sizeof(u32 *), GFP_KERNEL | __GFP_DMA);
+ if (!tx->command_ptr_ptr) {
+ ret = -ENOMEM;
+ goto err_tx_command_ptr_ptr;
+ }
+
+ tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
+ sizeof(dmov_box), DMA_TO_DEVICE);
+ tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev,
+ tx->command_ptr_ptr,
+ sizeof(u32 *), DMA_TO_DEVICE);
+ tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
+
+ init_waitqueue_head(&rx->wait);
+
+ rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
+ UARTDM_RX_BUF_SIZE, 16, 0);
+ if (!rx->pool) {
+ pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
+ ret = -ENOMEM;
+ goto err_dma_pool_create;
+ }
+
+ rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
+ if (!rx->buffer) {
+ pr_err("%s(): cannot allocate rx->buffer", __func__);
+ ret = -ENOMEM;
+ goto err_dma_pool_alloc;
+ }
+
+ /* Allocate the command pointer. Needs to be 64 bit aligned */
+ rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
+ if (!rx->command_ptr) {
+ pr_err("%s(): cannot allocate rx->command_ptr", __func__);
+ ret = -ENOMEM;
+ goto err_rx_command_ptr;
+ }
+
+ rx->command_ptr_ptr = kmalloc(sizeof(u32 *), GFP_KERNEL | __GFP_DMA);
+ if (!rx->command_ptr_ptr) {
+ pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
+ ret = -ENOMEM;
+ goto err_rx_command_ptr_ptr;
+ }
+
+ rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
+ (UARTDM_RX_BUF_SIZE >> 4);
+
+ rx->command_ptr->dst_row_addr = rx->rbuffer;
+
+ rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
+ sizeof(dmov_box), DMA_TO_DEVICE);
+
+ *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr);
+
+ rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr,
+ sizeof(u32 *), DMA_TO_DEVICE);
+ rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
+
+ INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work);
+
+ return ret;
+
+err_rx_command_ptr_ptr:
+ kfree(rx->command_ptr);
+err_rx_command_ptr:
+ dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
+ msm_uport->rx.rbuffer);
+err_dma_pool_alloc:
+ dma_pool_destroy(msm_uport->rx.pool);
+err_dma_pool_create:
+ dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
+ sizeof(u32 *), DMA_TO_DEVICE);
+ dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
+ sizeof(dmov_box), DMA_TO_DEVICE);
+ kfree(msm_uport->tx.command_ptr_ptr);
+err_tx_command_ptr_ptr:
+ kfree(msm_uport->tx.command_ptr);
+ return ret;
+}
+
+static int __devinit msm_hs_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct uart_port *uport;
+ struct msm_hs_port *msm_uport;
+ struct resource *resource;
+ const struct msm_serial_hs_platform_data *pdata =
+ pdev->dev.platform_data;
+
+ if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
+ printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
+ return -EINVAL;
+ }
+
+ msm_uport = &q_uart_port[pdev->id];
+ uport = &msm_uport->uport;
+
+ uport->dev = &pdev->dev;
+
+ resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!resource))
+ return -ENXIO;
+
+ uport->mapbase = resource->start;
+ uport->irq = platform_get_irq(pdev, 0);
+ if (unlikely(uport->irq < 0))
+ return -ENXIO;
+
+ if (unlikely(set_irq_wake(uport->irq, 1)))
+ return -ENXIO;
+
+ if (pdata == NULL || pdata->rx_wakeup_irq < 0)
+ msm_uport->rx_wakeup.irq = -1;
+ else {
+ msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq;
+ msm_uport->rx_wakeup.ignore = 1;
+ msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup;
+ msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject;
+
+ if (unlikely(msm_uport->rx_wakeup.irq < 0))
+ return -ENXIO;
+
+ if (unlikely(set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
+ return -ENXIO;
+ }
+
+ if (pdata == NULL)
+ msm_uport->exit_lpm_cb = NULL;
+ else
+ msm_uport->exit_lpm_cb = pdata->exit_lpm_cb;
+
+ resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+ "uartdm_channels");
+ if (unlikely(!resource))
+ return -ENXIO;
+
+ msm_uport->dma_tx_channel = resource->start;
+ msm_uport->dma_rx_channel = resource->end;
+
+ resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+ "uartdm_crci");
+ if (unlikely(!resource))
+ return -ENXIO;
+
+ msm_uport->dma_tx_crci = resource->start;
+ msm_uport->dma_rx_crci = resource->end;
+
+ uport->iotype = UPIO_MEM;
+ uport->fifosize = UART_FIFOSIZE;
+ uport->ops = &msm_hs_ops;
+ uport->flags = UPF_BOOT_AUTOCONF;
+ uport->uartclk = UARTCLK;
+ msm_uport->imr_reg = 0x0;
+ msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk");
+ if (IS_ERR(msm_uport->clk))
+ return PTR_ERR(msm_uport->clk);
+
+ ret = uartdm_init_port(uport);
+ if (unlikely(ret))
+ return ret;
+
+ msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
+ hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC,
+ HRTIMER_MODE_REL);
+ msm_uport->clk_off_timer.function = msm_hs_clk_off_retry;
+ msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */
+
+ uport->line = pdev->id;
+ return uart_add_one_port(&msm_hs_driver, uport);
+}
+
+static int __init msm_serial_hs_init(void)
+{
+ int ret, i;
+
+ /* Init all UARTS as non-configured */
+ for (i = 0; i < UARTDM_NR; i++)
+ q_uart_port[i].uport.type = PORT_UNKNOWN;
+
+ msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs");
+ if (unlikely(!msm_hs_workqueue))
+ return -ENOMEM;
+
+ ret = uart_register_driver(&msm_hs_driver);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "%s failed to load\n", __func__);
+ goto err_uart_register_driver;
+ }
+
+ ret = platform_driver_register(&msm_serial_hs_platform_driver);
+ if (ret) {
+ printk(KERN_ERR "%s failed to load\n", __func__);
+ goto err_platform_driver_register;
+ }
+
+ return ret;
+
+err_platform_driver_register:
+ uart_unregister_driver(&msm_hs_driver);
+err_uart_register_driver:
+ destroy_workqueue(msm_hs_workqueue);
+ return ret;
+}
+module_init(msm_serial_hs_init);
+
+/*
+ * Called by the upper layer when port is closed.
+ * - Disables the port
+ * - Unhook the ISR
+ */
+static void msm_hs_shutdown(struct uart_port *uport)
+{
+ unsigned long flags;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
+
+ spin_lock_irqsave(&uport->lock, flags);
+ clk_enable(msm_uport->clk);
+
+ /* Disable the transmitter */
+ msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK);
+ /* Disable the receiver */
+ msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK);
+
+ pm_runtime_disable(uport->dev);
+ pm_runtime_set_suspended(uport->dev);
+
+ /* Free the interrupt */
+ free_irq(uport->irq, msm_uport);
+ if (use_low_power_rx_wakeup(msm_uport))
+ free_irq(msm_uport->rx_wakeup.irq, msm_uport);
+
+ msm_uport->imr_reg = 0;
+ msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+
+ wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
+
+ clk_disable(msm_uport->clk); /* to balance local clk_enable() */
+ if (msm_uport->clk_state != MSM_HS_CLK_OFF)
+ clk_disable(msm_uport->clk); /* to balance clk_state */
+ msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
+
+ dma_unmap_single(uport->dev, msm_uport->tx.dma_base,
+ UART_XMIT_SIZE, DMA_TO_DEVICE);
+
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ if (cancel_work_sync(&msm_uport->rx.tty_work))
+ msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work);
+}
+
+static void __exit msm_serial_hs_exit(void)
+{
+ flush_workqueue(msm_hs_workqueue);
+ destroy_workqueue(msm_hs_workqueue);
+ platform_driver_unregister(&msm_serial_hs_platform_driver);
+ uart_unregister_driver(&msm_hs_driver);
+}
+module_exit(msm_serial_hs_exit);
+
+#ifdef CONFIG_PM_RUNTIME
+static int msm_hs_runtime_idle(struct device *dev)
+{
+ /*
+ * returning success from idle results in runtime suspend to be
+ * called
+ */
+ return 0;
+}
+
+static int msm_hs_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = container_of(dev, struct
+ platform_device, dev);
+ struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
+
+ msm_hs_request_clock_on(&msm_uport->uport);
+ return 0;
+}
+
+static int msm_hs_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = container_of(dev, struct
+ platform_device, dev);
+ struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
+
+ msm_hs_request_clock_off(&msm_uport->uport);
+ return 0;
+}
+#else
+#define msm_hs_runtime_idle NULL
+#define msm_hs_runtime_resume NULL
+#define msm_hs_runtime_suspend NULL
+#endif
+
+static const struct dev_pm_ops msm_hs_dev_pm_ops = {
+ .runtime_suspend = msm_hs_runtime_suspend,
+ .runtime_resume = msm_hs_runtime_resume,
+ .runtime_idle = msm_hs_runtime_idle,
+};
+
+static struct platform_driver msm_serial_hs_platform_driver = {
+ .probe = msm_hs_probe,
+ .remove = __devexit_p(msm_hs_remove),
+ .driver = {
+ .name = "msm_serial_hs",
+ .owner = THIS_MODULE,
+ .pm = &msm_hs_dev_pm_ops,
+ },
+};
+
+static struct uart_driver msm_hs_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "msm_serial_hs",
+ .dev_name = "ttyHS",
+ .nr = UARTDM_NR,
+ .cons = 0,
+};
+
+static struct uart_ops msm_hs_ops = {
+ .tx_empty = msm_hs_tx_empty,
+ .set_mctrl = msm_hs_set_mctrl_locked,
+ .get_mctrl = msm_hs_get_mctrl_locked,
+ .stop_tx = msm_hs_stop_tx_locked,
+ .start_tx = msm_hs_start_tx_locked,
+ .stop_rx = msm_hs_stop_rx_locked,
+ .enable_ms = msm_hs_enable_ms_locked,
+ .break_ctl = msm_hs_break_ctl,
+ .startup = msm_hs_startup,
+ .shutdown = msm_hs_shutdown,
+ .set_termios = msm_hs_set_termios,
+ .pm = msm_hs_pm,
+ .type = msm_hs_type,
+ .config_port = msm_hs_config_port,
+ .release_port = msm_hs_release_port,
+ .request_port = msm_hs_request_port,
+};
+
+MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
+MODULE_VERSION("1.2");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/msm_smd_tty.c b/drivers/tty/serial/msm_smd_tty.c
new file mode 100644
index 000000000000..beeff1e86093
--- /dev/null
+++ b/drivers/tty/serial/msm_smd_tty.c
@@ -0,0 +1,236 @@
+/* drivers/tty/serial/msm_smd_tty.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+
+#include <mach/msm_smd.h>
+
+#define MAX_SMD_TTYS 32
+
+struct smd_tty_info {
+ struct tty_port port;
+ smd_channel_t *ch;
+};
+
+struct smd_tty_channel_desc {
+ int id;
+ const char *name;
+};
+
+static struct smd_tty_info smd_tty[MAX_SMD_TTYS];
+
+static const struct smd_tty_channel_desc smd_default_tty_channels[] = {
+ { .id = 0, .name = "SMD_DS" },
+ { .id = 27, .name = "SMD_GPSNMEA" },
+};
+
+static const struct smd_tty_channel_desc *smd_tty_channels =
+ smd_default_tty_channels;
+static int smd_tty_channels_len = ARRAY_SIZE(smd_default_tty_channels);
+
+static void smd_tty_notify(void *priv, unsigned event)
+{
+ unsigned char *ptr;
+ int avail;
+ struct smd_tty_info *info = priv;
+ struct tty_struct *tty;
+
+ if (event != SMD_EVENT_DATA)
+ return;
+
+ tty = tty_port_tty_get(&info->port);
+ if (!tty)
+ return;
+
+ for (;;) {
+ if (test_bit(TTY_THROTTLED, &tty->flags))
+ break;
+ avail = smd_read_avail(info->ch);
+ if (avail == 0)
+ break;
+
+ avail = tty_prepare_flip_string(tty, &ptr, avail);
+
+ if (smd_read(info->ch, ptr, avail) != avail) {
+ /* shouldn't be possible since we're in interrupt
+ ** context here and nobody else could 'steal' our
+ ** characters.
+ */
+ pr_err("OOPS - smd_tty_buffer mismatch?!");
+ }
+
+ tty_flip_buffer_push(tty);
+ }
+
+ /* XXX only when writable and necessary */
+ tty_wakeup(tty);
+ tty_kref_put(tty);
+}
+
+static int smd_tty_port_activate(struct tty_port *tport, struct tty_struct *tty)
+{
+ int i, res = 0;
+ int n = tty->index;
+ const char *name = NULL;
+ struct smd_tty_info *info = smd_tty + n;
+
+ for (i = 0; i < smd_tty_channels_len; i++) {
+ if (smd_tty_channels[i].id == n) {
+ name = smd_tty_channels[i].name;
+ break;
+ }
+ }
+ if (!name)
+ return -ENODEV;
+
+ if (info->ch)
+ smd_kick(info->ch);
+ else
+ res = smd_open(name, &info->ch, info, smd_tty_notify);
+
+ if (!res)
+ tty->driver_data = info;
+
+ return res;
+}
+
+static void smd_tty_port_shutdown(struct tty_port *tport)
+{
+ struct smd_tty_info *info;
+ struct tty_struct *tty = tty_port_tty_get(tport);
+
+ info = tty->driver_data;
+ if (info->ch) {
+ smd_close(info->ch);
+ info->ch = 0;
+ }
+
+ tty->driver_data = 0;
+ tty_kref_put(tty);
+}
+
+static int smd_tty_open(struct tty_struct *tty, struct file *f)
+{
+ struct smd_tty_info *info = smd_tty + tty->index;
+
+ return tty_port_open(&info->port, tty, f);
+}
+
+static void smd_tty_close(struct tty_struct *tty, struct file *f)
+{
+ struct smd_tty_info *info = tty->driver_data;
+
+ tty_port_close(&info->port, tty, f);
+}
+
+static int smd_tty_write(struct tty_struct *tty,
+ const unsigned char *buf, int len)
+{
+ struct smd_tty_info *info = tty->driver_data;
+ int avail;
+
+ /* if we're writing to a packet channel we will
+ ** never be able to write more data than there
+ ** is currently space for
+ */
+ avail = smd_write_avail(info->ch);
+ if (len > avail)
+ len = avail;
+
+ return smd_write(info->ch, buf, len);
+}
+
+static int smd_tty_write_room(struct tty_struct *tty)
+{
+ struct smd_tty_info *info = tty->driver_data;
+ return smd_write_avail(info->ch);
+}
+
+static int smd_tty_chars_in_buffer(struct tty_struct *tty)
+{
+ struct smd_tty_info *info = tty->driver_data;
+ return smd_read_avail(info->ch);
+}
+
+static void smd_tty_unthrottle(struct tty_struct *tty)
+{
+ struct smd_tty_info *info = tty->driver_data;
+ smd_kick(info->ch);
+}
+
+static const struct tty_port_operations smd_tty_port_ops = {
+ .shutdown = smd_tty_port_shutdown,
+ .activate = smd_tty_port_activate,
+};
+
+static const struct tty_operations smd_tty_ops = {
+ .open = smd_tty_open,
+ .close = smd_tty_close,
+ .write = smd_tty_write,
+ .write_room = smd_tty_write_room,
+ .chars_in_buffer = smd_tty_chars_in_buffer,
+ .unthrottle = smd_tty_unthrottle,
+};
+
+static struct tty_driver *smd_tty_driver;
+
+static int __init smd_tty_init(void)
+{
+ int ret, i;
+
+ smd_tty_driver = alloc_tty_driver(MAX_SMD_TTYS);
+ if (smd_tty_driver == 0)
+ return -ENOMEM;
+
+ smd_tty_driver->owner = THIS_MODULE;
+ smd_tty_driver->driver_name = "smd_tty_driver";
+ smd_tty_driver->name = "smd";
+ smd_tty_driver->major = 0;
+ smd_tty_driver->minor_start = 0;
+ smd_tty_driver->type = TTY_DRIVER_TYPE_SERIAL;
+ smd_tty_driver->subtype = SERIAL_TYPE_NORMAL;
+ smd_tty_driver->init_termios = tty_std_termios;
+ smd_tty_driver->init_termios.c_iflag = 0;
+ smd_tty_driver->init_termios.c_oflag = 0;
+ smd_tty_driver->init_termios.c_cflag = B38400 | CS8 | CREAD;
+ smd_tty_driver->init_termios.c_lflag = 0;
+ smd_tty_driver->flags = TTY_DRIVER_RESET_TERMIOS |
+ TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+ tty_set_operations(smd_tty_driver, &smd_tty_ops);
+
+ ret = tty_register_driver(smd_tty_driver);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < smd_tty_channels_len; i++) {
+ tty_port_init(&smd_tty[smd_tty_channels[i].id].port);
+ smd_tty[smd_tty_channels[i].id].port.ops = &smd_tty_port_ops;
+ tty_register_device(smd_tty_driver, smd_tty_channels[i].id, 0);
+ }
+
+ return 0;
+}
+
+module_init(smd_tty_init);
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 5c7abe4c94dd..6a18ca6ddaa9 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -160,17 +160,17 @@ static int of_platform_serial_remove(struct platform_device *ofdev)
* A few common types, add more as needed.
*/
static struct of_device_id __devinitdata of_platform_serial_table[] = {
- { .type = "serial", .compatible = "ns8250", .data = (void *)PORT_8250, },
- { .type = "serial", .compatible = "ns16450", .data = (void *)PORT_16450, },
- { .type = "serial", .compatible = "ns16550a", .data = (void *)PORT_16550A, },
- { .type = "serial", .compatible = "ns16550", .data = (void *)PORT_16550, },
- { .type = "serial", .compatible = "ns16750", .data = (void *)PORT_16750, },
- { .type = "serial", .compatible = "ns16850", .data = (void *)PORT_16850, },
+ { .compatible = "ns8250", .data = (void *)PORT_8250, },
+ { .compatible = "ns16450", .data = (void *)PORT_16450, },
+ { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
+ { .compatible = "ns16550", .data = (void *)PORT_16550, },
+ { .compatible = "ns16750", .data = (void *)PORT_16750, },
+ { .compatible = "ns16850", .data = (void *)PORT_16850, },
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
- { .type = "serial", .compatible = "ibm,qpace-nwp-serial",
- .data = (void *)PORT_NWPSERIAL, },
+ { .compatible = "ibm,qpace-nwp-serial",
+ .data = (void *)PORT_NWPSERIAL, },
#endif
- { .type = "serial", .data = (void *)PORT_UNKNOWN, },
+ { .type = "serial", .data = (void *)PORT_UNKNOWN, },
{ /* end of list */ },
};
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 7f2f01058789..763537943a53 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -20,6 +20,10 @@
* this driver as required for the omap-platform.
*/
+#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
#include <linux/module.h>
#include <linux/init.h>
#include <linux/console.h>
@@ -190,7 +194,6 @@ static inline void receive_chars(struct uart_omap_port *up, int *status)
if (up->port.line == up->port.cons->index) {
/* Recover the break flag from console xmit */
lsr |= up->lsr_break_flag;
- up->lsr_break_flag = 0;
}
#endif
if (lsr & UART_LSR_BI)
@@ -517,6 +520,9 @@ static int serial_omap_startup(struct uart_port *port)
up->ier = UART_IER_RLSI | UART_IER_RDI;
serial_out(up, UART_IER, up->ier);
+ /* Enable module level wake up */
+ serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
+
up->port_activity = jiffies;
return 0;
}
@@ -824,9 +830,6 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
- /* Enable module level wake up */
- serial_out(up, UART_OMAP_WER,
- (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0);
}
static void serial_omap_release_port(struct uart_port *port)
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 70a61458ec42..a9ad7f33526d 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -21,6 +21,7 @@
#include <linux/serial_core.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/dmi.h>
#include <linux/dmaengine.h>
#include <linux/pch_dma.h>
@@ -40,10 +41,11 @@ enum {
#define PCH_UART_DRIVER_DEVICE "ttyPCH"
-#define PCH_UART_NR_GE_256FIFO 1
-#define PCH_UART_NR_GE_64FIFO 3
-#define PCH_UART_NR_GE (PCH_UART_NR_GE_256FIFO+PCH_UART_NR_GE_64FIFO)
-#define PCH_UART_NR PCH_UART_NR_GE
+/* Set the max number of UART port
+ * Intel EG20T PCH: 4 port
+ * OKI SEMICONDUCTOR ML7213 IOH: 3 port
+*/
+#define PCH_UART_NR 4
#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
@@ -192,6 +194,8 @@ enum {
#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
+#define PCI_VENDOR_ID_ROHM 0x10DB
+
struct pch_uart_buffer {
unsigned char *buf;
int size;
@@ -215,6 +219,7 @@ struct eg20t_port {
struct pch_uart_buffer rxbuf;
unsigned int dmsr;
unsigned int fcr;
+ unsigned int mcr;
unsigned int use_dma;
unsigned int use_dma_flag;
struct dma_async_tx_descriptor *desc_tx;
@@ -223,13 +228,44 @@ struct eg20t_port {
struct pch_dma_slave param_rx;
struct dma_chan *chan_tx;
struct dma_chan *chan_rx;
- struct scatterlist sg_tx;
+ struct scatterlist *sg_tx_p;
+ int nent;
struct scatterlist sg_rx;
int tx_dma_use;
void *rx_buf_virt;
dma_addr_t rx_buf_dma;
};
+/**
+ * struct pch_uart_driver_data - private data structure for UART-DMA
+ * @port_type: The number of DMA channel
+ * @line_no: UART port line number (0, 1, 2...)
+ */
+struct pch_uart_driver_data {
+ int port_type;
+ int line_no;
+};
+
+enum pch_uart_num_t {
+ pch_et20t_uart0 = 0,
+ pch_et20t_uart1,
+ pch_et20t_uart2,
+ pch_et20t_uart3,
+ pch_ml7213_uart0,
+ pch_ml7213_uart1,
+ pch_ml7213_uart2,
+};
+
+static struct pch_uart_driver_data drv_dat[] = {
+ [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
+ [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
+ [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
+ [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
+ [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
+ [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
+ [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
+};
+
static unsigned int default_baud = 9600;
static const int trigger_level_256[4] = { 1, 64, 128, 224 };
static const int trigger_level_64[4] = { 1, 16, 32, 56 };
@@ -278,7 +314,7 @@ static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
div = DIV_ROUND(priv->base_baud / 16, baud);
if (div < 0 || USHRT_MAX <= div) {
- pr_err("Invalid Baud(div=0x%x)\n", div);
+ dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
return -EINVAL;
}
@@ -286,17 +322,17 @@ static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
dlm = ((unsigned int)div >> 8) & 0x00FFU;
if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
- pr_err("Invalid parity(0x%x)\n", parity);
+ dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
return -EINVAL;
}
if (bits & ~PCH_UART_LCR_WLS) {
- pr_err("Invalid bits(0x%x)\n", bits);
+ dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
return -EINVAL;
}
if (stb & ~PCH_UART_LCR_STB) {
- pr_err("Invalid STB(0x%x)\n", stb);
+ dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
return -EINVAL;
}
@@ -304,7 +340,7 @@ static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
lcr |= bits;
lcr |= stb;
- pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
+ dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
__func__, baud, div, lcr, jiffies);
iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
iowrite8(dll, priv->membase + PCH_UART_DLL);
@@ -318,7 +354,8 @@ static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
unsigned int flag)
{
if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
- pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
+ dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
+ __func__, flag);
return -EINVAL;
}
@@ -337,17 +374,20 @@ static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
u8 fcr;
if (dmamode & ~PCH_UART_FCR_DMS) {
- pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
+ dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
+ __func__, dmamode);
return -EINVAL;
}
if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
- pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
+ dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
+ __func__, fifo_size);
return -EINVAL;
}
if (trigger & ~PCH_UART_FCR_RFTL) {
- pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
+ dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
+ __func__, trigger);
return -EINVAL;
}
@@ -386,7 +426,7 @@ static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
return get_msr(priv, priv->membase);
}
-static int pch_uart_hal_write(struct eg20t_port *priv,
+static void pch_uart_hal_write(struct eg20t_port *priv,
const unsigned char *buf, int tx_size)
{
int i;
@@ -396,7 +436,6 @@ static int pch_uart_hal_write(struct eg20t_port *priv,
thr = buf[i++];
iowrite8(thr, priv->membase + PCH_UART_THR);
}
- return i;
}
static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
@@ -452,7 +491,7 @@ static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
port = &priv->port;
tty = tty_port_tty_get(&port->state->port);
if (!tty) {
- pr_debug("%s:tty is busy now", __func__);
+ dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
return -EBUSY;
}
@@ -469,8 +508,8 @@ static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
struct uart_port *port = &priv->port;
if (port->x_char) {
- pr_debug("%s:X character send %02x (%lu)\n", __func__,
- port->x_char, jiffies);
+ dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
+ __func__, port->x_char, jiffies);
buf[0] = port->x_char;
port->x_char = 0;
ret = 1;
@@ -490,7 +529,7 @@ static int dma_push_rx(struct eg20t_port *priv, int size)
port = &priv->port;
tty = tty_port_tty_get(&port->state->port);
if (!tty) {
- pr_debug("%s:tty is busy now", __func__);
+ dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
return 0;
}
@@ -560,11 +599,13 @@ static void pch_request_dma(struct uart_port *port)
/* Set Tx DMA */
param = &priv->param_tx;
param->dma_dev = &dma_dev->dev;
- param->chan_id = priv->port.line;
+ param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
+
param->tx_reg = port->mapbase + UART_TX;
chan = dma_request_channel(mask, filter, param);
if (!chan) {
- pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
+ dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
+ __func__);
return;
}
priv->chan_tx = chan;
@@ -572,11 +613,13 @@ static void pch_request_dma(struct uart_port *port)
/* Set Rx DMA */
param = &priv->param_rx;
param->dma_dev = &dma_dev->dev;
- param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
+ param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
+
param->rx_reg = port->mapbase + UART_RX;
chan = dma_request_channel(mask, filter, param);
if (!chan) {
- pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
+ dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
+ __func__);
dma_release_channel(priv->chan_tx);
return;
}
@@ -592,16 +635,20 @@ static void pch_dma_rx_complete(void *arg)
struct eg20t_port *priv = arg;
struct uart_port *port = &priv->port;
struct tty_struct *tty = tty_port_tty_get(&port->state->port);
+ int count;
if (!tty) {
- pr_debug("%s:tty is busy now", __func__);
+ dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
return;
}
- if (dma_push_rx(priv, priv->trigger_level))
+ dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
+ count = dma_push_rx(priv, priv->trigger_level);
+ if (count)
tty_flip_buffer_push(tty);
-
tty_kref_put(tty);
+ async_tx_ack(priv->desc_rx);
+ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
}
static void pch_dma_tx_complete(void *arg)
@@ -609,16 +656,23 @@ static void pch_dma_tx_complete(void *arg)
struct eg20t_port *priv = arg;
struct uart_port *port = &priv->port;
struct circ_buf *xmit = &port->state->xmit;
+ struct scatterlist *sg = priv->sg_tx_p;
+ int i;
- xmit->tail += sg_dma_len(&priv->sg_tx);
+ for (i = 0; i < priv->nent; i++, sg++) {
+ xmit->tail += sg_dma_len(sg);
+ port->icount.tx += sg_dma_len(sg);
+ }
xmit->tail &= UART_XMIT_SIZE - 1;
- port->icount.tx += sg_dma_len(&priv->sg_tx);
-
async_tx_ack(priv->desc_tx);
+ dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
priv->tx_dma_use = 0;
+ priv->nent = 0;
+ kfree(priv->sg_tx_p);
+ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
}
-static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
+static int pop_tx(struct eg20t_port *priv, int size)
{
int count = 0;
struct uart_port *port = &priv->port;
@@ -631,13 +685,13 @@ static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
int cnt_to_end =
CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
int sz = min(size - count, cnt_to_end);
- memcpy(&buf[count], &xmit->buf[xmit->tail], sz);
+ pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
count += sz;
} while (!uart_circ_empty(xmit) && count < size);
pop_tx_end:
- pr_debug("%d characters. Remained %d characters. (%lu)\n",
+ dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
count, size - count, jiffies);
return count;
@@ -679,7 +733,7 @@ static int dma_handle_rx(struct eg20t_port *priv)
sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
- sg_dma_len(sg) = priv->fifo_size;
+ sg_dma_len(sg) = priv->trigger_level;
sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
@@ -689,7 +743,8 @@ static int dma_handle_rx(struct eg20t_port *priv)
desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
sg, 1, DMA_FROM_DEVICE,
- DMA_PREP_INTERRUPT);
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
if (!desc)
return 0;
@@ -706,14 +761,14 @@ static unsigned int handle_tx(struct eg20t_port *priv)
{
struct uart_port *port = &priv->port;
struct circ_buf *xmit = &port->state->xmit;
- int ret;
int fifo_size;
int tx_size;
int size;
int tx_empty;
if (!priv->start_tx) {
- pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
+ dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
+ __func__, jiffies);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
priv->tx_empty = 1;
return 0;
@@ -728,17 +783,21 @@ static unsigned int handle_tx(struct eg20t_port *priv)
fifo_size--;
}
size = min(xmit->head - xmit->tail, fifo_size);
- tx_size = pop_tx(priv, xmit->buf, size);
+ if (size < 0)
+ size = fifo_size;
+
+ tx_size = pop_tx(priv, size);
if (tx_size > 0) {
- ret = pch_uart_hal_write(priv, xmit->buf, tx_size);
- port->icount.tx += ret;
+ port->icount.tx += tx_size;
tx_empty = 0;
}
priv->tx_empty = tx_empty;
- if (tx_empty)
+ if (tx_empty) {
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ uart_write_wakeup(port);
+ }
return PCH_UART_HANDLED_TX_INT;
}
@@ -747,14 +806,28 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv)
{
struct uart_port *port = &priv->port;
struct circ_buf *xmit = &port->state->xmit;
- struct scatterlist *sg = &priv->sg_tx;
+ struct scatterlist *sg;
int nent;
int fifo_size;
int tx_empty;
struct dma_async_tx_descriptor *desc;
+ int num;
+ int i;
+ int bytes;
+ int size;
+ int rem;
if (!priv->start_tx) {
- pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
+ dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
+ __func__, jiffies);
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ priv->tx_empty = 1;
+ return 0;
+ }
+
+ if (priv->tx_dma_use) {
+ dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
+ __func__, jiffies);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
priv->tx_empty = 1;
return 0;
@@ -769,37 +842,73 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv)
fifo_size--;
}
- pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
+ UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
+ xmit->tail, UART_XMIT_SIZE));
+ if (!bytes) {
+ dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
+ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
+ uart_write_wakeup(port);
+ return 0;
+ }
+
+ if (bytes > fifo_size) {
+ num = bytes / fifo_size + 1;
+ size = fifo_size;
+ rem = bytes % fifo_size;
+ } else {
+ num = 1;
+ size = bytes;
+ rem = bytes;
+ }
+
+ dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
+ __func__, num, size, rem);
priv->tx_dma_use = 1;
- sg_init_table(&priv->sg_tx, 1); /* Initialize SG table */
+ priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
- sg_set_page(&priv->sg_tx, virt_to_page(xmit->buf),
- UART_XMIT_SIZE, (int)xmit->buf & ~PAGE_MASK);
+ sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
+ sg = priv->sg_tx_p;
- nent = dma_map_sg(port->dev, &priv->sg_tx, 1, DMA_TO_DEVICE);
+ for (i = 0; i < num; i++, sg++) {
+ if (i == (num - 1))
+ sg_set_page(sg, virt_to_page(xmit->buf),
+ rem, fifo_size * i);
+ else
+ sg_set_page(sg, virt_to_page(xmit->buf),
+ size, fifo_size * i);
+ }
+
+ sg = priv->sg_tx_p;
+ nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
if (!nent) {
- pr_err("%s:dma_map_sg Failed\n", __func__);
+ dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
return 0;
}
-
- sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
- sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
- sg->offset;
- sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail,
- UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
- xmit->tail, UART_XMIT_SIZE));
+ priv->nent = nent;
+
+ for (i = 0; i < nent; i++, sg++) {
+ sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
+ fifo_size * i;
+ sg_dma_address(sg) = (sg_dma_address(sg) &
+ ~(UART_XMIT_SIZE - 1)) + sg->offset;
+ if (i == (nent - 1))
+ sg_dma_len(sg) = rem;
+ else
+ sg_dma_len(sg) = size;
+ }
desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
- sg, nent, DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ priv->sg_tx_p, nent, DMA_TO_DEVICE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
- pr_err("%s:device_prep_slave_sg Failed\n", __func__);
+ dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
+ __func__);
return 0;
}
-
- dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
-
+ dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
priv->desc_tx = desc;
desc->callback = pch_dma_tx_complete;
desc->callback_param = priv;
@@ -854,10 +963,16 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
}
break;
case PCH_UART_IID_RDR: /* Received Data Ready */
- if (priv->use_dma)
+ if (priv->use_dma) {
+ pch_uart_hal_disable_interrupt(priv,
+ PCH_UART_HAL_RX_INT);
ret = dma_handle_rx(priv);
- else
+ if (!ret)
+ pch_uart_hal_enable_interrupt(priv,
+ PCH_UART_HAL_RX_INT);
+ } else {
ret = handle_rx(priv);
+ }
break;
case PCH_UART_IID_RDR_TO: /* Received Data Ready
(FIFO Timeout) */
@@ -874,7 +989,8 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
ret = PCH_UART_HANDLED_MS_INT;
break;
default: /* Never junp to this label */
- pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
+ dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
+ iid, jiffies);
ret = -1;
break;
}
@@ -932,7 +1048,6 @@ static unsigned int pch_uart_get_mctrl(struct uart_port *port)
static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
u32 mcr = 0;
- unsigned int dat;
struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
if (mctrl & TIOCM_DTR)
@@ -942,11 +1057,11 @@ static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
if (mctrl & TIOCM_LOOP)
mcr |= UART_MCR_LOOP;
- if (mctrl) {
- dat = pch_uart_get_mctrl(port);
- dat |= mcr;
- iowrite8(dat, priv->membase + UART_MCR);
- }
+ if (priv->mcr & UART_MCR_AFE)
+ mcr |= UART_MCR_AFE;
+
+ if (mctrl)
+ iowrite8(mcr, priv->membase + UART_MCR);
}
static void pch_uart_stop_tx(struct uart_port *port)
@@ -963,9 +1078,13 @@ static void pch_uart_start_tx(struct uart_port *port)
priv = container_of(port, struct eg20t_port, port);
- if (priv->use_dma)
- if (priv->tx_dma_use)
+ if (priv->use_dma) {
+ if (priv->tx_dma_use) {
+ dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
+ __func__);
return;
+ }
+ }
priv->start_tx = 1;
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
@@ -1010,7 +1129,12 @@ static int pch_uart_startup(struct uart_port *port)
priv = container_of(port, struct eg20t_port, port);
priv->tx_empty = 1;
- port->uartclk = priv->base_baud;
+
+ if (port->uartclk)
+ priv->base_baud = port->uartclk;
+ else
+ port->uartclk = priv->base_baud;
+
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
ret = pch_uart_hal_set_line(priv, default_baud,
PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
@@ -1081,7 +1205,8 @@ static void pch_uart_shutdown(struct uart_port *port)
ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
if (ret)
- pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
+ dev_err(priv->port.dev,
+ "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
if (priv->use_dma_flag)
pch_free_dma(port);
@@ -1130,6 +1255,13 @@ static void pch_uart_set_termios(struct uart_port *port,
} else {
parity = PCH_UART_HAL_PARITY_NONE;
}
+
+ /* Only UART0 has auto hardware flow function */
+ if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
+ priv->mcr |= UART_MCR_AFE;
+ else
+ priv->mcr &= ~UART_MCR_AFE;
+
termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
@@ -1202,17 +1334,19 @@ static int pch_uart_verify_port(struct uart_port *port,
priv = container_of(port, struct eg20t_port, port);
if (serinfo->flags & UPF_LOW_LATENCY) {
- pr_info("PCH UART : Use PIO Mode (without DMA)\n");
+ dev_info(priv->port.dev,
+ "PCH UART : Use PIO Mode (without DMA)\n");
priv->use_dma = 0;
serinfo->flags &= ~UPF_LOW_LATENCY;
} else {
#ifndef CONFIG_PCH_DMA
- pr_err("%s : PCH DMA is not Loaded.\n", __func__);
+ dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
+ __func__);
return -EOPNOTSUPP;
#endif
priv->use_dma = 1;
priv->use_dma_flag = 1;
- pr_info("PCH UART : Use DMA Mode\n");
+ dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
}
return 0;
@@ -1249,7 +1383,7 @@ static struct uart_driver pch_uart_driver = {
};
static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
- int port_type)
+ const struct pci_device_id *id)
{
struct eg20t_port *priv;
int ret;
@@ -1257,7 +1391,11 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
unsigned int mapbase;
unsigned char *rxbuf;
int fifosize, base_baud;
- static int num;
+ int port_type;
+ struct pch_uart_driver_data *board;
+
+ board = &drv_dat[id->driver_data];
+ port_type = board->port_type;
priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
if (priv == NULL)
@@ -1267,14 +1405,18 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
if (!rxbuf)
goto init_port_free_txbuf;
+ base_baud = 1843200; /* 1.8432MHz */
+
+ /* quirk for CM-iTC board */
+ if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
+ base_baud = 192000000; /* 192.0MHz */
+
switch (port_type) {
case PORT_UNKNOWN:
- fifosize = 256; /* UART0 */
- base_baud = 1843200; /* 1.8432MHz */
+ fifosize = 256; /* EG20T/ML7213: UART0 */
break;
case PORT_8250:
- fifosize = 64; /* UART1~3 */
- base_baud = 1843200; /* 1.8432MHz */
+ fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
break;
default:
dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
@@ -1302,11 +1444,14 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
priv->port.ops = &pch_uart_ops;
priv->port.flags = UPF_BOOT_AUTOCONF;
priv->port.fifosize = fifosize;
- priv->port.line = num++;
+ priv->port.line = board->line_no;
priv->trigger = PCH_UART_HAL_TRIGGER_M;
+ spin_lock_init(&priv->port.lock);
+
pci_set_drvdata(pdev, priv);
pch_uart_hal_request(pdev, fifosize, base_baud);
+
ret = uart_add_one_port(&pch_uart_driver, &priv->port);
if (ret < 0)
goto init_port_hal_free;
@@ -1377,13 +1522,19 @@ static int pch_uart_pci_resume(struct pci_dev *pdev)
static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
- .driver_data = PCH_UART_8LINE},
+ .driver_data = pch_et20t_uart0},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
- .driver_data = PCH_UART_2LINE},
+ .driver_data = pch_et20t_uart1},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
- .driver_data = PCH_UART_2LINE},
+ .driver_data = pch_et20t_uart2},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
- .driver_data = PCH_UART_2LINE},
+ .driver_data = pch_et20t_uart3},
+ {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
+ .driver_data = pch_ml7213_uart0},
+ {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
+ .driver_data = pch_ml7213_uart1},
+ {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
+ .driver_data = pch_ml7213_uart2},
{0,},
};
@@ -1397,7 +1548,7 @@ static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
if (ret < 0)
goto probe_error;
- priv = pch_uart_init_port(pdev, id->driver_data);
+ priv = pch_uart_init_port(pdev, id);
if (!priv) {
ret = -EBUSY;
goto probe_disable_device;
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 460a72d91bb7..733fe8e73f0f 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -905,7 +905,7 @@ static int uart_get_lsr_info(struct tty_struct *tty,
return put_user(result, value);
}
-static int uart_tiocmget(struct tty_struct *tty, struct file *file)
+static int uart_tiocmget(struct tty_struct *tty)
{
struct uart_state *state = tty->driver_data;
struct tty_port *port = &state->port;
@@ -913,10 +913,8 @@ static int uart_tiocmget(struct tty_struct *tty, struct file *file)
int result = -EIO;
mutex_lock(&port->mutex);
- if ((!file || !tty_hung_up_p(file)) &&
- !(tty->flags & (1 << TTY_IO_ERROR))) {
+ if (!(tty->flags & (1 << TTY_IO_ERROR))) {
result = uport->mctrl;
-
spin_lock_irq(&uport->lock);
result |= uport->ops->get_mctrl(uport);
spin_unlock_irq(&uport->lock);
@@ -927,8 +925,7 @@ static int uart_tiocmget(struct tty_struct *tty, struct file *file)
}
static int
-uart_tiocmset(struct tty_struct *tty, struct file *file,
- unsigned int set, unsigned int clear)
+uart_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
{
struct uart_state *state = tty->driver_data;
struct uart_port *uport = state->uart_port;
@@ -936,8 +933,7 @@ uart_tiocmset(struct tty_struct *tty, struct file *file,
int ret = -EIO;
mutex_lock(&port->mutex);
- if ((!file || !tty_hung_up_p(file)) &&
- !(tty->flags & (1 << TTY_IO_ERROR))) {
+ if (!(tty->flags & (1 << TTY_IO_ERROR))) {
uart_update_mctrl(uport, set, clear);
ret = 0;
}
@@ -1103,7 +1099,7 @@ static int uart_get_icount(struct tty_struct *tty,
* Called via sys_ioctl. We can use spin_lock_irq() here.
*/
static int
-uart_ioctl(struct tty_struct *tty, struct file *filp, unsigned int cmd,
+uart_ioctl(struct tty_struct *tty, unsigned int cmd,
unsigned long arg)
{
struct uart_state *state = tty->driver_data;
@@ -1156,7 +1152,7 @@ uart_ioctl(struct tty_struct *tty, struct file *filp, unsigned int cmd,
mutex_lock(&port->mutex);
- if (tty_hung_up_p(filp)) {
+ if (tty->flags & (1 << TTY_IO_ERROR)) {
ret = -EIO;
goto out_up;
}
@@ -2064,7 +2060,7 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
/*
* Re-enable the console device after suspending.
*/
- if (console_suspend_enabled && uart_console(uport)) {
+ if (uart_console(uport)) {
/*
* First try to use the console cflag setting.
*/
@@ -2077,9 +2073,9 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
if (port->tty && port->tty->termios && termios.c_cflag == 0)
termios = *(port->tty->termios);
- uart_change_pm(state, 0);
uport->ops->set_termios(uport, &termios, NULL);
- console_start(uport->cons);
+ if (console_suspend_enabled)
+ console_start(uport->cons);
}
if (port->flags & ASYNC_SUSPENDED) {
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-07 05:43:31 +0000