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path: root/drivers/usb/dwc3/core.h
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Diffstat (limited to 'drivers/usb/dwc3/core.h')
-rw-r--r--drivers/usb/dwc3/core.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 56e0b8e61011..fead52ed323c 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -138,6 +138,7 @@
#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
#define DWC3_GHWPARAMS8 0xc600
+#define DWC3_GUCTL3 0xc60c
#define DWC3_GFLADJ 0xc630
/* Device Registers */
@@ -398,6 +399,9 @@
/* Global User Control Register 2 */
#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
+/* Global User Control Register 3 */
+#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
+
/* Device Configuration Register */
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
@@ -719,7 +723,6 @@ struct dwc3_ep {
#define DWC3_EP_END_TRANSFER_PENDING BIT(4)
#define DWC3_EP_PENDING_REQUEST BIT(5)
#define DWC3_EP_DELAY_START BIT(6)
-#define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
#define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
/* This last one is specific to EP0 */
@@ -1076,6 +1079,7 @@ struct dwc3_platform_data {
* @dis_metastability_quirk: set to disable metastability quirk.
* @host_vbus_glitches: set to avoid vbus glitch during
* xhci reset.
+ * @dis_split_quirk: set to disable split boundary.
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
*/
@@ -1271,6 +1275,8 @@ struct dwc3 {
unsigned dis_metastability_quirk:1;
unsigned host_vbus_glitches:1;
+ unsigned dis_split_quirk:1;
+
u16 imod_interval;
};