diff options
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/Kconfig | 183 | ||||
| -rw-r--r-- | drivers/video/console/vgacon.c | 9 | ||||
| -rw-r--r-- | drivers/video/imxfb.c | 24 | ||||
| -rw-r--r-- | drivers/video/pm2fb.c | 17 | ||||
| -rw-r--r-- | drivers/video/pm3fb.c | 333 | ||||
| -rw-r--r-- | drivers/video/ps3fb.c | 8 | ||||
| -rw-r--r-- | drivers/video/w100fb.c | 14 |
7 files changed, 276 insertions, 312 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 4d7485fa553f..6e1f1ea21b38 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -704,6 +704,91 @@ config FB_CG6 This is the frame buffer device driver for the CGsix (GX, TurboGX) frame buffer. +config FB_FFB + bool "Creator/Creator3D/Elite3D support" + depends on FB_SBUS && SPARC64 + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Creator, Creator3D, + and Elite3D graphics boards. + +config FB_TCX + bool "TCX (SS4/SS5 only) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the TCX 24/8bit frame + buffer. + +config FB_CG14 + bool "CGfourteen (SX) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the CGfourteen frame + buffer on Desktop SPARCsystems with the SX graphics option. + +config FB_P9100 + bool "P9100 (Sparcbook 3 only) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the P9100 card + supported on Sparcbook 3 machines. + +config FB_LEO + bool "Leo (ZX) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the SBUS-based Sun ZX + (leo) frame buffer cards. + +config FB_IGA + bool "IGA 168x display support" + depends on FB && SPARC32 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the framebuffer device for the INTERGRAPHICS 1680 and + successor frame buffer cards. + +config FB_XVR500 + bool "Sun XVR-500 3DLABS Wildcat support" + depends on FB && PCI && SPARC64 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the framebuffer device for the Sun XVR-500 and similar + graphics cards based upon the 3DLABS Wildcat chipset. The driver + only works on sparc64 systems where the system firwmare has + mostly initialized the card already. It is treated as a + completely dumb framebuffer device. + +config FB_XVR2500 + bool "Sun XVR-2500 3DLABS Wildcat support" + depends on FB && PCI && SPARC64 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the framebuffer device for the Sun XVR-2500 and similar + graphics cards based upon the 3DLABS Wildcat chipset. The driver + only works on sparc64 systems where the system firwmare has + mostly initialized the card already. It is treated as a + completely dumb framebuffer device. + config FB_PVR2 tristate "NEC PowerVR 2 display support" depends on FB && SH_DREAMCAST @@ -1195,7 +1280,7 @@ config FB_ATY config FB_ATY_CT bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support" depends on PCI && FB_ATY - default y if SPARC64 && FB_PCI + default y if SPARC64 && PCI help Say Y here to support use of ATI's 64-bit Rage boards (or other boards based on the Mach64 CT, VT, GT, and LT chipsets) as a @@ -1484,95 +1569,6 @@ config FB_AU1200 source "drivers/video/geode/Kconfig" -config FB_FFB - bool "Creator/Creator3D/Elite3D support" - depends on FB_SBUS && SPARC64 - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the frame buffer device driver for the Creator, Creator3D, - and Elite3D graphics boards. - -config FB_TCX - bool "TCX (SS4/SS5 only) support" - depends on FB_SBUS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the frame buffer device driver for the TCX 24/8bit frame - buffer. - -config FB_CG14 - bool "CGfourteen (SX) support" - depends on FB_SBUS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the frame buffer device driver for the CGfourteen frame - buffer on Desktop SPARCsystems with the SX graphics option. - -config FB_P9100 - bool "P9100 (Sparcbook 3 only) support" - depends on FB_SBUS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the frame buffer device driver for the P9100 card - supported on Sparcbook 3 machines. - -config FB_LEO - bool "Leo (ZX) support" - depends on FB_SBUS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the frame buffer device driver for the SBUS-based Sun ZX - (leo) frame buffer cards. - -config FB_XVR500 - bool "Sun XVR-500 3DLABS Wildcat support" - depends on (FB = y) && PCI && SPARC64 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device for the Sun XVR-500 and similar - graphics cards based upon the 3DLABS Wildcat chipset. The driver - only works on sparc64 systems where the system firwmare has - mostly initialized the card already. It is treated as a - completely dumb framebuffer device. - -config FB_XVR2500 - bool "Sun XVR-2500 3DLABS Wildcat support" - depends on (FB = y) && PCI && SPARC64 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device for the Sun XVR-2500 and similar - graphics cards based upon the 3DLABS Wildcat chipset. The driver - only works on sparc64 systems where the system firwmare has - mostly initialized the card already. It is treated as a - completely dumb framebuffer device. - -config FB_PCI - bool "PCI framebuffers" - depends on (FB = y) && PCI && SPARC - -config FB_IGA - bool "IGA 168x display support" - depends on SPARC32 && FB_PCI - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device for the INTERGRAPHICS 1680 and - successor frame buffer cards. - config FB_HIT tristate "HD64461 Frame Buffer support" depends on FB && HD64461 @@ -1796,9 +1792,10 @@ config FB_IBM_GXT4500 config FB_PS3 bool "PS3 GPU framebuffer driver" depends on (FB = y) && PS3_PS3AV - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS ---help--- Include support for the virtual frame buffer in the PS3 platform. diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index 2460b82a1d93..f46fe95f69fb 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c @@ -368,9 +368,14 @@ static const char *vgacon_startup(void) #endif } + /* SCREEN_INFO initialized? */ + if ((ORIG_VIDEO_MODE == 0) && + (ORIG_VIDEO_LINES == 0) && + (ORIG_VIDEO_COLS == 0)) + goto no_vga; + /* VGA16 modes are not handled by VGACON */ - if ((ORIG_VIDEO_MODE == 0x00) || /* SCREEN_INFO not initialized */ - (ORIG_VIDEO_MODE == 0x0D) || /* 320x200/4 */ + if ((ORIG_VIDEO_MODE == 0x0D) || /* 320x200/4 */ (ORIG_VIDEO_MODE == 0x0E) || /* 640x200/4 */ (ORIG_VIDEO_MODE == 0x10) || /* 640x350/4 */ (ORIG_VIDEO_MODE == 0x12) || /* 640x480/4 */ diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index 267c1ff9ebd9..a12589898597 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c @@ -394,26 +394,18 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi) /* initialize GPIOs */ imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(PD10_PF_SPL_SPR); imx_gpio_mode(PD11_PF_CONTRAST); imx_gpio_mode(PD14_PF_FLM_VSYNC); imx_gpio_mode(PD13_PF_LP_HSYNC); - imx_gpio_mode(PD7_PF_REV); - imx_gpio_mode(PD8_PF_CLS); - -#ifndef CONFIG_MACH_PIMX1 - /* on PiMX1 used as buffers enable signal - */ - imx_gpio_mode(PD9_PF_PS); -#endif - -#ifndef CONFIG_MACH_MX1FS2 - /* on mx1fs2 this pin is used to (de)activate the display, so we need - * it as a normal gpio - */ imx_gpio_mode(PD12_PF_ACD_OE); -#endif + /* These are only needed for Sharp HR TFT displays */ + if (fbi->pcr & PCR_SHARP) { + imx_gpio_mode(PD7_PF_REV); + imx_gpio_mode(PD8_PF_CLS); + imx_gpio_mode(PD9_PF_PS); + imx_gpio_mode(PD10_PF_SPL_SPR); + } } #ifdef CONFIG_PM @@ -476,7 +468,6 @@ static int __init imxfb_init_fbinfo(struct device *dev) info->fbops = &imxfb_ops; info->flags = FBINFO_FLAG_DEFAULT; - info->pseudo_palette = (fbi + 1); fbi->rgb[RGB_16] = &def_rgb_16; fbi->rgb[RGB_8] = &def_rgb_8; @@ -499,6 +490,7 @@ static int __init imxfb_init_fbinfo(struct device *dev) info->var.sync = inf->sync; info->var.grayscale = inf->cmap_greyscale; fbi->cmap_inverse = inf->cmap_inverse; + fbi->cmap_static = inf->cmap_static; fbi->pcr = inf->pcr; fbi->lscr1 = inf->lscr1; fbi->dmacr = inf->dmacr; diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c index ab5e66890e4e..0a04483aa3e0 100644 --- a/drivers/video/pm2fb.c +++ b/drivers/video/pm2fb.c @@ -183,15 +183,17 @@ static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) index = PM2VR_RD_INDEXED_DATA; break; } - mb(); + wmb(); pm2_WR(p, index, v); + wmb(); } static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v) { pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); - mb(); + wmb(); pm2_WR(p, PM2VR_RD_INDEXED_DATA, v); + wmb(); } #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT @@ -466,11 +468,9 @@ static void set_memclock(struct pm2fb_par* par, u32 clk) WAIT_FIFO(par, 8); pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); - wmb(); pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); - wmb(); pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); rmb(); for (i = 256; @@ -483,12 +483,9 @@ static void set_memclock(struct pm2fb_par* par, u32 clk) pm2_mnp(clk, &m, &n, &p); WAIT_FIFO(par, 10); pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); - wmb(); pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); - wmb(); pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); - wmb(); pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); rmb(); for (i = 256; @@ -509,12 +506,9 @@ static void set_pixclock(struct pm2fb_par* par, u32 clk) pm2_mnp(clk, &m, &n, &p); WAIT_FIFO(par, 8); pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0); - wmb(); pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m); pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n); - wmb(); pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p); - wmb(); pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS); rmb(); for (i = 256; @@ -1066,10 +1060,9 @@ static void pm2fb_block_op(struct fb_info* info, int copy, if (!w || !h) return; - WAIT_FIFO(par, 6); + WAIT_FIFO(par, 5); pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | PM2F_CONFIG_FB_READ_SOURCE_ENABLE); - pm2_WR(par, PM2R_FB_PIXEL_OFFSET, 0); if (copy) pm2_WR(par, PM2R_FB_SOURCE_DELTA, ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff)); diff --git a/drivers/video/pm3fb.c b/drivers/video/pm3fb.c index c77a1a1fd46b..616a0c08e30c 100644 --- a/drivers/video/pm3fb.c +++ b/drivers/video/pm3fb.c @@ -52,11 +52,6 @@ static char *mode_option __devinitdata; /* - * If your driver supports multiple boards, you should make the - * below data types arrays, or allocate them dynamically (using kmalloc()). - */ - -/* * This structure defines the hardware state of the graphics card. Normally * you place this in a header file in linux/include/video. This file usually * also includes register information. That allows other driver subsystems @@ -67,7 +62,7 @@ struct pm3_par { unsigned char __iomem *v_regs;/* virtual address of p_regs */ u32 video; /* video flags before blanking */ u32 base; /* screen base (xoffset+yoffset) in 128 bits unit */ - u32 palette[16]; + u32 palette[16]; }; /* @@ -104,36 +99,28 @@ static inline void PM3_WAIT(struct pm3_par *par, u32 n) while (PM3_READ_REG(par, PM3InFIFOSpace) < n); } -static inline void PM3_SLOW_WRITE_REG(struct pm3_par *par, s32 off, u32 v) -{ - if (par->v_regs) { - mb(); - PM3_WAIT(par, 1); - wmb(); - PM3_WRITE_REG(par, off, v); - } -} - -static inline void PM3_SET_INDEX(struct pm3_par *par, unsigned index) -{ - PM3_SLOW_WRITE_REG(par, PM3RD_IndexHigh, (index >> 8) & 0xff); - PM3_SLOW_WRITE_REG(par, PM3RD_IndexLow, index & 0xff); -} - static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v) { - PM3_SET_INDEX(par, r); + PM3_WAIT(par, 3); + PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff); + PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff); wmb(); PM3_WRITE_REG(par, PM3RD_IndexedData, v); + wmb(); } static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno, unsigned char r, unsigned char g, unsigned char b) { - PM3_SLOW_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno); - PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, r); - PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, g); - PM3_SLOW_WRITE_REG(par, PM3RD_PaletteData, b); + PM3_WAIT(par, 4); + PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno); + wmb(); + PM3_WRITE_REG(par, PM3RD_PaletteData, r); + wmb(); + PM3_WRITE_REG(par, PM3RD_PaletteData, g); + wmb(); + PM3_WRITE_REG(par, PM3RD_PaletteData, b); + wmb(); } static void pm3fb_clear_colormap(struct pm3_par *par, @@ -141,7 +128,7 @@ static void pm3fb_clear_colormap(struct pm3_par *par, { int i; - for (i = 0; i < 256 ; i++) /* fill color map with white */ + for (i = 0; i < 256 ; i++) pm3fb_set_color(par, i, r, g, b); } @@ -175,19 +162,26 @@ static void pm3fb_calculate_clock(unsigned long reqclock, } } -static inline int pm3fb_shift_bpp(unsigned long depth, int v) +static inline int pm3fb_depth(const struct fb_var_screeninfo *var) { - switch (depth) { + if ( var->bits_per_pixel == 16 ) + return var->red.length + var->green.length + + var->blue.length; + + return var->bits_per_pixel; +} + +static inline int pm3fb_shift_bpp(unsigned bpp, int v) +{ + switch (bpp) { case 8: return (v >> 4); - case 12: - case 15: case 16: return (v >> 3); case 32: return (v >> 2); } - DPRINTK("Unsupported depth %ld\n", depth); + DPRINTK("Unsupported depth %u\n", bpp); return 0; } @@ -206,56 +200,50 @@ static void pm3fb_write_mode(struct fb_info *info) const u32 vbend = vsend + info->var.upper_margin; const u32 vtotal = info->var.yres + vbend; const u32 width = (info->var.xres_virtual + 7) & ~7; - - PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff); - PM3_SLOW_WRITE_REG(par, PM3Aperture0, 0x00000000); - PM3_SLOW_WRITE_REG(par, PM3Aperture1, 0x00000000); - PM3_SLOW_WRITE_REG(par, PM3FIFODis, 0x00000007); - - PM3_SLOW_WRITE_REG(par, PM3HTotal, - pm3fb_shift_bpp(info->var.bits_per_pixel, - htotal - 1)); - PM3_SLOW_WRITE_REG(par, PM3HsEnd, - pm3fb_shift_bpp(info->var.bits_per_pixel, - hsend)); - PM3_SLOW_WRITE_REG(par, PM3HsStart, - pm3fb_shift_bpp(info->var.bits_per_pixel, - hsstart)); - PM3_SLOW_WRITE_REG(par, PM3HbEnd, - pm3fb_shift_bpp(info->var.bits_per_pixel, - hbend)); - PM3_SLOW_WRITE_REG(par, PM3HgEnd, - pm3fb_shift_bpp(info->var.bits_per_pixel, - hbend)); - PM3_SLOW_WRITE_REG(par, PM3ScreenStride, - pm3fb_shift_bpp(info->var.bits_per_pixel, - width)); - PM3_SLOW_WRITE_REG(par, PM3VTotal, vtotal - 1); - PM3_SLOW_WRITE_REG(par, PM3VsEnd, vsend - 1); - PM3_SLOW_WRITE_REG(par, PM3VsStart, vsstart - 1); - PM3_SLOW_WRITE_REG(par, PM3VbEnd, vbend); - - switch (info->var.bits_per_pixel) { + const unsigned bpp = info->var.bits_per_pixel; + + PM3_WAIT(par, 20); + PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff); + PM3_WRITE_REG(par, PM3Aperture0, 0x00000000); + PM3_WRITE_REG(par, PM3Aperture1, 0x00000000); + PM3_WRITE_REG(par, PM3FIFODis, 0x00000007); + + PM3_WRITE_REG(par, PM3HTotal, + pm3fb_shift_bpp(bpp, htotal - 1)); + PM3_WRITE_REG(par, PM3HsEnd, + pm3fb_shift_bpp(bpp, hsend)); + PM3_WRITE_REG(par, PM3HsStart, + pm3fb_shift_bpp(bpp, hsstart)); + PM3_WRITE_REG(par, PM3HbEnd, + pm3fb_shift_bpp(bpp, hbend)); + PM3_WRITE_REG(par, PM3HgEnd, + pm3fb_shift_bpp(bpp, hbend)); + PM3_WRITE_REG(par, PM3ScreenStride, + pm3fb_shift_bpp(bpp, width)); + PM3_WRITE_REG(par, PM3VTotal, vtotal - 1); + PM3_WRITE_REG(par, PM3VsEnd, vsend - 1); + PM3_WRITE_REG(par, PM3VsStart, vsstart - 1); + PM3_WRITE_REG(par, PM3VbEnd, vbend); + + switch (bpp) { case 8: - PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode, + PM3_WRITE_REG(par, PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_8BIT); - PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode, + PM3_WRITE_REG(par, PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_8BIT); break; - case 12: - case 15: case 16: #ifndef __BIG_ENDIAN - PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode, + PM3_WRITE_REG(par, PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_16BIT); - PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode, + PM3_WRITE_REG(par, PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_16BIT); #else - PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode, + PM3_WRITE_REG(par, PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_16BIT | PM3ByApertureMode_BYTESWAP_BADC); - PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode, + PM3_WRITE_REG(par, PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_16BIT | PM3ByApertureMode_BYTESWAP_BADC); #endif /* ! __BIG_ENDIAN */ @@ -263,23 +251,22 @@ static void pm3fb_write_mode(struct fb_info *info) case 32: #ifndef __BIG_ENDIAN - PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode, + PM3_WRITE_REG(par, PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_32BIT); - PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode, + PM3_WRITE_REG(par, PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_32BIT); #else - PM3_SLOW_WRITE_REG(par, PM3ByAperture1Mode, + PM3_WRITE_REG(par, PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_32BIT | PM3ByApertureMode_BYTESWAP_DCBA); - PM3_SLOW_WRITE_REG(par, PM3ByAperture2Mode, + PM3_WRITE_REG(par, PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_32BIT | PM3ByApertureMode_BYTESWAP_DCBA); #endif /* ! __BIG_ENDIAN */ break; default: - DPRINTK("Unsupported depth %d\n", - info->var.bits_per_pixel); + DPRINTK("Unsupported depth %d\n", bpp); break; } @@ -296,14 +283,15 @@ static void pm3fb_write_mode(struct fb_info *info) PM3VideoControl_VSYNC_MASK); video |= PM3VideoControl_HSYNC_ACTIVE_HIGH | PM3VideoControl_VSYNC_ACTIVE_HIGH; - PM3_SLOW_WRITE_REG(par, PM3VideoControl, video); + PM3_WRITE_REG(par, PM3VideoControl, video); } - PM3_SLOW_WRITE_REG(par, PM3VClkCtl, + PM3_WRITE_REG(par, PM3VClkCtl, (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC)); - PM3_SLOW_WRITE_REG(par, PM3ScreenBase, par->base); - PM3_SLOW_WRITE_REG(par, PM3ChipConfig, + PM3_WRITE_REG(par, PM3ScreenBase, par->base); + PM3_WRITE_REG(par, PM3ChipConfig, (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD)); + wmb(); { unsigned char uninitialized_var(m); /* ClkPreScale */ unsigned char uninitialized_var(n); /* ClkFeedBackScale */ @@ -337,7 +325,7 @@ static void pm3fb_write_mode(struct fb_info *info) PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00); - switch (info->var.bits_per_pixel) { + switch (pm3fb_depth(&info->var)) { case 8: PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, PM3RD_PixelSize_8_BIT_PIXELS); @@ -393,57 +381,44 @@ static void pm3fb_write_mode(struct fb_info *info) * hardware independent functions */ int pm3fb_init(void); -int pm3fb_setup(char*); static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { u32 lpitch; + unsigned bpp = var->red.length + var->green.length + + var->blue.length + var->transp.length; - var->transp.offset = 0; - var->transp.length = 0; - switch(var->bits_per_pixel) { - case 8: - var->red.length = var->green.length = var->blue.length = 8; - var->red.offset = var->green.offset = var->blue.offset = 0; - break; - case 12: - var->red.offset = 8; - var->red.length = 4; - var->green.offset = 4; - var->green.length = 4; - var->blue.offset = 0; - var->blue.length = 4; - var->transp.offset = 12; - var->transp.length = 4; - case 15: - var->red.offset = 10; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 5; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 15; - var->transp.length = 1; - break; - case 16: - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - break; - case 32: - var->transp.offset = 24; - var->transp.length = 8; - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = var->green.length = var->blue.length = 8; - break; - default: - DPRINTK("depth not supported: %u\n", var->bits_per_pixel); - return -EINVAL; + if ( bpp != var->bits_per_pixel ) { + /* set predefined mode for bits_per_pixel settings */ + + switch(var->bits_per_pixel) { + case 8: + var->red.length = var->green.length = var->blue.length = 8; + var->red.offset = var->green.offset = var->blue.offset = 0; + var->transp.offset = 0; + var->transp.length = 0; + break; + case 16: + var->red.length = var->blue.length = 5; + var->green.length = 6; + var->transp.length = 0; + break; + case 32: + var->red.length = var->green.length = var->blue.length = 8; + var->transp.length = 8; + break; + default: + DPRINTK("depth not supported: %u\n", var->bits_per_pixel); + return -EINVAL; + } + } + /* it is assumed BGRA order */ + if (var->bits_per_pixel > 8 ) + { + var->blue.offset = 0; + var->green.offset = var->blue.length; + var->red.offset = var->green.offset + var->green.length; + var->transp.offset = var->red.offset + var->red.length; } var->height = var->width = -1; @@ -502,10 +477,9 @@ static int pm3fb_set_par(struct fb_info *info) { struct pm3_par *par = info->par; const u32 xres = (info->var.xres + 31) & ~31; - const int depth = (info->var.bits_per_pixel + 7) & ~7; + const unsigned bpp = info->var.bits_per_pixel; - par->base = pm3fb_shift_bpp(info->var.bits_per_pixel, - (info->var.yoffset * xres) + par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres) + info->var.xoffset); par->video = 0; @@ -530,12 +504,10 @@ static int pm3fb_set_par(struct fb_info *info) par->video |= PM3VideoControl_DISABLE; DPRINTK("PM3Video disabled\n"); } - switch (depth) { + switch (bpp) { case 8: par->video |= PM3VideoControl_PIXELSIZE_8BIT; break; - case 12: - case 15: case 16: par->video |= PM3VideoControl_PIXELSIZE_16BIT; break; @@ -548,9 +520,9 @@ static int pm3fb_set_par(struct fb_info *info) } info->fix.visual = - (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; + (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; info->fix.line_length = ((info->var.xres_virtual + 7) & ~7) - * depth / 8; + * bpp / 8; /* pm3fb_clear_memory(info, 0);*/ pm3fb_clear_colormap(par, 0, 0, 0); @@ -580,8 +552,8 @@ static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green, * var->{color}.length contains length of bitfield * {hardwarespecific} contains width of DAC * pseudo_palette[X] is programmed to (X << red.offset) | - * (X << green.offset) | - * (X << blue.offset) + * (X << green.offset) | + * (X << blue.offset) * RAMDAC[X] is programmed to (red, green, blue) * color depth = SUM(var->{color}.length) * @@ -621,7 +593,6 @@ static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green, case 8: break; case 16: - case 24: case 32: ((u32*)(info->pseudo_palette))[regno] = v; break; @@ -643,7 +614,8 @@ static int pm3fb_pan_display(struct fb_var_screeninfo *var, par->base = pm3fb_shift_bpp(var->bits_per_pixel, (var->yoffset * xres) + var->xoffset); - PM3_SLOW_WRITE_REG(par, PM3ScreenBase, par->base); + PM3_WAIT(par, 1); + PM3_WRITE_REG(par, PM3ScreenBase, par->base); return 0; } @@ -665,31 +637,31 @@ static int pm3fb_blank(int blank_mode, struct fb_info *info) switch (blank_mode) { case FB_BLANK_UNBLANK: - video = video | PM3VideoControl_ENABLE; + video |= PM3VideoControl_ENABLE; break; - case FB_BLANK_NORMAL: /* FIXME */ - video = video & ~(PM3VideoControl_ENABLE); + case FB_BLANK_NORMAL: + video &= ~(PM3VideoControl_ENABLE); break; case FB_BLANK_HSYNC_SUSPEND: - video = video & ~(PM3VideoControl_HSYNC_MASK | - PM3VideoControl_BLANK_ACTIVE_LOW); + video &= ~(PM3VideoControl_HSYNC_MASK | + PM3VideoControl_BLANK_ACTIVE_LOW); break; case FB_BLANK_VSYNC_SUSPEND: - video = video & ~(PM3VideoControl_VSYNC_MASK | - PM3VideoControl_BLANK_ACTIVE_LOW); + video &= ~(PM3VideoControl_VSYNC_MASK | + PM3VideoControl_BLANK_ACTIVE_LOW); break; case FB_BLANK_POWERDOWN: - video = video & ~(PM3VideoControl_HSYNC_MASK | - PM3VideoControl_VSYNC_MASK | - PM3VideoControl_BLANK_ACTIVE_LOW); + video &= ~(PM3VideoControl_HSYNC_MASK | + PM3VideoControl_VSYNC_MASK | + PM3VideoControl_BLANK_ACTIVE_LOW); break; default: DPRINTK("Unsupported blanking %d\n", blank_mode); return 1; } - PM3_SLOW_WRITE_REG(par,PM3VideoControl, video); - + PM3_WAIT(par, 1); + PM3_WRITE_REG(par,PM3VideoControl, video); return 0; } @@ -703,9 +675,9 @@ static struct fb_ops pm3fb_ops = { .fb_set_par = pm3fb_set_par, .fb_setcolreg = pm3fb_setcolreg, .fb_pan_display = pm3fb_pan_display, - .fb_fillrect = cfb_fillrect, /* Needed !!! */ - .fb_copyarea = cfb_copyarea, /* Needed !!! */ - .fb_imageblit = cfb_imageblit, /* Needed !!! */ + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, .fb_blank = pm3fb_blank, }; @@ -722,7 +694,7 @@ static unsigned long pm3fb_size_memory(struct pm3_par *par) unsigned long memsize = 0, tempBypass, i, temp1, temp2; unsigned char __iomem *screen_mem; - pm3fb_fix.smem_len = 64 * 1024 * 1024; /* request full aperture size */ + pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */ /* Linear frame buffer - request region and map it. */ if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len, "pm3fb smem")) { @@ -744,7 +716,8 @@ static unsigned long pm3fb_size_memory(struct pm3_par *par) DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass); - PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF); + PM3_WAIT(par, 1); + PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF); /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */ for (i = 0; i < 32; i++) { @@ -765,10 +738,9 @@ static unsigned long pm3fb_size_memory(struct pm3_par *par) if (memsize + 1 == i) { for (i = 0; i < 32; i++) { /* Clear first 32MB ; 0 is 0, no need to byteswap */ - writel(0x0000000, - (screen_mem + (i * 1048576))); - mb(); + writel(0x0000000, (screen_mem + (i * 1048576))); } + wmb(); for (i = 32; i < 64; i++) { fb_writel(i * 0x00345678, @@ -787,7 +759,8 @@ static unsigned long pm3fb_size_memory(struct pm3_par *par) } DPRINTK("Second detect pass got %ld MB\n", memsize + 1); - PM3_SLOW_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass); + PM3_WAIT(par, 1); + PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass); iounmap(screen_mem); release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); @@ -890,7 +863,6 @@ static int __devinit pm3fb_probe(struct pci_dev *dev, goto err_exit_both; } - /* This has to been done !!! */ if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { retval = -ENOMEM; goto err_exit_both; @@ -907,7 +879,7 @@ static int __devinit pm3fb_probe(struct pci_dev *dev, } printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); - pci_set_drvdata(dev, info); /* or dev_set_drvdata(device, info) */ + pci_set_drvdata(dev, info); return 0; err_exit_all: @@ -949,8 +921,7 @@ static void __devexit pm3fb_remove(struct pci_dev *dev) static struct pci_device_id pm3fb_id_table[] = { { PCI_VENDOR_ID_3DLABS, 0x0a, - PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, - 0xff0000, 0 }, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { 0, } }; @@ -964,6 +935,22 @@ static struct pci_driver pm3fb_driver = { MODULE_DEVICE_TABLE(pci, pm3fb_id_table); +#ifndef MODULE + /* + * Setup + */ + +/* + * Only necessary if your driver takes special options, + * otherwise we fall back on the generic fb_setup(). + */ +static int __init pm3fb_setup(char *options) +{ + /* Parse user speficied options (`video=pm3fb:') */ + return 0; +} +#endif /* MODULE */ + int __init pm3fb_init(void) { /* @@ -985,22 +972,6 @@ static void __exit pm3fb_exit(void) pci_unregister_driver(&pm3fb_driver); } -#ifndef MODULE - /* - * Setup - */ - -/* - * Only necessary if your driver takes special options, - * otherwise we fall back on the generic fb_setup(). - */ -int __init pm3fb_setup(char *options) -{ - /* Parse user speficied options (`video=pm3fb:') */ - return 0; -} -#endif /* MODULE */ - module_init(pm3fb_init); module_exit(pm3fb_exit); diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c index 9756a728b74f..9cf92ba5d6e3 100644 --- a/drivers/video/ps3fb.c +++ b/drivers/video/ps3fb.c @@ -951,12 +951,14 @@ static int ps3fb_xdr_settings(u64 xdr_lpar) static struct fb_ops ps3fb_ops = { .fb_open = ps3fb_open, .fb_release = ps3fb_release, + .fb_read = fb_sys_read, + .fb_write = fb_sys_write, .fb_check_var = ps3fb_check_var, .fb_set_par = ps3fb_set_par, .fb_setcolreg = ps3fb_setcolreg, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, + .fb_fillrect = sys_fillrect, + .fb_copyarea = sys_copyarea, + .fb_imageblit = sys_imageblit, .fb_mmap = ps3fb_mmap, .fb_blank = ps3fb_blank, .fb_ioctl = ps3fb_ioctl, diff --git a/drivers/video/w100fb.c b/drivers/video/w100fb.c index 5fc86ea20692..003c49a490eb 100644 --- a/drivers/video/w100fb.c +++ b/drivers/video/w100fb.c @@ -660,7 +660,7 @@ int __init w100fb_probe(struct platform_device *pdev) err = -ENODEV; goto out; } - printk(" at 0x%08lx.\n", mem->start+W100_CFG_BASE); + printk(" at 0x%08lx.\n", (unsigned long) mem->start+W100_CFG_BASE); /* Remap the framebuffer */ remapped_fbuf = ioremap_nocache(mem->start+MEM_WINDOW_BASE, MEM_WINDOW_SIZE); @@ -753,10 +753,14 @@ int __init w100fb_probe(struct platform_device *pdev) goto out; } - device_create_file(&pdev->dev, &dev_attr_fastpllclk); - device_create_file(&pdev->dev, &dev_attr_reg_read); - device_create_file(&pdev->dev, &dev_attr_reg_write); - device_create_file(&pdev->dev, &dev_attr_flip); + err = device_create_file(&pdev->dev, &dev_attr_fastpllclk); + err |= device_create_file(&pdev->dev, &dev_attr_reg_read); + err |= device_create_file(&pdev->dev, &dev_attr_reg_write); + err |= device_create_file(&pdev->dev, &dev_attr_flip); + + if (err != 0) + printk(KERN_WARNING "fb%d: failed to register attributes (%d)\n", + info->node, err); printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); return 0; |