3 files changed, 31 insertions, 9 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index b770d83fac05..9fd64003ef3f 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dsi.c
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -2094,7 +2094,7 @@ tegra_dsi_mipi_calibration_status(struct tegra_dc_dsi_data *dsi)
 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
 static void tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
 {
-	u32 val;
+	u32 val, reg;
 	struct clk *clk72mhz = NULL;
 
 	clk72mhz = clk_get_sys("clk72mhz", NULL);
@@ -2129,6 +2129,15 @@ static void tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
 		   DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
 	tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
 
+	/* Deselect shared clk lane with DSI pads */
+	for (reg = MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0;
+		reg <= MIPI_CAL_CSIE_MIPI_CAL_CONFIG_2_0;
+		reg += 4) {
+		val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
+		val &= ~(MIPI_CAL_SELA(0x1));
+		tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
+	}
+
 	/* Calibrate DSI 0 */
 	if (dsi->info.ganged_type ||
 		dsi->info.dsi_instance == DSI_INSTANCE_0) {
@@ -2371,6 +2380,8 @@ static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
 #endif
 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
 {
+	u32 val = 0, reg;
+
 	if (!dsi->ulpm)
 		tegra_dsi_pad_enable(dsi);
 	else
@@ -2382,6 +2393,15 @@ static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
 
 		tegra_mipi_cal_clk_enable(dsi->mipi_cal);
 
+		/* Deselect CSI pads */
+		for (reg = MIPI_CAL_CILA_MIPI_CAL_CONFIG_0;
+			reg <= MIPI_CAL_CILF_MIPI_CAL_CONFIG_0;
+			reg += 4) {
+			val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
+			val &= ~(MIPI_CAL_SELA(0x1));
+			tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
+		}
+
 		tegra_mipi_cal_write(dsi->mipi_cal,
 			MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
 			MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
diff --git a/drivers/video/tegra/dc/mipi_cal.c b/drivers/video/tegra/dc/mipi_cal.c
index e3989acdcc9f..8592a954cab9 100644
--- a/drivers/video/tegra/dc/mipi_cal.c
+++ b/drivers/video/tegra/dc/mipi_cal.c
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/mipi_cal.c
  *
- * Copyright (c) 2012-2013, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2012-2015, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -98,17 +98,12 @@ static inline void dbg_dsi_mipi_dir_create(struct tegra_mipi_cal *mipi_cal)
 
 int tegra_mipi_cal_init_hw(struct tegra_mipi_cal *mipi_cal)
 {
-	unsigned cnt = MIPI_CAL_MIPI_CAL_CTRL_0;
-
 	BUG_ON(IS_ERR_OR_NULL(mipi_cal));
 
 	mutex_lock(&mipi_cal->lock);
 
 	tegra_mipi_cal_clk_enable(mipi_cal);
 
-	for (; cnt <= MIPI_VALID_REG_LIMIT; cnt += 4)
-		tegra_mipi_cal_write(mipi_cal, 0, cnt);
-
 	/* Clear MIPI cal status register */
 	tegra_mipi_cal_write(mipi_cal,
 			MIPI_AUTO_CAL_DONE_DSID(0x1) |
diff --git a/drivers/video/tegra/dc/mipi_cal_regs.h b/drivers/video/tegra/dc/mipi_cal_regs.h
index d5b969900af4..0efd5e59a40a 100644
--- a/drivers/video/tegra/dc/mipi_cal_regs.h
+++ b/drivers/video/tegra/dc/mipi_cal_regs.h
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/mipi_cal_regs.h
  *
- * Copyright (c) 2012-2013, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2012-2015, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -69,6 +69,13 @@
 #define MIPI_CAL_HSPUOSE(x)		(((x) & 0x1f) << 8)
 #define MIPI_CAL_TERMOSE(x)		(((x) & 0x1f) << 0)
 
+#define MIPI_CAL_CILF_MIPI_CAL_CONFIG_0	0x28
+#define MIPI_CAL_OVERIDEF(x)		(((x) & 0x1) << 30)
+#define MIPI_CAL_SELF(x)		(((x) & 0x1) << 21)
+#define MIPI_CAL_HSPDOSF(x)		(((x) & 0x1f) << 16)
+#define MIPI_CAL_HSPUOSF(x)		(((x) & 0x1f) << 8)
+#define MIPI_CAL_TERMOSF(x)		(((x) & 0x1f) << 0)
+
 #define MIPI_CAL_MIPI_BIAS_PAD_CFG0_0	0x58
 #define MIPI_BIAS_PAD_PDVCLAMP(x)	(((x) & 0x1) << 1)
 #define MIPI_BIAS_PAD_E_VCLAMP_REF(x)	(((x) & 0x1) << 0)