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-rw-r--r--drivers/video/mxc/ad9389.c815
-rw-r--r--drivers/video/mxc/elcdif_regs.h678
-rw-r--r--drivers/video/mxc/epdc_regs.h301
-rw-r--r--drivers/video/mxc/ldb.c1448
-rw-r--r--drivers/video/mxc/mxc_elcdif_fb.c1445
-rw-r--r--drivers/video/mxc/mxc_epdc_fb.c3187
-rw-r--r--drivers/video/mxc/mxcfb_sii9022.c252
-rw-r--r--drivers/video/mxs/regs-tvenc.h583
-rw-r--r--drivers/video/mxs/tvenc.c279
9 files changed, 8988 insertions, 0 deletions
diff --git a/drivers/video/mxc/ad9389.c b/drivers/video/mxc/ad9389.c
new file mode 100644
index 000000000000..9765cfd1a17f
--- /dev/null
+++ b/drivers/video/mxc/ad9389.c
@@ -0,0 +1,815 @@
+/*
+ * ad9389.c
+ *
+ * Copyright 2010 - Digi International, Inc. All Rights Reserved.
+ *
+ * Based on ad9889.c driver from Armadeus:
+ * Copyright (C) 2009 Armadeus Systems <nicolas.colombain@armadeus.com>
+ * And also on mxcfb_sii9022.c from Pegatron:
+ * Copyright 2009 Pegatron Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/proc_fs.h>
+#include <linux/fb.h>
+#include <linux/console.h>
+#include <video/ad9389.h>
+
+#define HPD_INT 0x80
+#define MSEN_INT 0x40
+#define VS_INT 0x20
+#define AUDIO_FIFO_FULL_INT 0x10
+#define ITU656_ERR_INT 0x08
+#define EDID_RDY_INT 0x04
+#define EDID_LENGTH 256
+#define DRV_NAME "ad9389"
+
+
+#define DEBUG
+#define I2C_DBG 0x0001
+#define EDID_DBG 0x0002
+#define REGS_DBG 0x0004
+#define SCREEN_DBG 0x0008
+
+//int debug = I2C_DBG | EDID_DBG | REGS_DBG | SCREEN_DBG;
+int debug = 0;
+#define DBG(flag, fmt, args...) do { \
+ if (debug & flag) \
+ printk(KERN_DEBUG fmt, ## args); \
+ } while (0)
+
+struct ad9389_dev *pad9389;
+
+
+static inline int ad9389_read_reg(struct i2c_client *client, u8 reg)
+{
+ return i2c_smbus_read_byte_data(client, reg);
+}
+
+static inline int ad9389_write_reg(struct i2c_client *client, u8 reg, u8 val)
+{
+ DBG(I2C_DBG, "I2C WR[%02x] = %02x\n", reg, val);
+ return i2c_smbus_write_byte_data(client, reg, val);
+}
+
+static inline int ad9389_update_reg(struct i2c_client *client, u8 reg, u8 mask, u8 val)
+{
+ u8 regval = i2c_smbus_read_byte_data(client, reg);
+ regval &= ~mask;
+ regval |= val;
+ return ad9389_write_reg(client, reg, regval);
+}
+
+static void ad9389_set_av_mute(struct i2c_client *client, int mute)
+{
+ if (mute) {
+ ad9389_update_reg(client, 0x45, 0x40, 0x40);
+ ad9389_update_reg(client, 0x45, 0x80, 0);
+ } else {
+ ad9389_update_reg(client, 0x45, 0x40, 0x0);
+ ad9389_update_reg(client, 0x45, 0x80, 0x80);
+ }
+}
+
+static void ad9389_set_power_down(struct i2c_client *client, int powerd)
+{
+ ad9389_update_reg(client, 0x41, 0x40, powerd ? 0x40 : 0);
+}
+
+static int ad9389_disp_connected(struct i2c_client *client)
+{
+ return (ad9389_read_reg(client, 0x42) & 0x40) != 0;
+}
+
+static void ad9389_enable_i2s_ch(struct i2c_client *client, u8 enable, u8 ch)
+{
+ u8 mask;
+
+ if (ch > 3)
+ return;
+
+ mask = 0x04 << ch;
+ ad9389_update_reg(client, 0x0c, mask, enable ? mask : 0);
+}
+
+static int ad9389_is_enabled_i2s_ch(struct i2c_client *client, u8 ch)
+{
+ u8 mask;
+
+ if (ch > 3)
+ return -EINVAL;
+
+ mask = 0x04 << ch;
+ return (i2c_smbus_read_byte_data(client, 0x0c) & mask) != 0;
+}
+
+static void ad9389_set_i2s_sf(struct i2c_client *client, int sample_freq)
+{
+ ad9389_update_reg(client, 0x15, 0xf0, sample_freq << 4);
+}
+
+static void ad9389_set_hdmi_mode(struct i2c_client *client, int hdmi)
+{
+ ad9389_update_reg(client, 0xaf, 0x02, hdmi ? 0x02 : 0);
+}
+
+static void ad9389_set_if_cc(struct i2c_client *client, int chcnt)
+{
+ ad9389_update_reg(client, 0x50, 0xe0, chcnt << 5);
+}
+
+static void ad9389_set_spk_map(struct i2c_client *client, int map)
+{
+ ad9389_write_reg(client, 0x51, map);
+}
+
+static void ad9389_set_N(struct i2c_client *client, int N_val)
+{
+ ad9389_write_reg(client, 0x1, N_val >> 16);
+ ad9389_write_reg(client, 0x2, N_val >> 8);
+ ad9389_write_reg(client, 0x3, N_val & 0xff);
+}
+
+static int ad9389_get_N(struct i2c_client *client)
+{
+ int N_val;
+
+ N_val = (ad9389_read_reg(client, 0x1) & 0x0f) << 16;
+ N_val |= (ad9389_read_reg(client, 0x2) << 8);
+ N_val |= ad9389_read_reg(client, 0x3);
+
+ return N_val;
+}
+
+#ifdef USED
+static void ad9389_audio_set_CTS(struct i2c_client *client, int cts)
+{
+ ad9389_update_reg(client, 0x04, 0x0f, (cts >> 16) & 0x0f);
+ ad9389_write_reg(client, 0x05, cts >> 8);
+ ad9389_write_reg(client, 0x6, cts & 0xff);
+}
+
+static void ad9389_set_i2s_nbits(struct i2c_client *client, int bits)
+{
+ if (bits <= 24)
+ ad9389_write_reg(client, 0x0d, bits);
+}
+
+static void ad9389_set_low_freq_vrr(struct i2c_client *client, int lowf)
+{
+ ad9389_update_reg(client, 0x15, 0x01, lowf ? 1 : 0);
+}
+#endif
+
+#ifdef DEBUG
+static void ad9389_dump_edid(u8 *edid)
+{
+ int i;
+
+ if (!(debug & EDID_DBG))
+ return;
+
+ printk("\nEDID data:\n");
+ for (i = 0; i < EDID_LENGTH; i++) {
+ if (i % 8 == 0)
+ printk("\n");
+ printk("%02x ", edid[i]);
+ }
+ printk("\n");
+}
+
+static void ad9389_dump_regs(struct i2c_client *client)
+{
+ int i;
+
+ if (!(debug & REGS_DBG))
+ return;
+
+ printk("\nAD9389 regs:\n");
+ for (i = 0; i < EDID_LENGTH; i++) {
+ if (i % 8 == 0)
+ printk("\n%03x: ", i);
+ printk("%02x ", ad9389_read_reg(client, i));
+ }
+ printk(KERN_DEBUG "\n");
+}
+
+static void fb_dump_modeline( struct fb_videomode *modedb, int num)
+{
+ struct fb_videomode *mode;
+ int i;
+
+ if (!(debug & SCREEN_DBG))
+ return;
+
+ printk(KERN_DEBUG "Monitor/TV supported modelines:\n");
+
+ for (i = 0; i < num; i++) {
+ mode = &modedb[i];
+
+ printk(" \"%dx%d%s%d\" %lu.%02lu ",
+ mode->xres, mode->yres, (mode->vmode & FB_VMODE_INTERLACED) ? "i@" : "@", mode->refresh,
+ (PICOS2KHZ(mode->pixclock) * 1000UL)/1000000,
+ (PICOS2KHZ(mode->pixclock) ) % 1000);
+ printk("%d %d %d %d ",
+ mode->xres,
+ mode->xres + mode->right_margin,
+ mode->xres + mode->right_margin + mode->hsync_len,
+ mode->xres + mode->right_margin + mode->hsync_len + mode->left_margin );
+ printk("%d %d %d %d ",
+ mode->yres,
+ mode->yres + mode->lower_margin,
+ mode->yres + mode->lower_margin + mode->vsync_len,
+ mode->yres + mode->lower_margin + mode->vsync_len + mode->upper_margin );
+ printk("%shsync %svsync\n", (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? "+" : "-",
+ (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? "+" : "-" );
+ }
+}
+#else
+static void ad9389_dump_edid(u8 *edid) {}
+static void ad9389_dump_regs(struct i2c_client *client) {}
+static void fb_dump_modeline( struct fb_videomode *modedb, int num) {}
+#endif
+
+static int ad9389_read_edid(struct i2c_client *client, u8 *edid)
+{
+ union i2c_smbus_data data;
+ struct ad9389_pdata *config = client->dev.platform_data;
+ struct ad9389_dev *ad9389 = i2c_get_clientdata(client);
+ u8 *pd;
+ int status, i;
+
+ for (i = 0, pd = edid; i < EDID_LENGTH/I2C_SMBUS_BLOCK_MAX; i++, pd += I2C_SMBUS_BLOCK_MAX) {
+ data.block[0] = I2C_SMBUS_BLOCK_MAX;
+ status = i2c_smbus_xfer(ad9389->edid_ram->adapter, config->edid_addr,
+ ad9389->edid_ram->flags,
+ I2C_SMBUS_READ, i*I2C_SMBUS_BLOCK_MAX,
+ I2C_SMBUS_I2C_BLOCK_DATA, &data);
+ if (status < 0)
+ return status;
+ memcpy(pd, &data.block[1], data.block[0]);
+ }
+
+ return 0;
+}
+
+static int ad9389_parse_edid(struct fb_var_screeninfo *einfo, u8 *edid, int *dvi)
+{
+ int ret;
+
+ if (einfo == NULL || edid == NULL || dvi == NULL)
+ return -EINVAL;
+
+ if (edid[1] == 0x00)
+ return -ENOENT;
+
+ /* Assume dvi if no CEA extension */
+ *dvi = 1;
+ if (edid[126] > 0) {
+ /* CEA extensions */
+ if (edid[128] == 0x02 && edid[131] & 0x40) {
+ *dvi = 0;
+ }
+ }
+
+ ret = fb_parse_edid(edid, einfo);
+ if (ret)
+ return -ret;
+
+ /* This is valid for version 1.3 of the EDID */
+ if ((edid[18] == 1) && (edid[19] == 3)) {
+ einfo->height = edid[21] * 10;
+ einfo->width = edid[22] * 10;
+ }
+
+ return 0;
+}
+
+static void ad9389_audio_setup(struct ad9389_dev *ad9389)
+{
+ struct i2c_client *client = ad9389->client;
+
+ /* disable I2S channels */
+ ad9389_enable_i2s_ch(client, 0, 0);
+ ad9389_enable_i2s_ch(client, 0, 1);
+ ad9389_enable_i2s_ch(client, 0, 2);
+ ad9389_enable_i2s_ch(client, 0, 3);
+
+ /* Set sample freq, currently hardcoded to 44KHz */
+ ad9389_set_i2s_sf(client, 0);
+
+ /* By default, enable i2s ch0. Can be modified through the sysfs */
+ ad9389_set_N(client, 6272);
+ ad9389_set_if_cc(client, 1);
+ ad9389_set_spk_map(client, 0);
+ ad9389_enable_i2s_ch(client, 1, 0);
+ ad9389_set_av_mute(client, 0);
+}
+
+
+static void ad9389_fb_init(struct fb_info *info)
+{
+ struct ad9389_dev *ad9389 = pad9389;
+ struct i2c_client *client = ad9389->client;
+ struct ad9389_pdata *pdata = client->dev.platform_data;
+ static struct fb_var_screeninfo var;
+ int ret = 0;
+
+ dev_info(info->dev, "%s\n", __func__);
+
+ if (!ad9389_disp_connected(client)) {
+ ad9389_set_power_down(client, 1);
+ if(pdata->disp_disconnected)
+ pdata->disp_disconnected(ad9389);
+ return;
+ }
+
+ if(pdata->disp_connected)
+ pdata->disp_connected(ad9389);
+
+ dev_info(info->dev, "%s, display connected\n", __func__);
+ memset(&var, 0, sizeof(var));
+
+ /* Disable Power down and set mute to on */
+ ad9389_set_power_down(client, 0);
+ ad9389_set_av_mute(client, 1);
+
+ /* set static reserved registers*/
+ ad9389_write_reg(client,0x0a, 0x01);
+ ad9389_write_reg(client, 0x98, 0x03);
+ ad9389_write_reg(client, 0x9C, 0x38);
+
+ /* Write magic numbers */
+ ad9389_write_reg(client, 0xA2, 0x87);
+ ad9389_write_reg(client, 0xA3, 0x87);
+
+ /* set capture edge */
+ ad9389_write_reg(client, 0xba, 0x60);
+ ad9389_write_reg(client, 0x47, 0x80);
+
+ mdelay(250);
+
+ ret = ad9389_read_edid(ad9389->client, ad9389->edid_data);
+ if (!ret) {
+ ad9389_dump_edid(ad9389->edid_data);
+ ret = ad9389_parse_edid(&var, ad9389->edid_data, &ad9389->dvi);
+ if (!ret) {
+ if (!ad9389->dvi) {
+ ad9389_set_hdmi_mode(client, 1);
+ /* FIXME audio setup should be done once we know the pixclock */
+ ad9389_audio_setup(ad9389);
+ }
+
+ fb_edid_to_monspecs(ad9389->edid_data, &info->monspecs);
+ if (info->monspecs.modedb_len) {
+ fb_dump_modeline(info->monspecs.modedb, info->monspecs.modedb_len);
+ if (pdata->vmode_to_modelist)
+ pdata->vmode_to_modelist(info->monspecs.modedb,
+ info->monspecs.modedb_len,
+ &info->modelist, &var);
+ else
+ fb_videomode_to_modelist(info->monspecs.modedb,
+ info->monspecs.modedb_len,
+ &info->modelist);
+ }
+ }
+ } else {
+ /* TODO */
+ printk(KERN_WARNING "NO EDID information found, using default mode?\n");
+ }
+
+ ad9389_dump_regs(client);
+
+ if (pdata->vmode_to_var)
+ pdata->vmode_to_var(ad9389, &var);
+
+ var.activate = FB_ACTIVATE_ALL;
+ acquire_console_sem();
+ info->flags |= FBINFO_MISC_USEREVENT;
+ fb_set_var(info, &var);
+ info->flags &= ~FBINFO_MISC_USEREVENT;
+ fb_blank(info, FB_BLANK_UNBLANK);
+ fb_show_logo(info, 0);
+ release_console_sem();
+}
+
+int ad9389_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+ return 0;
+}
+
+static void ad9389_work(struct work_struct *work)
+{
+ struct ad9389_dev *ad9389 = container_of(work, struct ad9389_dev, work);
+ struct i2c_client *client = ad9389->client;
+ unsigned char irq_reg1;
+ unsigned char irq_reg2;
+
+ dev_dbg(&client->dev, "%s\n", __func__);
+
+ mutex_lock(&ad9389->irq_lock);
+
+ /* Interrupts are disabled here... */
+ irq_reg1 = ad9389_read_reg(client, 0x96);
+ irq_reg2 = ad9389_read_reg(client, 0x97);
+
+ while ((irq_reg1 & 0xc4) | (irq_reg2 & 0xc0)) {
+
+ dev_dbg(&client->dev, "IRQ register %02x/%02x\n",
+ irq_reg1, irq_reg2);
+
+ /* hot plug detections interrupt? */
+ if (irq_reg1 & HPD_INT) {
+ dev_dbg(&client->dev, "HPD irq\n");
+ ad9389_fb_init(ad9389->fbi);
+ }
+
+ /* check for EDID ready flag, then call EDID Handler */
+ if (irq_reg1 & EDID_RDY_INT) {
+ dev_dbg(&client->dev, "EDID_RDY_INT\n");
+ }
+
+ /* ack and check again */
+ ad9389_write_reg(client, 0x96, irq_reg1);
+ ad9389_write_reg(client, 0x97, irq_reg2);
+
+ irq_reg1 = ad9389_read_reg(client, 0x96);
+ irq_reg2 = ad9389_read_reg(client, 0x97);
+ }
+
+ mutex_unlock(&ad9389->irq_lock);
+}
+
+
+static irqreturn_t ad9389_handler(int irq, void *dev_id)
+{
+ struct ad9389_dev *dev = (struct ad9389_dev *) dev_id;
+
+ dev_dbg(&dev->client->dev, "%s\n", __func__);
+ schedule_work(&dev->work);
+
+ return IRQ_HANDLED;
+}
+
+static ssize_t ad9389_show_mute(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ int read, ret = 0;
+
+ read = ad9389_read_reg(client, 0x45);
+ if (read & 0x40)
+ ret = snprintf(buf, PAGE_SIZE, "on");
+ else if (read & 0x80)
+ ret = snprintf(buf, PAGE_SIZE, "off");
+
+ return ret;
+}
+
+static ssize_t ad9389_store_mute(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ int mute;
+
+ if (!strcmp(buf, "on"))
+ mute = 1;
+ else if (!strcmp(buf, "off"))
+ mute = 0;
+ else
+ return 0;
+
+ ad9389_set_av_mute(client, mute);
+
+ return count;
+}
+
+static ssize_t ad9389_show_N_param(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ int N_val;
+
+ N_val = ad9389_get_N(client);
+
+ return snprintf(buf, PAGE_SIZE, "%d", N_val);
+}
+
+static ssize_t ad9389_store_N_param(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ unsigned long N_val;
+
+ N_val = simple_strtoul(buf, NULL, 10);
+ ad9389_set_N(client, N_val);
+
+ return count;
+}
+
+#define ad9389_show_i2s_ch(num) \
+static ssize_t ad9389_show_i2s_ch##num(struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
+{ \
+ struct i2c_client *client = to_i2c_client(dev); \
+ int read, ret = 0; \
+ read = ad9389_is_enabled_i2s_ch(client, num); \
+ if (read < 0) \
+ ret = snprintf(buf, PAGE_SIZE, "error"); \
+ else if (read == 1) \
+ ret = snprintf(buf, PAGE_SIZE, "on"); \
+ else \
+ ret = snprintf(buf, PAGE_SIZE, "off"); \
+ return ret; \
+}
+
+#define ad9389_store_i2s_ch(num) \
+static ssize_t ad9389_store_i2s_ch##num(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
+{ \
+ struct i2c_client *client = to_i2c_client(dev); \
+ int enable; \
+ if (!strcmp(buf, "on")) \
+ enable = 1; \
+ else if (!strcmp(buf, "off")) \
+ enable = 0; \
+ else \
+ return 0; \
+ ad9389_enable_i2s_ch(client, enable, num); \
+ return count; \
+}
+
+#define audio_ch(num) \
+ static DEVICE_ATTR(i2s_ch##num, S_IWUSR | S_IRUGO, ad9389_show_i2s_ch##num, ad9389_store_i2s_ch##num)
+
+static DEVICE_ATTR(mute, S_IWUSR | S_IRUGO, ad9389_show_mute, ad9389_store_mute);
+static DEVICE_ATTR(N_param, S_IWUSR | S_IRUGO, ad9389_show_N_param, ad9389_store_N_param);
+
+ad9389_show_i2s_ch(0)
+ad9389_show_i2s_ch(1)
+ad9389_show_i2s_ch(2)
+ad9389_show_i2s_ch(3)
+ad9389_store_i2s_ch(0)
+ad9389_store_i2s_ch(1)
+ad9389_store_i2s_ch(2)
+ad9389_store_i2s_ch(3)
+audio_ch(0);
+audio_ch(1);
+audio_ch(2);
+audio_ch(3);
+
+static struct attribute *ad9389_attributes[] = {
+ &dev_attr_mute.attr,
+ &dev_attr_i2s_ch0.attr,
+ &dev_attr_i2s_ch1.attr,
+ &dev_attr_i2s_ch2.attr,
+ &dev_attr_i2s_ch3.attr,
+ &dev_attr_N_param.attr,
+ NULL
+};
+
+static const struct attribute_group ad9389_attr_group = {
+ .attrs = ad9389_attributes,
+};
+
+static struct notifier_block nb = {
+ .notifier_call = ad9389_fb_event,
+};
+
+static int ad9389_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ad9389_pdata *pdata = client->dev.platform_data;
+ struct ad9389_dev *ad9389;
+ int ret = -EINVAL;
+
+ /* Sanity checks */
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -EIO;
+
+ if (!pdata) {
+ printk(KERN_ERR DRV_NAME ": Platform data not supplied\n");
+ return -ENOENT;
+ }
+
+ if (!client->irq) {
+ printk(KERN_ERR DRV_NAME ": Invalid irq value\n");
+ return -ENOENT;
+ }
+
+ ad9389 = kzalloc(sizeof(struct ad9389_dev), GFP_KERNEL);
+ if (ad9389 == NULL)
+ return -ENOMEM;
+
+ ad9389->edid_data = kmalloc(EDID_LENGTH, GFP_KERNEL);
+ if (ad9389->edid_data == NULL) {
+ ret = -ENOMEM;
+ goto err_edid_alloc;
+ }
+
+ pad9389 = ad9389;
+ ad9389->client = client;
+ i2c_set_clientdata(client, ad9389);
+
+ INIT_WORK(&ad9389->work, ad9389_work);
+ mutex_init(&ad9389->irq_lock);
+ mutex_lock(&ad9389->irq_lock);
+
+ /* platform specific initialization (gpio, irq...) */
+ if (pdata->hw_init)
+ pdata->hw_init(ad9389);
+
+ ret = request_irq(client->irq, ad9389_handler,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, DRV_NAME, ad9389);
+ if (ret < 0) {
+ printk(KERN_ERR DRV_NAME ": Could not allocate IRQ (n %d)\n", client->irq);
+ goto err_irq;
+ }
+
+ /**
+ * There is no good way to detect if the chip is present. We assume that its present
+ * because somebody answered (ack) on the device address...
+ */
+ ret = ad9389_read_reg(client, 0x00);
+ if (ret < 0) {
+ printk(KERN_WARNING DRV_NAME ": i2c transfer error, (device present?)\n");
+ ret = -ENODEV;
+ goto err_presence;
+ }
+
+ ad9389->chiprev = (u8)ret;
+ ad9389->edid_ram = i2c_new_dummy(client->adapter, pdata->edid_addr);
+ if (!ad9389->edid_ram) {
+ printk(KERN_WARNING DRV_NAME ": can't add i2c device at 0x%x\n", pdata->edid_addr);
+ goto err_presence;
+ }
+
+ /* Register sysfs hooks */
+ ret = sysfs_create_group(&client->dev.kobj, &ad9389_attr_group);
+ if (ret)
+ goto err_sysfs_file;
+
+ ad9389->fbi = registered_fb[pdata->dispif];
+ fb_register_client(&nb);
+
+ /* Ack any active interrupt and enable irqs */
+ ad9389_write_reg(client, 0x94, 0x84);
+ ad9389_write_reg(client, 0x95, 0xc3);
+ ad9389_write_reg(client, 0x96, 0x84);
+ ad9389_write_reg(client, 0x97, 0xc3);
+
+ mutex_unlock(&ad9389->irq_lock);
+
+ ad9389_fb_init(registered_fb[pdata->dispif]);
+
+ printk(KERN_INFO DRV_NAME ": device detected at address 0x%x, chip revision 0x%02x\n",
+ client->addr << 1, ad9389->chiprev);
+
+ return 0;
+
+err_sysfs_file:
+ i2c_unregister_device(ad9389->edid_ram);
+err_presence:
+ free_irq(client->irq, ad9389);
+err_irq:
+ flush_scheduled_work();
+ if (pdata->hw_deinit)
+ pdata->hw_deinit(ad9389);
+ kfree(ad9389->edid_data);
+err_edid_alloc:
+ kfree(ad9389);
+ pad9389 = NULL;
+ return ret;
+}
+
+static int ad9389_remove(struct i2c_client *client)
+{
+ struct ad9389_pdata *pdata = client->dev.platform_data;
+ struct ad9389_dev *ad9389 = i2c_get_clientdata(client);
+
+ free_irq(client->irq, ad9389);
+ flush_scheduled_work();
+ sysfs_remove_group(&client->dev.kobj, &ad9389_attr_group);
+ i2c_unregister_device(ad9389->edid_ram);
+ fb_unregister_client(&nb);
+ kfree(ad9389->edid_data);
+ kfree(ad9389);
+ pad9389 = NULL;
+
+ if (pdata->hw_deinit)
+ pdata->hw_deinit(ad9389);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int ad9389_suspend(struct i2c_client *client, pm_message_t state)
+{
+ dev_dbg(&client->dev, "PM suspend\n");
+ ad9389_set_power_down(client, 1);
+
+ return 0;
+}
+
+static int ad9389_resume(struct i2c_client *client)
+{
+ struct ad9389_dev *ad9389 = pad9389;
+ int ret;
+ static struct fb_var_screeninfo var;
+
+ dev_dbg(&client->dev, "PM resume\n");
+
+ /* Disable Power down and set mute to on */
+ ad9389_set_power_down(client, 0);
+ ad9389_set_av_mute(client, 1);
+
+ /* set static reserved registers*/
+ ad9389_write_reg(client,0x0a, 0x01);
+ ad9389_write_reg(client, 0x98, 0x03);
+ ad9389_write_reg(client, 0x9C, 0x38);
+
+ /* Write magic numbers */
+ ad9389_write_reg(client, 0xA2, 0x87);
+ ad9389_write_reg(client, 0xA3, 0x87);
+
+ /* set capture edge */
+ ad9389_write_reg(client, 0xba, 0x60);
+ ad9389_write_reg(client, 0x47, 0x80);
+
+ mdelay(250);
+
+ ret = ad9389_read_edid(ad9389->client, ad9389->edid_data);
+ if (!ret) {
+ ad9389_dump_edid(ad9389->edid_data);
+ ret = ad9389_parse_edid(&var, ad9389->edid_data, &ad9389->dvi);
+ if (!ret) {
+ if (!ad9389->dvi) {
+ ad9389_set_hdmi_mode(client, 1);
+ /* FIXME audio setup should be done once we know the pixclock */
+ ad9389_audio_setup(ad9389);
+ }
+ }
+ }
+ return 0;
+}
+#else
+#define ad9389_suspend NULL
+#define ad9389_resume NULL
+#endif
+
+
+static struct i2c_device_id ad9389_id[] = {
+ { "ad9389", 0 },
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, ad9389_id);
+
+static struct i2c_driver ad9389_driver = {
+ .driver = {
+ .name = "ad9389",
+ },
+ .probe = ad9389_probe,
+ .remove = ad9389_remove,
+ .suspend = ad9389_suspend,
+ .resume = ad9389_resume,
+ .id_table = ad9389_id,
+
+};
+
+static int __init ad9389_init(void)
+{
+ return i2c_add_driver(&ad9389_driver);
+}
+
+static void __exit ad9389_exit(void)
+{
+ i2c_del_driver(&ad9389_driver);
+}
+
+module_init(ad9389_init);
+module_exit(ad9389_exit);
+
+MODULE_DESCRIPTION("AD9389 hdmi/dvi driver");
+MODULE_AUTHOR("Digi International Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/elcdif_regs.h b/drivers/video/mxc/elcdif_regs.h
new file mode 100644
index 000000000000..2eceba5864e0
--- /dev/null
+++ b/drivers/video/mxc/elcdif_regs.h
@@ -0,0 +1,678 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on arch/arm/mach-mx28/include/mach/regs-lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#ifndef __ELCDIF_REGS_INCLUDED_
+#define __ELCDIF_REGS_INCLUDED_
+
+#define HW_ELCDIF_CTRL (0x00000000)
+#define HW_ELCDIF_CTRL_SET (0x00000004)
+#define HW_ELCDIF_CTRL_CLR (0x00000008)
+#define HW_ELCDIF_CTRL_TOG (0x0000000c)
+
+#define BM_ELCDIF_CTRL_SFTRST 0x80000000
+#define BM_ELCDIF_CTRL_CLKGATE 0x40000000
+#define BM_ELCDIF_CTRL_YCBCR422_INPUT 0x20000000
+#define BM_ELCDIF_CTRL_READ_WRITEB 0x10000000
+#define BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
+#define BM_ELCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0
+#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1
+#define BP_ELCDIF_CTRL_SHIFT_NUM_BITS 21
+#define BM_ELCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
+#define BF_ELCDIF_CTRL_SHIFT_NUM_BITS(v) \
+ (((v) << 21) & BM_ELCDIF_CTRL_SHIFT_NUM_BITS)
+#define BM_ELCDIF_CTRL_DVI_MODE 0x00100000
+#define BM_ELCDIF_CTRL_BYPASS_COUNT 0x00080000
+#define BM_ELCDIF_CTRL_VSYNC_MODE 0x00040000
+#define BM_ELCDIF_CTRL_DOTCLK_MODE 0x00020000
+#define BM_ELCDIF_CTRL_DATA_SELECT 0x00010000
+#define BV_ELCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0
+#define BV_ELCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1
+#define BP_ELCDIF_CTRL_INPUT_DATA_SWIZZLE 14
+#define BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
+#define BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \
+ (((v) << 14) & BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2
+#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3
+#define BP_ELCDIF_CTRL_CSC_DATA_SWIZZLE 12
+#define BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000
+#define BF_ELCDIF_CTRL_CSC_DATA_SWIZZLE(v) \
+ (((v) << 12) & BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE)
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2
+#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3
+#define BP_ELCDIF_CTRL_LCD_DATABUS_WIDTH 10
+#define BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
+#define BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(v) \
+ (((v) << 10) & BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH)
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3
+#define BP_ELCDIF_CTRL_WORD_LENGTH 8
+#define BM_ELCDIF_CTRL_WORD_LENGTH 0x00000300
+#define BF_ELCDIF_CTRL_WORD_LENGTH(v) \
+ (((v) << 8) & BM_ELCDIF_CTRL_WORD_LENGTH)
+#define BV_ELCDIF_CTRL_WORD_LENGTH__16_BIT 0x0
+#define BV_ELCDIF_CTRL_WORD_LENGTH__8_BIT 0x1
+#define BV_ELCDIF_CTRL_WORD_LENGTH__18_BIT 0x2
+#define BV_ELCDIF_CTRL_WORD_LENGTH__24_BIT 0x3
+#define BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
+#define BM_ELCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040
+#define BM_ELCDIF_CTRL_ELCDIF_MASTER 0x00000020
+#define BM_ELCDIF_CTRL_RSRVD0 0x00000010
+#define BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008
+#define BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1
+#define BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0
+#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1
+#define BM_ELCDIF_CTRL_RUN 0x00000001
+
+#define HW_ELCDIF_CTRL1 (0x00000010)
+#define HW_ELCDIF_CTRL1_SET (0x00000014)
+#define HW_ELCDIF_CTRL1_CLR (0x00000018)
+#define HW_ELCDIF_CTRL1_TOG (0x0000001c)
+
+#define BP_ELCDIF_CTRL1_RSRVD1 28
+#define BM_ELCDIF_CTRL1_RSRVD1 0xF0000000
+#define BF_ELCDIF_CTRL1_RSRVD1(v) \
+ (((v) << 28) & BM_ELCDIF_CTRL1_RSRVD1)
+#define BM_ELCDIF_CTRL1_COMBINE_MPU_WR_STRB 0x08000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000
+#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ 0x02000000
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1
+#define BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
+#define BM_ELCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
+#define BM_ELCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000
+#define BM_ELCDIF_CTRL1_FIFO_CLEAR 0x00200000
+#define BM_ELCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000
+#define BP_ELCDIF_CTRL1_BYTE_PACKING_FORMAT 16
+#define BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
+#define BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \
+ (((v) << 16) & BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT)
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
+#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1
+#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1
+#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1
+#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0
+#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1
+#define BP_ELCDIF_CTRL1_RSRVD0 3
+#define BM_ELCDIF_CTRL1_RSRVD0 0x000000F8
+#define BF_ELCDIF_CTRL1_RSRVD0(v) \
+ (((v) << 3) & BM_ELCDIF_CTRL1_RSRVD0)
+#define BM_ELCDIF_CTRL1_BUSY_ENABLE 0x00000004
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0
+#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1
+#define BM_ELCDIF_CTRL1_MODE86 0x00000002
+#define BV_ELCDIF_CTRL1_MODE86__8080_MODE 0x0
+#define BV_ELCDIF_CTRL1_MODE86__6800_MODE 0x1
+#define BM_ELCDIF_CTRL1_RESET 0x00000001
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_LOW 0x0
+#define BV_ELCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1
+
+#define HW_ELCDIF_CTRL2 (0x00000020)
+#define HW_ELCDIF_CTRL2_SET (0x00000024)
+#define HW_ELCDIF_CTRL2_CLR (0x00000028)
+#define HW_ELCDIF_CTRL2_TOG (0x0000002c)
+
+#define BP_ELCDIF_CTRL2_RSRVD5 24
+#define BM_ELCDIF_CTRL2_RSRVD5 0xFF000000
+#define BF_ELCDIF_CTRL2_RSRVD5(v) \
+ (((v) << 24) & BM_ELCDIF_CTRL2_RSRVD5)
+#define BP_ELCDIF_CTRL2_OUTSTANDING_REQS 21
+#define BM_ELCDIF_CTRL2_OUTSTANDING_REQS 0x00E00000
+#define BF_ELCDIF_CTRL2_OUTSTANDING_REQS(v) \
+ (((v) << 21) & BM_ELCDIF_CTRL2_OUTSTANDING_REQS)
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_1 0x0
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_2 0x1
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_4 0x2
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8 0x3
+#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4
+#define BM_ELCDIF_CTRL2_BURST_LEN_8 0x00100000
+#define BM_ELCDIF_CTRL2_RSRVD4 0x00080000
+#define BP_ELCDIF_CTRL2_ODD_LINE_PATTERN 16
+#define BM_ELCDIF_CTRL2_ODD_LINE_PATTERN 0x00070000
+#define BF_ELCDIF_CTRL2_ODD_LINE_PATTERN(v) \
+ (((v) << 16) & BM_ELCDIF_CTRL2_ODD_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD3 0x00008000
+#define BP_ELCDIF_CTRL2_EVEN_LINE_PATTERN 12
+#define BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN 0x00007000
+#define BF_ELCDIF_CTRL2_EVEN_LINE_PATTERN(v) \
+ (((v) << 12) & BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN)
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4
+#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5
+#define BM_ELCDIF_CTRL2_RSRVD2 0x00000800
+#define BM_ELCDIF_CTRL2_READ_PACK_DIR 0x00000400
+#define BM_ELCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT 0x00000200
+#define BM_ELCDIF_CTRL2_READ_MODE_6_BIT_INPUT 0x00000100
+#define BM_ELCDIF_CTRL2_RSRVD1 0x00000080
+#define BP_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 4
+#define BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 0x00000070
+#define BF_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v) \
+ (((v) << 4) & BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS)
+#define BP_ELCDIF_CTRL2_INITIAL_DUMMY_READ 1
+#define BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ 0x0000000E
+#define BF_ELCDIF_CTRL2_INITIAL_DUMMY_READ(v) \
+ (((v) << 1) & BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ)
+#define BM_ELCDIF_CTRL2_RSRVD0 0x00000001
+
+#define HW_ELCDIF_TRANSFER_COUNT (0x00000030)
+
+#define BP_ELCDIF_TRANSFER_COUNT_V_COUNT 16
+#define BM_ELCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
+#define BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v) \
+ (((v) << 16) & BM_ELCDIF_TRANSFER_COUNT_V_COUNT)
+#define BP_ELCDIF_TRANSFER_COUNT_H_COUNT 0
+#define BM_ELCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
+#define BF_ELCDIF_TRANSFER_COUNT_H_COUNT(v) \
+ (((v) << 0) & BM_ELCDIF_TRANSFER_COUNT_H_COUNT)
+
+#define HW_ELCDIF_CUR_BUF (0x00000040)
+
+#define BP_ELCDIF_CUR_BUF_ADDR 0
+#define BM_ELCDIF_CUR_BUF_ADDR 0xFFFFFFFF
+#define BF_ELCDIF_CUR_BUF_ADDR(v) (v)
+
+#define HW_ELCDIF_NEXT_BUF (0x00000050)
+
+#define BP_ELCDIF_NEXT_BUF_ADDR 0
+#define BM_ELCDIF_NEXT_BUF_ADDR 0xFFFFFFFF
+#define BF_ELCDIF_NEXT_BUF_ADDR(v) (v)
+
+#define HW_ELCDIF_TIMING (0x00000060)
+
+#define BP_ELCDIF_TIMING_CMD_HOLD 24
+#define BM_ELCDIF_TIMING_CMD_HOLD 0xFF000000
+#define BF_ELCDIF_TIMING_CMD_HOLD(v) \
+ (((v) << 24) & BM_ELCDIF_TIMING_CMD_HOLD)
+#define BP_ELCDIF_TIMING_CMD_SETUP 16
+#define BM_ELCDIF_TIMING_CMD_SETUP 0x00FF0000
+#define BF_ELCDIF_TIMING_CMD_SETUP(v) \
+ (((v) << 16) & BM_ELCDIF_TIMING_CMD_SETUP)
+#define BP_ELCDIF_TIMING_DATA_HOLD 8
+#define BM_ELCDIF_TIMING_DATA_HOLD 0x0000FF00
+#define BF_ELCDIF_TIMING_DATA_HOLD(v) \
+ (((v) << 8) & BM_ELCDIF_TIMING_DATA_HOLD)
+#define BP_ELCDIF_TIMING_DATA_SETUP 0
+#define BM_ELCDIF_TIMING_DATA_SETUP 0x000000FF
+#define BF_ELCDIF_TIMING_DATA_SETUP(v) \
+ (((v) << 0) & BM_ELCDIF_TIMING_DATA_SETUP)
+
+#define HW_ELCDIF_VDCTRL0 (0x00000070)
+#define HW_ELCDIF_VDCTRL0_SET (0x00000074)
+#define HW_ELCDIF_VDCTRL0_CLR (0x00000078)
+#define HW_ELCDIF_VDCTRL0_TOG (0x0000007c)
+
+#define BP_ELCDIF_VDCTRL0_RSRVD2 30
+#define BM_ELCDIF_VDCTRL0_RSRVD2 0xC0000000
+#define BF_ELCDIF_VDCTRL0_RSRVD2(v) \
+ (((v) << 30) & BM_ELCDIF_VDCTRL0_RSRVD2)
+#define BM_ELCDIF_VDCTRL0_VSYNC_OEB 0x20000000
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0
+#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1
+#define BM_ELCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
+#define BM_ELCDIF_VDCTRL0_VSYNC_POL 0x08000000
+#define BM_ELCDIF_VDCTRL0_HSYNC_POL 0x04000000
+#define BM_ELCDIF_VDCTRL0_DOTCLK_POL 0x02000000
+#define BM_ELCDIF_VDCTRL0_ENABLE_POL 0x01000000
+#define BP_ELCDIF_VDCTRL0_RSRVD1 22
+#define BM_ELCDIF_VDCTRL0_RSRVD1 0x00C00000
+#define BF_ELCDIF_VDCTRL0_RSRVD1(v) \
+ (((v) << 22) & BM_ELCDIF_VDCTRL0_RSRVD1)
+#define BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE 0x00080000
+#define BM_ELCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000
+#define BP_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
+#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
+#define BF_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \
+ (((v) << 0) & BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH)
+
+#define HW_ELCDIF_VDCTRL1 (0x00000080)
+
+#define BP_ELCDIF_VDCTRL1_VSYNC_PERIOD 0
+#define BM_ELCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
+#define BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v) (v)
+
+#define HW_ELCDIF_VDCTRL2 (0x00000090)
+
+#define BP_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 18
+#define BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFFFC0000
+#define BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \
+ (((v) << 18) & BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH)
+#define BP_ELCDIF_VDCTRL2_HSYNC_PERIOD 0
+#define BM_ELCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
+#define BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(v) \
+ (((v) << 0) & BM_ELCDIF_VDCTRL2_HSYNC_PERIOD)
+
+#define HW_ELCDIF_VDCTRL3 (0x000000a0)
+
+#define BP_ELCDIF_VDCTRL3_RSRVD0 30
+#define BM_ELCDIF_VDCTRL3_RSRVD0 0xC0000000
+#define BF_ELCDIF_VDCTRL3_RSRVD0(v) \
+ (((v) << 30) & BM_ELCDIF_VDCTRL3_RSRVD0)
+#define BM_ELCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000
+#define BM_ELCDIF_VDCTRL3_VSYNC_ONLY 0x10000000
+#define BP_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
+#define BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
+#define BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \
+ (((v) << 16) & BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT)
+#define BP_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
+#define BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
+#define BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \
+ (((v) << 0) & BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT)
+
+#define HW_ELCDIF_VDCTRL4 (0x000000b0)
+
+#define BP_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL 29
+#define BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL 0xE0000000
+#define BF_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \
+ (((v) << 29) & BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL)
+#define BP_ELCDIF_VDCTRL4_RSRVD0 19
+#define BM_ELCDIF_VDCTRL4_RSRVD0 0x1FF80000
+#define BF_ELCDIF_VDCTRL4_RSRVD0(v) \
+ (((v) << 19) & BM_ELCDIF_VDCTRL4_RSRVD0)
+#define BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
+#define BP_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
+#define BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
+#define BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \
+ (((v) << 0) & BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT)
+
+#define HW_ELCDIF_DVICTRL0 (0x000000c0)
+
+#define BP_ELCDIF_DVICTRL0_RSRVD1 28
+#define BM_ELCDIF_DVICTRL0_RSRVD1 0xF0000000
+#define BF_ELCDIF_DVICTRL0_RSRVD1(v) \
+ (((v) << 28) & BM_ELCDIF_DVICTRL0_RSRVD1)
+#define BP_ELCDIF_DVICTRL0_H_ACTIVE_CNT 16
+#define BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT 0x0FFF0000
+#define BF_ELCDIF_DVICTRL0_H_ACTIVE_CNT(v) \
+ (((v) << 16) & BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT)
+#define BP_ELCDIF_DVICTRL0_RSRVD0 12
+#define BM_ELCDIF_DVICTRL0_RSRVD0 0x0000F000
+#define BF_ELCDIF_DVICTRL0_RSRVD0(v) \
+ (((v) << 12) & BM_ELCDIF_DVICTRL0_RSRVD0)
+#define BP_ELCDIF_DVICTRL0_H_BLANKING_CNT 0
+#define BM_ELCDIF_DVICTRL0_H_BLANKING_CNT 0x00000FFF
+#define BF_ELCDIF_DVICTRL0_H_BLANKING_CNT(v) \
+ (((v) << 0) & BM_ELCDIF_DVICTRL0_H_BLANKING_CNT)
+
+#define HW_ELCDIF_DVICTRL1 (0x000000d0)
+
+#define BP_ELCDIF_DVICTRL1_RSRVD0 30
+#define BM_ELCDIF_DVICTRL1_RSRVD0 0xC0000000
+#define BF_ELCDIF_DVICTRL1_RSRVD0(v) \
+ (((v) << 30) & BM_ELCDIF_DVICTRL1_RSRVD0)
+#define BP_ELCDIF_DVICTRL1_F1_START_LINE 20
+#define BM_ELCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
+#define BF_ELCDIF_DVICTRL1_F1_START_LINE(v) \
+ (((v) << 20) & BM_ELCDIF_DVICTRL1_F1_START_LINE)
+#define BP_ELCDIF_DVICTRL1_F1_END_LINE 10
+#define BM_ELCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
+#define BF_ELCDIF_DVICTRL1_F1_END_LINE(v) \
+ (((v) << 10) & BM_ELCDIF_DVICTRL1_F1_END_LINE)
+#define BP_ELCDIF_DVICTRL1_F2_START_LINE 0
+#define BM_ELCDIF_DVICTRL1_F2_START_LINE 0x000003FF
+#define BF_ELCDIF_DVICTRL1_F2_START_LINE(v) \
+ (((v) << 0) & BM_ELCDIF_DVICTRL1_F2_START_LINE)
+
+#define HW_ELCDIF_DVICTRL2 (0x000000e0)
+
+#define BP_ELCDIF_DVICTRL2_RSRVD0 30
+#define BM_ELCDIF_DVICTRL2_RSRVD0 0xC0000000
+#define BF_ELCDIF_DVICTRL2_RSRVD0(v) \
+ (((v) << 30) & BM_ELCDIF_DVICTRL2_RSRVD0)
+#define BP_ELCDIF_DVICTRL2_F2_END_LINE 20
+#define BM_ELCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
+#define BF_ELCDIF_DVICTRL2_F2_END_LINE(v) \
+ (((v) << 20) & BM_ELCDIF_DVICTRL2_F2_END_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_START_LINE 10
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \
+ (((v) << 10) & BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL2_V1_BLANK_END_LINE 0
+#define BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
+#define BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \
+ (((v) << 0) & BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE)
+
+#define HW_ELCDIF_DVICTRL3 (0x000000f0)
+
+#define BP_ELCDIF_DVICTRL3_RSRVD0 30
+#define BM_ELCDIF_DVICTRL3_RSRVD0 0xC0000000
+#define BF_ELCDIF_DVICTRL3_RSRVD0(v) \
+ (((v) << 30) & BM_ELCDIF_DVICTRL3_RSRVD0)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_START_LINE 20
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3FF00000
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \
+ (((v) << 20) & BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE)
+#define BP_ELCDIF_DVICTRL3_V2_BLANK_END_LINE 10
+#define BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000FFC00
+#define BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \
+ (((v) << 10) & BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE)
+#define BP_ELCDIF_DVICTRL3_V_LINES_CNT 0
+#define BM_ELCDIF_DVICTRL3_V_LINES_CNT 0x000003FF
+#define BF_ELCDIF_DVICTRL3_V_LINES_CNT(v) \
+ (((v) << 0) & BM_ELCDIF_DVICTRL3_V_LINES_CNT)
+
+#define HW_ELCDIF_DVICTRL4 (0x00000100)
+
+#define BP_ELCDIF_DVICTRL4_Y_FILL_VALUE 24
+#define BM_ELCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
+#define BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(v) \
+ (((v) << 24) & BM_ELCDIF_DVICTRL4_Y_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CB_FILL_VALUE 16
+#define BM_ELCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
+#define BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(v) \
+ (((v) << 16) & BM_ELCDIF_DVICTRL4_CB_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_CR_FILL_VALUE 8
+#define BM_ELCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
+#define BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(v) \
+ (((v) << 8) & BM_ELCDIF_DVICTRL4_CR_FILL_VALUE)
+#define BP_ELCDIF_DVICTRL4_H_FILL_CNT 0
+#define BM_ELCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
+#define BF_ELCDIF_DVICTRL4_H_FILL_CNT(v) \
+ (((v) << 0) & BM_ELCDIF_DVICTRL4_H_FILL_CNT)
+
+#define HW_ELCDIF_CSC_COEFF0 (0x00000110)
+
+#define BP_ELCDIF_CSC_COEFF0_RSRVD1 26
+#define BM_ELCDIF_CSC_COEFF0_RSRVD1 0xFC000000
+#define BF_ELCDIF_CSC_COEFF0_RSRVD1(v) \
+ (((v) << 26) & BM_ELCDIF_CSC_COEFF0_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF0_C0 16
+#define BM_ELCDIF_CSC_COEFF0_C0 0x03FF0000
+#define BF_ELCDIF_CSC_COEFF0_C0(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_COEFF0_C0)
+#define BP_ELCDIF_CSC_COEFF0_RSRVD0 2
+#define BM_ELCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC
+#define BF_ELCDIF_CSC_COEFF0_RSRVD0(v) \
+ (((v) << 2) & BM_ELCDIF_CSC_COEFF0_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
+#define BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
+#define BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER)
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2
+#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3
+
+#define HW_ELCDIF_CSC_COEFF1 (0x00000120)
+
+#define BP_ELCDIF_CSC_COEFF1_RSRVD1 26
+#define BM_ELCDIF_CSC_COEFF1_RSRVD1 0xFC000000
+#define BF_ELCDIF_CSC_COEFF1_RSRVD1(v) \
+ (((v) << 26) & BM_ELCDIF_CSC_COEFF1_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF1_C2 16
+#define BM_ELCDIF_CSC_COEFF1_C2 0x03FF0000
+#define BF_ELCDIF_CSC_COEFF1_C2(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_COEFF1_C2)
+#define BP_ELCDIF_CSC_COEFF1_RSRVD0 10
+#define BM_ELCDIF_CSC_COEFF1_RSRVD0 0x0000FC00
+#define BF_ELCDIF_CSC_COEFF1_RSRVD0(v) \
+ (((v) << 10) & BM_ELCDIF_CSC_COEFF1_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF1_C1 0
+#define BM_ELCDIF_CSC_COEFF1_C1 0x000003FF
+#define BF_ELCDIF_CSC_COEFF1_C1(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_COEFF1_C1)
+
+#define HW_ELCDIF_CSC_COEFF2 (0x00000130)
+
+#define BP_ELCDIF_CSC_COEFF2_RSRVD1 26
+#define BM_ELCDIF_CSC_COEFF2_RSRVD1 0xFC000000
+#define BF_ELCDIF_CSC_COEFF2_RSRVD1(v) \
+ (((v) << 26) & BM_ELCDIF_CSC_COEFF2_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF2_C4 16
+#define BM_ELCDIF_CSC_COEFF2_C4 0x03FF0000
+#define BF_ELCDIF_CSC_COEFF2_C4(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_COEFF2_C4)
+#define BP_ELCDIF_CSC_COEFF2_RSRVD0 10
+#define BM_ELCDIF_CSC_COEFF2_RSRVD0 0x0000FC00
+#define BF_ELCDIF_CSC_COEFF2_RSRVD0(v) \
+ (((v) << 10) & BM_ELCDIF_CSC_COEFF2_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF2_C3 0
+#define BM_ELCDIF_CSC_COEFF2_C3 0x000003FF
+#define BF_ELCDIF_CSC_COEFF2_C3(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_COEFF2_C3)
+
+#define HW_ELCDIF_CSC_COEFF3 (0x00000140)
+
+#define BP_ELCDIF_CSC_COEFF3_RSRVD1 26
+#define BM_ELCDIF_CSC_COEFF3_RSRVD1 0xFC000000
+#define BF_ELCDIF_CSC_COEFF3_RSRVD1(v) \
+ (((v) << 26) & BM_ELCDIF_CSC_COEFF3_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF3_C6 16
+#define BM_ELCDIF_CSC_COEFF3_C6 0x03FF0000
+#define BF_ELCDIF_CSC_COEFF3_C6(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_COEFF3_C6)
+#define BP_ELCDIF_CSC_COEFF3_RSRVD0 10
+#define BM_ELCDIF_CSC_COEFF3_RSRVD0 0x0000FC00
+#define BF_ELCDIF_CSC_COEFF3_RSRVD0(v) \
+ (((v) << 10) & BM_ELCDIF_CSC_COEFF3_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF3_C5 0
+#define BM_ELCDIF_CSC_COEFF3_C5 0x000003FF
+#define BF_ELCDIF_CSC_COEFF3_C5(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_COEFF3_C5)
+
+#define HW_ELCDIF_CSC_COEFF4 (0x00000150)
+
+#define BP_ELCDIF_CSC_COEFF4_RSRVD1 26
+#define BM_ELCDIF_CSC_COEFF4_RSRVD1 0xFC000000
+#define BF_ELCDIF_CSC_COEFF4_RSRVD1(v) \
+ (((v) << 26) & BM_ELCDIF_CSC_COEFF4_RSRVD1)
+#define BP_ELCDIF_CSC_COEFF4_C8 16
+#define BM_ELCDIF_CSC_COEFF4_C8 0x03FF0000
+#define BF_ELCDIF_CSC_COEFF4_C8(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_COEFF4_C8)
+#define BP_ELCDIF_CSC_COEFF4_RSRVD0 10
+#define BM_ELCDIF_CSC_COEFF4_RSRVD0 0x0000FC00
+#define BF_ELCDIF_CSC_COEFF4_RSRVD0(v) \
+ (((v) << 10) & BM_ELCDIF_CSC_COEFF4_RSRVD0)
+#define BP_ELCDIF_CSC_COEFF4_C7 0
+#define BM_ELCDIF_CSC_COEFF4_C7 0x000003FF
+#define BF_ELCDIF_CSC_COEFF4_C7(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_COEFF4_C7)
+
+#define HW_ELCDIF_CSC_OFFSET (0x00000160)
+
+#define BP_ELCDIF_CSC_OFFSET_RSRVD1 25
+#define BM_ELCDIF_CSC_OFFSET_RSRVD1 0xFE000000
+#define BF_ELCDIF_CSC_OFFSET_RSRVD1(v) \
+ (((v) << 25) & BM_ELCDIF_CSC_OFFSET_RSRVD1)
+#define BP_ELCDIF_CSC_OFFSET_CBCR_OFFSET 16
+#define BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
+#define BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET)
+#define BP_ELCDIF_CSC_OFFSET_RSRVD0 9
+#define BM_ELCDIF_CSC_OFFSET_RSRVD0 0x0000FE00
+#define BF_ELCDIF_CSC_OFFSET_RSRVD0(v) \
+ (((v) << 9) & BM_ELCDIF_CSC_OFFSET_RSRVD0)
+#define BP_ELCDIF_CSC_OFFSET_Y_OFFSET 0
+#define BM_ELCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
+#define BF_ELCDIF_CSC_OFFSET_Y_OFFSET(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_OFFSET_Y_OFFSET)
+
+#define HW_ELCDIF_CSC_LIMIT (0x00000170)
+
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MIN 24
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MIN(v) \
+ (((v) << 24) & BM_ELCDIF_CSC_LIMIT_CBCR_MIN)
+#define BP_ELCDIF_CSC_LIMIT_CBCR_MAX 16
+#define BM_ELCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
+#define BF_ELCDIF_CSC_LIMIT_CBCR_MAX(v) \
+ (((v) << 16) & BM_ELCDIF_CSC_LIMIT_CBCR_MAX)
+#define BP_ELCDIF_CSC_LIMIT_Y_MIN 8
+#define BM_ELCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
+#define BF_ELCDIF_CSC_LIMIT_Y_MIN(v) \
+ (((v) << 8) & BM_ELCDIF_CSC_LIMIT_Y_MIN)
+#define BP_ELCDIF_CSC_LIMIT_Y_MAX 0
+#define BM_ELCDIF_CSC_LIMIT_Y_MAX 0x000000FF
+#define BF_ELCDIF_CSC_LIMIT_Y_MAX(v) \
+ (((v) << 0) & BM_ELCDIF_CSC_LIMIT_Y_MAX)
+
+#define HW_ELCDIF_DATA (0x00000180)
+
+#define BP_ELCDIF_DATA_DATA_THREE 24
+#define BM_ELCDIF_DATA_DATA_THREE 0xFF000000
+#define BF_ELCDIF_DATA_DATA_THREE(v) \
+ (((v) << 24) & BM_ELCDIF_DATA_DATA_THREE)
+#define BP_ELCDIF_DATA_DATA_TWO 16
+#define BM_ELCDIF_DATA_DATA_TWO 0x00FF0000
+#define BF_ELCDIF_DATA_DATA_TWO(v) \
+ (((v) << 16) & BM_ELCDIF_DATA_DATA_TWO)
+#define BP_ELCDIF_DATA_DATA_ONE 8
+#define BM_ELCDIF_DATA_DATA_ONE 0x0000FF00
+#define BF_ELCDIF_DATA_DATA_ONE(v) \
+ (((v) << 8) & BM_ELCDIF_DATA_DATA_ONE)
+#define BP_ELCDIF_DATA_DATA_ZERO 0
+#define BM_ELCDIF_DATA_DATA_ZERO 0x000000FF
+#define BF_ELCDIF_DATA_DATA_ZERO(v) \
+ (((v) << 0) & BM_ELCDIF_DATA_DATA_ZERO)
+
+#define HW_ELCDIF_BM_ERROR_STAT (0x00000190)
+
+#define BP_ELCDIF_BM_ERROR_STAT_ADDR 0
+#define BM_ELCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF
+#define BF_ELCDIF_BM_ERROR_STAT_ADDR(v) (v)
+
+#define HW_ELCDIF_CRC_STAT (0x000001a0)
+
+#define BP_ELCDIF_CRC_STAT_CRC_VALUE 0
+#define BM_ELCDIF_CRC_STAT_CRC_VALUE 0xFFFFFFFF
+#define BF_ELCDIF_CRC_STAT_CRC_VALUE(v) (v)
+
+#define HW_ELCDIF_STAT (0x000001b0)
+
+#define BM_ELCDIF_STAT_PRESENT 0x80000000
+#define BM_ELCDIF_STAT_DMA_REQ 0x40000000
+#define BM_ELCDIF_STAT_LFIFO_FULL 0x20000000
+#define BM_ELCDIF_STAT_LFIFO_EMPTY 0x10000000
+#define BM_ELCDIF_STAT_TXFIFO_FULL 0x08000000
+#define BM_ELCDIF_STAT_TXFIFO_EMPTY 0x04000000
+#define BM_ELCDIF_STAT_BUSY 0x02000000
+#define BM_ELCDIF_STAT_DVI_CURRENT_FIELD 0x01000000
+#define BP_ELCDIF_STAT_RSRVD0 9
+#define BM_ELCDIF_STAT_RSRVD0 0x00FFFE00
+#define BF_ELCDIF_STAT_RSRVD0(v) \
+ (((v) << 9) & BM_ELCDIF_STAT_RSRVD0)
+#define BP_ELCDIF_STAT_LFIFO_COUNT 0
+#define BM_ELCDIF_STAT_LFIFO_COUNT 0x000001FF
+#define BF_ELCDIF_STAT_LFIFO_COUNT(v) \
+ (((v) << 0) & BM_ELCDIF_STAT_LFIFO_COUNT)
+
+#define HW_ELCDIF_VERSION (0x000001c0)
+
+#define BP_ELCDIF_VERSION_MAJOR 24
+#define BM_ELCDIF_VERSION_MAJOR 0xFF000000
+#define BF_ELCDIF_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_ELCDIF_VERSION_MAJOR)
+#define BP_ELCDIF_VERSION_MINOR 16
+#define BM_ELCDIF_VERSION_MINOR 0x00FF0000
+#define BF_ELCDIF_VERSION_MINOR(v) \
+ (((v) << 16) & BM_ELCDIF_VERSION_MINOR)
+#define BP_ELCDIF_VERSION_STEP 0
+#define BM_ELCDIF_VERSION_STEP 0x0000FFFF
+#define BF_ELCDIF_VERSION_STEP(v) \
+ (((v) << 0) & BM_ELCDIF_VERSION_STEP)
+
+#define HW_ELCDIF_DEBUG0 (0x000001d0)
+
+#define BM_ELCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000
+#define BM_ELCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000
+#define BM_ELCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000
+#define BM_ELCDIF_DEBUG0_DMACMDKICK 0x10000000
+#define BM_ELCDIF_DEBUG0_ENABLE 0x08000000
+#define BM_ELCDIF_DEBUG0_HSYNC 0x04000000
+#define BM_ELCDIF_DEBUG0_VSYNC 0x02000000
+#define BM_ELCDIF_DEBUG0_CUR_FRAME_TX 0x01000000
+#define BM_ELCDIF_DEBUG0_EMPTY_WORD 0x00800000
+#define BP_ELCDIF_DEBUG0_CUR_STATE 16
+#define BM_ELCDIF_DEBUG0_CUR_STATE 0x007F0000
+#define BF_ELCDIF_DEBUG0_CUR_STATE(v) \
+ (((v) << 16) & BM_ELCDIF_DEBUG0_CUR_STATE)
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B0_READY 0x00008000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B0_DONE 0x00004000
+#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B1_READY 0x00002000
+#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B1_DONE 0x00001000
+#define BP_ELCDIF_DEBUG0_CUR_REQ_STATE 10
+#define BM_ELCDIF_DEBUG0_CUR_REQ_STATE 0x00000C00
+#define BF_ELCDIF_DEBUG0_CUR_REQ_STATE(v) \
+ (((v) << 10) & BM_ELCDIF_DEBUG0_CUR_REQ_STATE)
+#define BM_ELCDIF_DEBUG0_MST_AVALID 0x00000200
+#define BP_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS 4
+#define BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS 0x000001F0
+#define BF_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS(v) \
+ (((v) << 4) & BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS)
+#define BP_ELCDIF_DEBUG0_MST_WORDS 0
+#define BM_ELCDIF_DEBUG0_MST_WORDS 0x0000000F
+#define BF_ELCDIF_DEBUG0_MST_WORDS(v) \
+ (((v) << 0) & BM_ELCDIF_DEBUG0_MST_WORDS)
+
+#define HW_ELCDIF_DEBUG1 (0x000001e0)
+
+#define BP_ELCDIF_DEBUG1_H_DATA_COUNT 16
+#define BM_ELCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000
+#define BF_ELCDIF_DEBUG1_H_DATA_COUNT(v) \
+ (((v) << 16) & BM_ELCDIF_DEBUG1_H_DATA_COUNT)
+#define BP_ELCDIF_DEBUG1_V_DATA_COUNT 0
+#define BM_ELCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF
+#define BF_ELCDIF_DEBUG1_V_DATA_COUNT(v) \
+ (((v) << 0) & BM_ELCDIF_DEBUG1_V_DATA_COUNT)
+
+#define HW_ELCDIF_DEBUG2 (0x000001f0)
+
+#define BP_ELCDIF_DEBUG2_MST_ADDRESS 0
+#define BM_ELCDIF_DEBUG2_MST_ADDRESS 0xFFFFFFFF
+#define BF_ELCDIF_DEBUG2_MST_ADDRESS(v) (v)
+#endif /* __ELCDIF_REGS_INCLUDED_ */
diff --git a/drivers/video/mxc/epdc_regs.h b/drivers/video/mxc/epdc_regs.h
new file mode 100644
index 000000000000..1d0635b928ad
--- /dev/null
+++ b/drivers/video/mxc/epdc_regs.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __EPDC_REGS_INCLUDED__
+#define __EPDC_REGS_INCLUDED__
+
+extern void __iomem *epdc_base;
+
+//*************************************
+// Register addresses
+//*************************************
+
+#define EPDC_CTRL (epdc_base + 0x000)
+#define EPDC_CTRL_SET (epdc_base + 0x004)
+#define EPDC_CTRL_CLEAR (epdc_base + 0x008)
+#define EPDC_CTRL_TOGGLE (epdc_base + 0x00C)
+#define EPDC_WVADDR (epdc_base + 0x020)
+#define EPDC_WB_ADDR (epdc_base + 0x030)
+#define EPDC_RES (epdc_base + 0x040)
+#define EPDC_FORMAT (epdc_base + 0x050)
+#define EPDC_FORMAT_SET (epdc_base + 0x054)
+#define EPDC_FORMAT_CLEAR (epdc_base + 0x058)
+#define EPDC_FORMAT_TOGGLE (epdc_base + 0x05C)
+#define EPDC_FIFOCTRL (epdc_base + 0x0A0)
+#define EPDC_FIFOCTRL_SET (epdc_base + 0x0A4)
+#define EPDC_FIFOCTRL_CLEAR (epdc_base + 0x0A8)
+#define EPDC_FIFOCTRL_TOGGLE (epdc_base + 0x0AC)
+#define EPDC_UPD_ADDR (epdc_base + 0x100)
+#define EPDC_UPD_CORD (epdc_base + 0x120)
+#define EPDC_UPD_SIZE (epdc_base + 0x140)
+#define EPDC_UPD_CTRL (epdc_base + 0x160)
+#define EPDC_UPD_FIXED (epdc_base + 0x180)
+#define EPDC_TEMP (epdc_base + 0x1A0)
+#define EPDC_TCE_CTRL (epdc_base + 0x200)
+#define EPDC_TCE_SDCFG (epdc_base + 0x220)
+#define EPDC_TCE_GDCFG (epdc_base + 0x240)
+#define EPDC_TCE_HSCAN1 (epdc_base + 0x260)
+#define EPDC_TCE_HSCAN2 (epdc_base + 0x280)
+#define EPDC_TCE_VSCAN (epdc_base + 0x2A0)
+#define EPDC_TCE_OE (epdc_base + 0x2C0)
+#define EPDC_TCE_POLARITY (epdc_base + 0x2E0)
+#define EPDC_TCE_TIMING1 (epdc_base + 0x300)
+#define EPDC_TCE_TIMING2 (epdc_base + 0x310)
+#define EPDC_TCE_TIMING3 (epdc_base + 0x320)
+#define EPDC_IRQ_MASK (epdc_base + 0x400)
+#define EPDC_IRQ_MASK_SET (epdc_base + 0x404)
+#define EPDC_IRQ_MASK_CLEAR (epdc_base + 0x408)
+#define EPDC_IRQ_MASK_TOGGLE (epdc_base + 0x40C)
+#define EPDC_IRQ (epdc_base + 0x420)
+#define EPDC_IRQ_SET (epdc_base + 0x424)
+#define EPDC_IRQ_CLEAR (epdc_base + 0x428)
+#define EPDC_IRQ_TOGGLE (epdc_base + 0x42C)
+#define EPDC_STATUS_LUTS (epdc_base + 0x440)
+#define EPDC_STATUS_LUTS_SET (epdc_base + 0x444)
+#define EPDC_STATUS_LUTS_CLEAR (epdc_base + 0x448)
+#define EPDC_STATUS_LUTS_TOGGLE (epdc_base + 0x44C)
+#define EPDC_STATUS_NEXTLUT (epdc_base + 0x460)
+#define EPDC_STATUS_COL (epdc_base + 0x480)
+#define EPDC_STATUS (epdc_base + 0x4A0)
+#define EPDC_STATUS_SET (epdc_base + 0x4A4)
+#define EPDC_STATUS_CLEAR (epdc_base + 0x4A8)
+#define EPDC_STATUS_TOGGLE (epdc_base + 0x4AC)
+#define EPDC_DEBUG (epdc_base + 0x500)
+#define EPDC_DEBUG_LUT0 (epdc_base + 0x540)
+#define EPDC_DEBUG_LUT1 (epdc_base + 0x550)
+#define EPDC_DEBUG_LUT2 (epdc_base + 0x560)
+#define EPDC_DEBUG_LUT3 (epdc_base + 0x570)
+#define EPDC_DEBUG_LUT4 (epdc_base + 0x580)
+#define EPDC_DEBUG_LUT5 (epdc_base + 0x590)
+#define EPDC_DEBUG_LUT6 (epdc_base + 0x5A0)
+#define EPDC_DEBUG_LUT7 (epdc_base + 0x5B0)
+#define EPDC_DEBUG_LUT8 (epdc_base + 0x5C0)
+#define EPDC_DEBUG_LUT9 (epdc_base + 0x5D0)
+#define EPDC_DEBUG_LUT10 (epdc_base + 0x5E0)
+#define EPDC_DEBUG_LUT11 (epdc_base + 0x5F0)
+#define EPDC_DEBUG_LUT12 (epdc_base + 0x600)
+#define EPDC_DEBUG_LUT13 (epdc_base + 0x610)
+#define EPDC_DEBUG_LUT14 (epdc_base + 0x620)
+#define EPDC_DEBUG_LUT15 (epdc_base + 0x630)
+#define EPDC_GPIO (epdc_base + 0x700)
+#define EPDC_VERSION (epdc_base + 0x7F0)
+
+/*
+ * Register field definitions
+ */
+
+enum {
+/* EPDC_CTRL field values */
+ EPDC_CTRL_SFTRST = 0x80000000,
+ EPDC_CTRL_CLKGATE = 0x40000000,
+ EPDC_CTRL_SRAM_POWERDOWN = 0x100,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
+ EPDC_CTRL_BURST_LEN_8_8 = 0x1,
+ EPDC_CTRL_BURST_LEN_8_16 = 0,
+
+/* EPDC_RES field values */
+ EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
+ EPDC_RES_VERTICAL_OFFSET = 16,
+ EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
+ EPDC_RES_HORIZONTAL_OFFSET = 0,
+
+/* EPDC_FORMAT field values */
+ EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
+
+/* EPDC_FIFOCTRL field values */
+ EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
+
+/* EPDC_UPD_CORD field values */
+ EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
+ EPDC_UPD_CORD_YCORD_OFFSET = 16,
+ EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
+ EPDC_UPD_CORD_XCORD_OFFSET = 0,
+
+/* EPDC_UPD_SIZE field values */
+ EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
+ EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
+ EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
+ EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
+
+/* EPDC_UPD_CTRL field values */
+ EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
+ EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000,
+ EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
+ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
+ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+ EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
+
+/* EPDC_UPD_FIXED field values */
+ EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
+ EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
+ EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
+ EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
+ EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
+ EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
+
+/* EPDC_TCE_CTRL field values */
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
+ EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
+ EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
+ EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
+ EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
+ EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
+ EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
+ EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
+ EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
+ EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
+ EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
+ EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
+
+/* EPDC_TCE_SDCFG field values */
+ EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
+ EPDC_TCE_SDCFG_SDSHR = 0x100000,
+ EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
+ EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
+ EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
+ EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
+ EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
+
+/* EPDC_TCE_GDCFG field values */
+ EPDC_TCE_SDCFG_GDRL = 0x10,
+ EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
+ EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
+ EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
+
+/* EPDC_TCE_HSCAN1 field values */
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
+ EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
+ EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_HSCAN2 field values */
+ EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
+ EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
+ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
+ EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
+
+/* EPDC_TCE_VSCAN field values */
+ EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
+ EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
+ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
+ EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
+ EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
+ EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_OE field values */
+ EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
+ EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
+ EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
+ EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
+ EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
+ EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
+ EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
+ EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
+
+/* EPDC_TCE_POLARITY field values */
+ EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
+ EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
+ EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
+ EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
+ EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
+
+/* EPDC_TCE_TIMING1 field values */
+ EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
+ EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
+
+/* EPDC_TCE_TIMING2 field values */
+ EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
+ EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
+ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
+ EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
+
+/* EPDC_TCE_TIMING3 field values */
+ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
+ EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
+
+/* EPDC_IRQ_MASK/EPDC_IRQ field values */
+ EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
+ EPDC_IRQ_LUT_COL_IRQ = 0x20000,
+ EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
+ EPDC_IRQ_FRAME_END_IRQ = 0x80000,
+ EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
+ EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+
+/* EPDC_STATUS_NEXTLUT field values */
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xF,
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
+
+/* EPDC_STATUS field values */
+ EPDC_STATUS_LUTS_UNDERRUN = 0x4,
+ EPDC_STATUS_LUTS_BUSY = 0x2,
+ EPDC_STATUS_WB_BUSY = 0x1,
+
+/* EPDC_DEBUG field values */
+ EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
+ EPDC_DEBUG_COLLISION_OFF = 0x1,
+
+/* EPDC_GPIO field values */
+ EPDC_GPIO_PWRCOM = 0x40,
+ EPDC_GPIO_PWRCTRL_MASK = 0x3C,
+ EPDC_GPIO_PWRCTRL_OFFSET = 2,
+ EPDC_GPIO_BDR_MASK = 0x3,
+ EPDC_GPIO_BDR_OFFSET = 0,
+};
+
+#endif /* __EPDC_REGS_INCLUDED__ */
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
new file mode 100644
index 000000000000..fe58146df3cb
--- /dev/null
+++ b/drivers/video/mxc/ldb.c
@@ -0,0 +1,1448 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file mxc_ldb.c
+ *
+ * @brief This file contains the LDB driver device interface and fops
+ * functions.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/ldb.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <mach/hardware.h>
+
+#define LDB_BGREF_RMODE_MASK 0x00008000
+#define LDB_BGREF_RMODE_INT 0x00008000
+#define LDB_BGREF_RMODE_EXT 0x0
+
+#define LDB_DI1_VS_POL_MASK 0x00000400
+#define LDB_DI1_VS_POL_ACT_LOW 0x00000400
+#define LDB_DI1_VS_POL_ACT_HIGH 0x0
+#define LDB_DI0_VS_POL_MASK 0x00000200
+#define LDB_DI0_VS_POL_ACT_LOW 0x00000200
+#define LDB_DI0_VS_POL_ACT_HIGH 0x0
+
+#define LDB_BIT_MAP_CH1_MASK 0x00000100
+#define LDB_BIT_MAP_CH1_JEIDA 0x00000100
+#define LDB_BIT_MAP_CH1_SPWG 0x0
+#define LDB_BIT_MAP_CH0_MASK 0x00000040
+#define LDB_BIT_MAP_CH0_JEIDA 0x00000040
+#define LDB_BIT_MAP_CH0_SPWG 0x0
+
+#define LDB_DATA_WIDTH_CH1_MASK 0x00000080
+#define LDB_DATA_WIDTH_CH1_24 0x00000080
+#define LDB_DATA_WIDTH_CH1_18 0x0
+#define LDB_DATA_WIDTH_CH0_MASK 0x00000020
+#define LDB_DATA_WIDTH_CH0_24 0x00000020
+#define LDB_DATA_WIDTH_CH0_18 0x0
+
+#define LDB_CH1_MODE_MASK 0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI1 0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI0 0x00000004
+#define LDB_CH1_MODE_DISABLE 0x0
+#define LDB_CH0_MODE_MASK 0x00000003
+#define LDB_CH0_MODE_EN_TO_DI1 0x00000003
+#define LDB_CH0_MODE_EN_TO_DI0 0x00000001
+#define LDB_CH0_MODE_DISABLE 0x0
+
+#define LDB_SPLIT_MODE_EN 0x00000010
+
+enum ldb_chan_mode_opt {
+ LDB_SIN_DI0 = 0,
+ LDB_SIN_DI1 = 1,
+ LDB_SEP = 2,
+ LDB_DUL_DI0 = 3,
+ LDB_DUL_DI1 = 4,
+ LDB_SPL_DI0 = 5,
+ LDB_SPL_DI1 = 6,
+};
+
+static struct ldb_data {
+ struct fb_info *fbi[2];
+ bool ch_working[2];
+ uint32_t chan_mode_opt;
+ uint32_t chan_bit_map[2];
+ uint32_t bgref_rmode;
+ uint32_t base_addr;
+ uint32_t *control_reg;
+ struct clk *ldb_di_clk[2];
+ struct regulator *lvds_bg_reg;
+ struct list_head modelist;
+} ldb;
+
+static struct device *g_ldb_dev;
+static u32 *ldb_reg;
+static bool enabled[2];
+static int g_chan_mode_opt;
+static int g_chan_bit_map[2];
+static bool g_enable_ldb;
+static bool g_boot_cmd;
+
+DEFINE_SPINLOCK(ldb_lock);
+
+struct fb_videomode mxcfb_ldb_modedb[] = {
+ {
+ "1080P60", 60, 1920, 1080, 7692,
+ 100, 40,
+ 30, 3,
+ 10, 2,
+ FB_SYNC_EXT,
+ FB_VMODE_NONINTERLACED,
+ 0,},
+ {
+ "XGA", 60, 1024, 768, 15385,
+ 220, 40,
+ 21, 7,
+ 60, 10,
+ FB_SYNC_EXT,
+ FB_VMODE_NONINTERLACED,
+ 0,},
+};
+int mxcfb_ldb_modedb_sz = ARRAY_SIZE(mxcfb_ldb_modedb);
+
+static int bits_per_pixel(int pixel_fmt)
+{
+ switch (pixel_fmt) {
+ case IPU_PIX_FMT_BGR24:
+ case IPU_PIX_FMT_RGB24:
+ return 24;
+ break;
+ case IPU_PIX_FMT_BGR666:
+ case IPU_PIX_FMT_RGB666:
+ case IPU_PIX_FMT_LVDS666:
+ return 18;
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int valid_mode(int pixel_fmt)
+{
+ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
+ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
+ (pixel_fmt == IPU_PIX_FMT_LVDS666) ||
+ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
+ (pixel_fmt == IPU_PIX_FMT_BGR666));
+}
+
+static void ldb_disable(int ipu_di)
+{
+ uint32_t reg;
+ int i = 0;
+
+ spin_lock(&ldb_lock);
+
+ switch (ldb.chan_mode_opt) {
+ case LDB_SIN_DI0:
+ if (ipu_di != 0 || !ldb.ch_working[0] || !enabled[0]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_DISABLE,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_disable(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[0]);
+
+ ldb.ch_working[0] = false;
+ enabled[0] = false;
+ break;
+ case LDB_SIN_DI1:
+ if (ipu_di != 1 || !ldb.ch_working[1] || !enabled[1]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_DISABLE,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_disable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ ldb.ch_working[1] = false;
+ enabled[1] = false;
+ break;
+ case LDB_SPL_DI0:
+ case LDB_DUL_DI0:
+ if (ipu_di != 0 || !enabled[0]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ for (i = 0; i < 2; i++) {
+ if (ldb.ch_working[i]) {
+ reg = __raw_readl(ldb.control_reg);
+ if (i == 0)
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_DISABLE,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH1_MODE_DISABLE,
+ ldb.control_reg);
+
+ if (ldb.chan_mode_opt == LDB_SPL_DI0) {
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+ }
+
+ ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+ "ldb_di1_clk" :
+ "ldb_di0_clk");
+ clk_disable(ldb.ldb_di_clk[i]);
+ clk_put(ldb.ldb_di_clk[i]);
+
+ ldb.ch_working[i] = false;
+ }
+ }
+ enabled[0] = false;
+ break;
+ case LDB_SPL_DI1:
+ case LDB_DUL_DI1:
+ if (ipu_di != 1 || !enabled[1]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ for (i = 0; i < 2; i++) {
+ if (ldb.ch_working[i]) {
+ reg = __raw_readl(ldb.control_reg);
+ if (i == 0)
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_DISABLE,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH1_MODE_DISABLE,
+ ldb.control_reg);
+
+ if (ldb.chan_mode_opt == LDB_SPL_DI1) {
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel(reg & ~LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+ }
+
+ ldb.ldb_di_clk[i] = clk_get(NULL, i ?
+ "ldb_di1_clk" :
+ "ldb_di0_clk");
+ clk_disable(ldb.ldb_di_clk[i]);
+ clk_put(ldb.ldb_di_clk[i]);
+
+ ldb.ch_working[i] = false;
+ }
+ }
+ enabled[1] = false;
+ break;
+ case LDB_SEP:
+ if (ldb.ch_working[ipu_di] && enabled[ipu_di]) {
+ reg = __raw_readl(ldb.control_reg);
+ if (ipu_di == 0)
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_DISABLE,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_DISABLE,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[ipu_di] = clk_get(NULL, ipu_di ?
+ "ldb_di1_clk" :
+ "ldb_di0_clk");
+ clk_disable(ldb.ldb_di_clk[ipu_di]);
+ clk_put(ldb.ldb_di_clk[ipu_di]);
+
+ ldb.ch_working[ipu_di] = false;
+ enabled[ipu_di] = false;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&ldb_lock);
+ return;
+}
+
+static void ldb_enable(int ipu_di)
+{
+ uint32_t reg;
+
+ spin_lock(&ldb_lock);
+
+ reg = __raw_readl(ldb.control_reg);
+ switch (ldb.chan_mode_opt) {
+ case LDB_SIN_DI0:
+ if (ldb.ch_working[0] || ipu_di != 0 || enabled[0]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[0]);
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+ ldb.ch_working[0] = true;
+ enabled[0] = true;
+ break;
+ case LDB_SIN_DI1:
+ if (ldb.ch_working[1] || ipu_di != 1 || enabled[1]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[1]);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+ ldb.ch_working[1] = true;
+ enabled[1] = true;
+ break;
+ case LDB_SEP:
+ if (ldb.ch_working[ipu_di] || enabled[ipu_di]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ if (ipu_di == 0) {
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[0]);
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI0,
+ ldb.control_reg);
+ ldb.ch_working[0] = true;
+ } else {
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[1]);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ ldb.ch_working[1] = true;
+ }
+ enabled[ipu_di] = true;
+ break;
+ case LDB_DUL_DI0:
+ case LDB_SPL_DI0:
+ if (ipu_di != 0 || enabled[0])
+ return;
+ else
+ goto proc;
+ case LDB_DUL_DI1:
+ case LDB_SPL_DI1:
+ if (ipu_di != 1 || enabled[1])
+ return;
+proc:
+ if (ldb.ch_working[0] || ldb.ch_working[1]) {
+ spin_unlock(&ldb_lock);
+ return;
+ }
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ if (ldb.chan_mode_opt == LDB_DUL_DI0 ||
+ ldb.chan_mode_opt == LDB_SPL_DI0) {
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI0,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI0,
+ ldb.control_reg);
+ } else if (ldb.chan_mode_opt == LDB_DUL_DI1 ||
+ ldb.chan_mode_opt == LDB_SPL_DI1) {
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ }
+ if (ldb.chan_mode_opt == LDB_SPL_DI0 ||
+ ldb.chan_mode_opt == LDB_SPL_DI1) {
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel(reg | LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+ }
+ ldb.ch_working[0] = true;
+ ldb.ch_working[1] = true;
+ enabled[ipu_di] = true;
+ break;
+ default:
+ break;
+ }
+ spin_unlock(&ldb_lock);
+ return;
+}
+
+int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+ struct fb_event *event = v;
+ struct fb_info *fbi = event->info;
+ mm_segment_t old_fs;
+ int ipu_di = 0;
+
+ switch (val) {
+ case FB_EVENT_BLANK:
+ if (ldb.fbi[0] != fbi && ldb.fbi[1] != fbi)
+ return 0;
+
+ if (fbi->fbops->fb_ioctl) {
+ old_fs = get_fs();
+ set_fs(KERNEL_DS);
+ fbi->fbops->fb_ioctl(fbi,
+ MXCFB_GET_FB_IPU_DI,
+ (unsigned long)&ipu_di);
+ set_fs(old_fs);
+ } else
+ return 0;
+
+ if (*((int *)event->data) == FB_BLANK_UNBLANK)
+ ldb_enable(ipu_di);
+ else
+ ldb_disable(ipu_di);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static struct notifier_block nb = {
+ .notifier_call = ldb_fb_event,
+};
+
+static int mxc_ldb_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int ret = 0;
+ uint32_t reg;
+
+ switch (cmd) {
+ case LDB_BGREF_RMODE:
+ {
+ ldb_bgref_parm parm;
+
+ if (copy_from_user(&parm, (ldb_bgref_parm *) arg,
+ sizeof(ldb_bgref_parm)))
+ return -EFAULT;
+
+ spin_lock(&ldb_lock);
+ reg = __raw_readl(ldb.control_reg);
+ if (parm.bgref_mode == LDB_EXT_REF)
+ __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+ LDB_BGREF_RMODE_EXT, ldb.control_reg);
+ else if (parm.bgref_mode == LDB_INT_REF)
+ __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+ LDB_BGREF_RMODE_INT, ldb.control_reg);
+ spin_unlock(&ldb_lock);
+ break;
+ }
+ case LDB_VSYNC_POL:
+ {
+ ldb_vsync_parm parm;
+
+ if (copy_from_user(&parm, (ldb_vsync_parm *) arg,
+ sizeof(ldb_vsync_parm)))
+ return -EFAULT;
+
+ spin_lock(&ldb_lock);
+ reg = __raw_readl(ldb.control_reg);
+ if (parm.vsync_mode == LDB_VS_ACT_H) {
+ if (parm.di == 0)
+ __raw_writel((reg &
+ ~LDB_DI0_VS_POL_MASK) |
+ LDB_DI0_VS_POL_ACT_HIGH,
+ ldb.control_reg);
+ else
+ __raw_writel((reg &
+ ~LDB_DI1_VS_POL_MASK) |
+ LDB_DI1_VS_POL_ACT_HIGH,
+ ldb.control_reg);
+ } else if (parm.vsync_mode == LDB_VS_ACT_L) {
+ if (parm.di == 0)
+ __raw_writel((reg &
+ ~LDB_DI0_VS_POL_MASK) |
+ LDB_DI0_VS_POL_ACT_LOW,
+ ldb.control_reg);
+ else
+ __raw_writel((reg &
+ ~LDB_DI1_VS_POL_MASK) |
+ LDB_DI1_VS_POL_ACT_LOW,
+ ldb.control_reg);
+
+ }
+ spin_unlock(&ldb_lock);
+ break;
+ }
+ case LDB_BIT_MAP:
+ {
+ ldb_bitmap_parm parm;
+
+ if (copy_from_user(&parm, (ldb_bitmap_parm *) arg,
+ sizeof(ldb_bitmap_parm)))
+ return -EFAULT;
+
+ spin_lock(&ldb_lock);
+ reg = __raw_readl(ldb.control_reg);
+ if (parm.bitmap_mode == LDB_BIT_MAP_SPWG) {
+ if (parm.channel == 0)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH1_SPWG,
+ ldb.control_reg);
+ } else if (parm.bitmap_mode == LDB_BIT_MAP_JEIDA) {
+ if (parm.channel == 0)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_JEIDA,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH1_JEIDA,
+ ldb.control_reg);
+ }
+ spin_unlock(&ldb_lock);
+ break;
+ }
+ case LDB_DATA_WIDTH:
+ {
+ ldb_data_width_parm parm;
+
+ if (copy_from_user(&parm, (ldb_data_width_parm *) arg,
+ sizeof(ldb_data_width_parm)))
+ return -EFAULT;
+
+ spin_lock(&ldb_lock);
+ reg = __raw_readl(ldb.control_reg);
+ if (parm.data_width == 24) {
+ if (parm.channel == 0)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_24,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH1_24,
+ ldb.control_reg);
+ } else if (parm.data_width == 18) {
+ if (parm.channel == 0)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_18,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH1_18,
+ ldb.control_reg);
+ }
+ spin_unlock(&ldb_lock);
+ break;
+ }
+ case LDB_CHAN_MODE:
+ {
+ ldb_chan_mode_parm parm;
+ struct clk *pll4_clk;
+ unsigned long pll4_rate = 0;
+
+ if (copy_from_user(&parm, (ldb_chan_mode_parm *) arg,
+ sizeof(ldb_chan_mode_parm)))
+ return -EFAULT;
+
+ spin_lock(&ldb_lock);
+
+ /* TODO:Set the correct pll4 rate for all situations */
+ pll4_clk = clk_get(NULL, "pll4");
+ pll4_rate = clk_get_rate(pll4_clk);
+ pll4_rate = 455000000;
+ clk_set_rate(pll4_clk, pll4_rate);
+ clk_put(pll4_clk);
+
+ reg = __raw_readl(ldb.control_reg);
+ switch (parm.channel_mode) {
+ case LDB_CHAN_MODE_SIN:
+ if (parm.di == 0) {
+ ldb.chan_mode_opt = LDB_SIN_DI0;
+
+ ldb.ldb_di_clk[0] = clk_get(NULL,
+ "ldb_di0_clk");
+ clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+ clk_put(ldb.ldb_di_clk[0]);
+
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI0,
+ ldb.control_reg);
+ } else {
+ ldb.chan_mode_opt = LDB_SIN_DI1;
+
+ ldb.ldb_di_clk[1] = clk_get(NULL,
+ "ldb_di1_clk");
+ clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ }
+ break;
+ case LDB_CHAN_MODE_SEP:
+ ldb.chan_mode_opt = LDB_SEP;
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7);
+ clk_put(ldb.ldb_di_clk[0]);
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI0 |
+ LDB_CH1_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ break;
+ case LDB_CHAN_MODE_DUL:
+ case LDB_CHAN_MODE_SPL:
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ if (parm.di == 0) {
+ if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+ ldb.chan_mode_opt = LDB_DUL_DI0;
+ clk_set_rate(ldb.ldb_di_clk[0],
+ pll4_rate/7);
+ } else {
+ ldb.chan_mode_opt = LDB_SPL_DI0;
+ clk_set_rate(ldb.ldb_di_clk[0],
+ 2*pll4_rate/7);
+ clk_set_rate(ldb.ldb_di_clk[1],
+ 2*pll4_rate/7);
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel(reg | LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI0 |
+ LDB_CH1_MODE_EN_TO_DI0,
+ ldb.control_reg);
+ } else {
+ if (parm.channel_mode == LDB_CHAN_MODE_DUL) {
+ ldb.chan_mode_opt = LDB_DUL_DI1;
+ clk_set_rate(ldb.ldb_di_clk[1],
+ pll4_rate/7);
+ } else {
+ ldb.chan_mode_opt = LDB_SPL_DI1;
+ clk_set_rate(ldb.ldb_di_clk[0],
+ 2*pll4_rate/7);
+ clk_set_rate(ldb.ldb_di_clk[1],
+ 2*pll4_rate/7);
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel(reg | LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI1 |
+ LDB_CH1_MODE_EN_TO_DI1,
+ ldb.control_reg);
+ }
+ clk_put(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[1]);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ spin_unlock(&ldb_lock);
+ break;
+ }
+ case LDB_ENABLE:
+ {
+ int ipu_di;
+
+ if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+ return -EFAULT;
+
+ ldb_enable(ipu_di);
+ break;
+ }
+ case LDB_DISABLE:
+ {
+ int ipu_di;
+
+ if (copy_from_user(&ipu_di, (int *) arg, sizeof(int)))
+ return -EFAULT;
+
+ ldb_disable(ipu_di);
+ break;
+ }
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int mxc_ldb_open(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static int mxc_ldb_release(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static int mxc_ldb_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ return 0;
+}
+
+static const struct file_operations mxc_ldb_fops = {
+ .owner = THIS_MODULE,
+ .open = mxc_ldb_open,
+ .mmap = mxc_ldb_mmap,
+ .release = mxc_ldb_release,
+ .ioctl = mxc_ldb_ioctl
+};
+
+/*!
+ * This function is called by the driver framework to initialize the LDB
+ * device.
+ *
+ * @param dev The device structure for the LDB passed in by the
+ * driver framework.
+ *
+ * @return Returns 0 on success or negative error code on error
+ */
+static int ldb_probe(struct platform_device *pdev)
+{
+ int ret = 0, i, ipu_di, ipu_di_pix_fmt[2];
+ bool primary = false, find_1080p = false;
+ struct resource *res;
+ struct ldb_platform_data *plat_data = pdev->dev.platform_data;
+ mm_segment_t old_fs;
+ struct clk *ldb_clk_parent;
+ unsigned long ldb_clk_prate = 455000000;
+ struct fb_var_screeninfo *var[2];
+ uint32_t reg;
+ struct device *temp;
+ int mxc_ldb_major;
+ const struct fb_videomode *mode;
+ struct class *mxc_ldb_class;
+
+ if (g_enable_ldb == false)
+ return -ENODEV;
+
+ spin_lock_init(&ldb_lock);
+
+ g_ldb_dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (IS_ERR(res))
+ return -ENODEV;
+
+ memset(&ldb, 0, sizeof(struct ldb_data));
+ enabled[0] = enabled[1] = false;
+ var[0] = var[1] = NULL;
+ if (g_boot_cmd) {
+ ldb.chan_mode_opt = g_chan_mode_opt;
+ ldb.chan_bit_map[0] = g_chan_bit_map[0];
+ ldb.chan_bit_map[1] = g_chan_bit_map[1];
+ }
+
+ ldb.base_addr = res->start;
+ ldb_reg = ioremap(ldb.base_addr, res->end - res->start + 1);
+ ldb.control_reg = ldb_reg + 2;
+
+ INIT_LIST_HEAD(&ldb.modelist);
+ for (i = 0; i < mxcfb_ldb_modedb_sz; i++)
+ fb_add_videomode(&mxcfb_ldb_modedb[i], &ldb.modelist);
+
+ for (i = 0; i < num_registered_fb; i++) {
+ if ((registered_fb[i]->var.sync & FB_SYNC_EXT) &&
+ (registered_fb[i]->var.vmode == FB_VMODE_NONINTERLACED)) {
+ ldb.fbi[i] = registered_fb[i];
+
+ mode = fb_match_mode(&ldb.fbi[i]->var, &ldb.modelist);
+ if (mode) {
+ dev_dbg(g_ldb_dev, "fb mode found\n");
+ fb_videomode_to_var(&ldb.fbi[i]->var, mode);
+ } else {
+ dev_warn(g_ldb_dev,
+ "can't find video mode\n");
+ goto err0;
+ }
+ /*
+ * Default ldb mode:
+ * 1080p: DI0 split, SPWG
+ * others: single, SPWG
+ */
+ if (g_boot_cmd == false) {
+ ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+ if (fb_mode_is_equal(mode, &mxcfb_ldb_modedb[0])) {
+ ldb.chan_mode_opt = LDB_SPL_DI0;
+ ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+ ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+ find_1080p = true;
+ dev_warn(g_ldb_dev, "default split mode\n");
+ } else if (!find_1080p) {
+ if (strcmp(ldb.fbi[i]->fix.id,
+ "DISP3 BG") == 0) {
+ ldb.chan_mode_opt = LDB_SIN_DI0;
+ ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+ dev_warn(g_ldb_dev,
+ "default di0 single mode\n");
+ } else if (strcmp(ldb.fbi[i]->fix.id,
+ "DISP3 BG - DI1") == 0) {
+ ldb.chan_mode_opt = LDB_SIN_DI1;
+ ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+ dev_warn(g_ldb_dev,
+ "default di1 single mode\n");
+ }
+ }
+ }
+
+ acquire_console_sem();
+ fb_blank(ldb.fbi[i], FB_BLANK_POWERDOWN);
+ release_console_sem();
+
+ if (i == 0)
+ primary = true;
+
+ if (ldb.fbi[1] != NULL)
+ break;
+ }
+ }
+
+ /*
+ * We cannot support two LVDS panel with different pixel clock rates
+ * except that one's pixel clock rate is two times of the others'.
+ */
+ if (ldb.fbi[1] && ldb.fbi[0] != NULL) {
+ if (ldb.fbi[0]->var.pixclock != ldb.fbi[1]->var.pixclock &&
+ ldb.fbi[0]->var.pixclock != 2 * ldb.fbi[1]->var.pixclock &&
+ ldb.fbi[1]->var.pixclock != 2 * ldb.fbi[0]->var.pixclock)
+ return -EINVAL;
+ }
+
+ ldb.bgref_rmode = plat_data->ext_ref;
+ ldb.lvds_bg_reg = regulator_get(&pdev->dev, plat_data->lvds_bg_reg);
+ if (!IS_ERR(ldb.lvds_bg_reg)) {
+ regulator_set_voltage(ldb.lvds_bg_reg, 2500000, 2500000);
+ regulator_enable(ldb.lvds_bg_reg);
+ }
+
+ for (i = 0; i < 2; i++) {
+ if (ldb.fbi[i] != NULL) {
+ if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG") == 0)
+ ipu_di = 0;
+ else if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG - DI1")
+ == 0)
+ ipu_di = 1;
+ else {
+ dev_err(g_ldb_dev, "Wrong framebuffer\n");
+ goto err0;
+ }
+
+ var[ipu_di] = &ldb.fbi[i]->var;
+ if (ldb.fbi[i]->fbops->fb_ioctl) {
+ old_fs = get_fs();
+ set_fs(KERNEL_DS);
+ ldb.fbi[i]->fbops->fb_ioctl(ldb.fbi[i],
+ MXCFB_GET_DIFMT,
+ (unsigned long)&(ipu_di_pix_fmt[ipu_di]));
+ set_fs(old_fs);
+ } else {
+ dev_err(g_ldb_dev, "Can't get framebuffer "
+ "information\n");
+ goto err0;
+ }
+
+ if (!valid_mode(ipu_di_pix_fmt[ipu_di])) {
+ dev_err(g_ldb_dev, "Unsupport pixel format "
+ "for ldb input\n");
+ goto err0;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (var[ipu_di]->sync & FB_SYNC_VERT_HIGH_ACT) {
+ if (ipu_di == 0)
+ __raw_writel((reg &
+ ~LDB_DI0_VS_POL_MASK) |
+ LDB_DI0_VS_POL_ACT_HIGH,
+ ldb.control_reg);
+ else
+ __raw_writel((reg &
+ ~LDB_DI1_VS_POL_MASK) |
+ LDB_DI1_VS_POL_ACT_HIGH,
+ ldb.control_reg);
+ } else {
+ if (ipu_di == 0)
+ __raw_writel((reg &
+ ~LDB_DI0_VS_POL_MASK) |
+ LDB_DI0_VS_POL_ACT_LOW,
+ ldb.control_reg);
+ else
+ __raw_writel((reg &
+ ~LDB_DI1_VS_POL_MASK) |
+ LDB_DI1_VS_POL_ACT_LOW,
+ ldb.control_reg);
+ }
+
+ /* TODO:Set the correct pll4 rate for all situations */
+ if (ipu_di == 1) {
+ ldb.ldb_di_clk[1] =
+ clk_get(&pdev->dev, "ldb_di1_clk");
+ ldb_clk_parent =
+ clk_get_parent(ldb.ldb_di_clk[1]);
+ clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+ clk_put(ldb.ldb_di_clk[1]);
+ } else {
+ ldb.ldb_di_clk[0] =
+ clk_get(&pdev->dev, "ldb_di0_clk");
+ ldb_clk_parent =
+ clk_get_parent(ldb.ldb_di_clk[0]);
+ clk_set_rate(ldb_clk_parent, ldb_clk_prate);
+ clk_put(ldb.ldb_di_clk[0]);
+ }
+ }
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.bgref_rmode == LDB_EXT_REF)
+ __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+ LDB_BGREF_RMODE_EXT, ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) |
+ LDB_BGREF_RMODE_INT, ldb.control_reg);
+
+ switch (ldb.chan_mode_opt) {
+ case LDB_SIN_DI0:
+ if (var[0] == NULL) {
+ dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+ break;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_18,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_JEIDA,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[0]);
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH0_MODE_MASK) |
+ LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg);
+ ldb.ch_working[0] = true;
+ break;
+ case LDB_SIN_DI1:
+ if (var[1] == NULL) {
+ dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+ break;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+ LDB_DATA_WIDTH_CH1_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+ LDB_DATA_WIDTH_CH1_18,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_JEIDA,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~LDB_CH1_MODE_MASK) |
+ LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+ ldb.ch_working[1] = true;
+ break;
+ case LDB_SEP:
+ if (var[0] == NULL || var[1] == NULL) {
+ dev_err(g_ldb_dev, "Can't find framebuffers on DI0/1\n");
+ break;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) |
+ LDB_DATA_WIDTH_CH0_18,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+ LDB_DATA_WIDTH_CH1_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+ __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) |
+ LDB_DATA_WIDTH_CH1_18,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_JEIDA,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_JEIDA,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[0]);
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI0 |
+ LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+ ldb.ch_working[0] = true;
+ ldb.ch_working[1] = true;
+ break;
+ case LDB_DUL_DI0:
+ case LDB_SPL_DI0:
+ if (var[0] == NULL) {
+ dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n");
+ break;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24)
+ __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+ LDB_DATA_WIDTH_CH1_MASK)) |
+ LDB_DATA_WIDTH_CH0_24 |
+ LDB_DATA_WIDTH_CH1_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18)
+ __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+ LDB_DATA_WIDTH_CH1_MASK)) |
+ LDB_DATA_WIDTH_CH0_18 |
+ LDB_DATA_WIDTH_CH1_18,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_JEIDA,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_JEIDA,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_mode_opt == LDB_SPL_DI0)
+ __raw_writel(reg | LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ if (ldb.chan_mode_opt == LDB_DUL_DI0) {
+ clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7);
+ } else {
+ clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+ clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+ }
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI0 |
+ LDB_CH1_MODE_EN_TO_DI0, ldb.control_reg);
+ ldb.ch_working[0] = true;
+ ldb.ch_working[1] = true;
+ break;
+ case LDB_DUL_DI1:
+ case LDB_SPL_DI1:
+ if (var[1] == NULL) {
+ dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n");
+ break;
+ }
+
+ reg = __raw_readl(ldb.control_reg);
+ if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24)
+ __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+ LDB_DATA_WIDTH_CH1_MASK)) |
+ LDB_DATA_WIDTH_CH0_24 |
+ LDB_DATA_WIDTH_CH1_24,
+ ldb.control_reg);
+ else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18)
+ __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK |
+ LDB_DATA_WIDTH_CH1_MASK)) |
+ LDB_DATA_WIDTH_CH0_18 |
+ LDB_DATA_WIDTH_CH1_18,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) |
+ LDB_BIT_MAP_CH0_JEIDA,
+ ldb.control_reg);
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG)
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_SPWG,
+ ldb.control_reg);
+ else
+ __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) |
+ LDB_BIT_MAP_CH1_JEIDA,
+ ldb.control_reg);
+
+ reg = __raw_readl(ldb.control_reg);
+ if (ldb.chan_mode_opt == LDB_SPL_DI1)
+ __raw_writel(reg | LDB_SPLIT_MODE_EN,
+ ldb.control_reg);
+
+ ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk");
+ ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk");
+ if (ldb.chan_mode_opt == LDB_DUL_DI1) {
+ clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7);
+ } else {
+ clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7);
+ clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7);
+ }
+ clk_enable(ldb.ldb_di_clk[0]);
+ clk_enable(ldb.ldb_di_clk[1]);
+ clk_put(ldb.ldb_di_clk[0]);
+ clk_put(ldb.ldb_di_clk[1]);
+
+ reg = __raw_readl(ldb.control_reg);
+ __raw_writel((reg & ~(LDB_CH0_MODE_MASK |
+ LDB_CH1_MODE_MASK)) |
+ LDB_CH0_MODE_EN_TO_DI1 |
+ LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg);
+ ldb.ch_working[0] = true;
+ ldb.ch_working[1] = true;
+ break;
+ default:
+ break;
+ }
+
+ mxc_ldb_major = register_chrdev(0, "mxc_ldb", &mxc_ldb_fops);
+ if (mxc_ldb_major < 0) {
+ dev_err(g_ldb_dev, "Unable to register MXC LDB as a char "
+ "device\n");
+ ret = mxc_ldb_major;
+ goto err0;
+ }
+
+ mxc_ldb_class = class_create(THIS_MODULE, "mxc_ldb");
+ if (IS_ERR(mxc_ldb_class)) {
+ dev_err(g_ldb_dev, "Unable to create class for MXC LDB\n");
+ ret = PTR_ERR(mxc_ldb_class);
+ goto err1;
+ }
+
+ temp = device_create(mxc_ldb_class, NULL, MKDEV(mxc_ldb_major, 0),
+ NULL, "mxc_ldb");
+ if (IS_ERR(temp)) {
+ dev_err(g_ldb_dev, "Unable to create class device for "
+ "MXC LDB\n");
+ ret = PTR_ERR(temp);
+ goto err2;
+ }
+
+ ret = fb_register_client(&nb);
+ if (ret < 0)
+ goto err2;
+
+ if (primary && ldb.fbi[0] != NULL) {
+ acquire_console_sem();
+ fb_blank(ldb.fbi[0], FB_BLANK_UNBLANK);
+ release_console_sem();
+ fb_show_logo(ldb.fbi[0], 0);
+ }
+
+ return ret;
+err2:
+ class_destroy(mxc_ldb_class);
+err1:
+ unregister_chrdev(mxc_ldb_major, "mxc_ldb");
+err0:
+ iounmap(ldb_reg);
+ return ret;
+}
+
+static int ldb_remove(struct platform_device *pdev)
+{
+ int i;
+
+ __raw_writel(0, ldb.control_reg);
+
+ for (i = 0; i < 2; i++) {
+ if (ldb.ch_working[i]) {
+ ldb.ldb_di_clk[i] = clk_get(NULL,
+ i ? "ldb_di1_clk" : "ldb_di0_clk");
+ clk_disable(ldb.ldb_di_clk[i]);
+ clk_put(ldb.ldb_di_clk[i]);
+ ldb.ch_working[i] = false;
+ }
+ }
+
+ fb_unregister_client(&nb);
+ return 0;
+}
+
+static int ldb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ switch (ldb.chan_mode_opt) {
+ case LDB_SIN_DI0:
+ case LDB_DUL_DI0:
+ case LDB_SPL_DI0:
+ ldb_disable(0);
+ break;
+ case LDB_SIN_DI1:
+ case LDB_DUL_DI1:
+ case LDB_SPL_DI1:
+ ldb_disable(1);
+ break;
+ case LDB_SEP:
+ ldb_disable(0);
+ ldb_disable(1);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int ldb_resume(struct platform_device *pdev)
+{
+ switch (ldb.chan_mode_opt) {
+ case LDB_SIN_DI0:
+ case LDB_DUL_DI0:
+ case LDB_SPL_DI0:
+ ldb_enable(0);
+ break;
+ case LDB_SIN_DI1:
+ case LDB_DUL_DI1:
+ case LDB_SPL_DI1:
+ ldb_enable(1);
+ break;
+ case LDB_SEP:
+ ldb_enable(0);
+ ldb_enable(1);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static struct platform_driver mxcldb_driver = {
+ .driver = {
+ .name = "mxc_ldb",
+ },
+ .probe = ldb_probe,
+ .remove = ldb_remove,
+ .suspend = ldb_suspend,
+ .resume = ldb_resume,
+};
+
+/*
+ * Parse user specified options (`lvds=')
+ * example:
+ * lvds=single(separate, dual or split),(di=0 or di=1),
+ * ch0_map=SPWG or JEIDA,ch1_map=SPWG or JEIDA
+ *
+ */
+static int __init ldb_setup(char *options)
+{
+ g_enable_ldb = true;
+
+ if (!strlen(options))
+ return 1;
+ else if (!strsep(&options, "="))
+ return 1;
+
+ if (!strncmp(options, "single", 6)) {
+ strsep(&options, ",");
+ if (!strncmp(options, "di=0", 4))
+ g_chan_mode_opt = LDB_SIN_DI0;
+ else
+ g_chan_mode_opt = LDB_SIN_DI1;
+ } else if (!strncmp(options, "separate", 8)) {
+ g_chan_mode_opt = LDB_SEP;
+ } else if (!strncmp(options, "dual", 4)) {
+ strsep(&options, ",");
+ if (!strncmp(options, "di=", 3)) {
+ if (simple_strtoul(options + 3, NULL, 0) == 0)
+ g_chan_mode_opt = LDB_DUL_DI0;
+ else
+ g_chan_mode_opt = LDB_DUL_DI1;
+ }
+ } else if (!strncmp(options, "split", 5)) {
+ strsep(&options, ",");
+ if (!strncmp(options, "di=", 3)) {
+ if (simple_strtoul(options + 3, NULL, 0) == 0)
+ g_chan_mode_opt = LDB_SPL_DI0;
+ else
+ g_chan_mode_opt = LDB_SPL_DI1;
+ }
+ } else
+ return 1;
+
+ if ((strsep(&options, ",") != NULL) &&
+ !strncmp(options, "ch0_map=", 8)) {
+ if (!strncmp(options + 8, "SPWG", 4))
+ g_chan_bit_map[0] = LDB_BIT_MAP_SPWG;
+ else
+ g_chan_bit_map[0] = LDB_BIT_MAP_JEIDA;
+ }
+
+ if (!(g_chan_mode_opt == LDB_SIN_DI0 ||
+ g_chan_mode_opt == LDB_SIN_DI1) &&
+ (strsep(&options, ",") != NULL) &&
+ !strncmp(options, "ch1_map=", 8)) {
+ if (!strncmp(options + 8, "SPWG", 4))
+ g_chan_bit_map[1] = LDB_BIT_MAP_SPWG;
+ else
+ g_chan_bit_map[1] = LDB_BIT_MAP_JEIDA;
+ }
+
+ g_boot_cmd = true;
+
+ return 1;
+}
+__setup("ldb", ldb_setup);
+
+static int __init ldb_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&mxcldb_driver);
+ return 0;
+}
+
+static void __exit ldb_uninit(void)
+{
+ platform_driver_unregister(&mxcldb_driver);
+}
+
+module_init(ldb_init);
+module_exit(ldb_uninit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC LDB driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_elcdif_fb.c b/drivers/video/mxc/mxc_elcdif_fb.c
new file mode 100644
index 000000000000..e163edb7bfb9
--- /dev/null
+++ b/drivers/video/mxc/mxc_elcdif_fb.c
@@ -0,0 +1,1445 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Based on drivers/video/mxc/mxc_ipuv3_fb.c, drivers/video/mxs/lcdif.c
+ * and arch/arm/mach-mx28/include/mach/lcdif.h.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/mxcfb.h>
+#include <linux/uaccess.h>
+
+#include <mach/hardware.h>
+
+#include "elcdif_regs.h"
+
+/* ELCDIF Pixel format definitions */
+/* Four-character-code (FOURCC) */
+#define fourcc(a, b, c, d) \
+ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * ELCDIF RGB Formats
+ */
+#define ELCDIF_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1')
+#define ELCDIF_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O')
+#define ELCDIF_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P')
+#define ELCDIF_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6')
+#define ELCDIF_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6')
+#define ELCDIF_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3')
+#define ELCDIF_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3')
+#define ELCDIF_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4')
+#define ELCDIF_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A')
+#define ELCDIF_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4')
+#define ELCDIF_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A')
+#define ELCDIF_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R')
+
+struct mxc_elcdif_fb_data {
+ int cur_blank;
+ int next_blank;
+ int output_pix_fmt;
+ int elcdif_mode;
+ ssize_t mem_size;
+ ssize_t map_size;
+ dma_addr_t phys_start;
+ dma_addr_t cur_phys;
+ int dma_irq;
+ int err_irq;
+ void *virt_start;
+ struct completion vsync_complete;
+ struct semaphore flip_sem;
+ u32 pseudo_palette[16];
+};
+
+struct elcdif_signal_cfg {
+ unsigned clk_pol:1; /* true = falling edge */
+ unsigned enable_pol:1; /* true = active high */
+ unsigned Hsync_pol:1; /* true = active high */
+ unsigned Vsync_pol:1; /* true = active high */
+};
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info);
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *info);
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *info);
+static char *fb_mode;
+static unsigned long default_bpp = 16;
+static void __iomem *elcdif_base;
+static struct device *g_elcdif_dev;
+static bool g_elcdif_axi_clk_enable;
+static bool g_elcdif_pix_clk_enable;
+static struct clk *g_elcdif_axi_clk;
+static struct clk *g_elcdif_pix_clk;
+
+static inline void setup_dotclk_panel(u32 pixel_clk,
+ u16 v_pulse_width,
+ u16 v_period,
+ u16 v_wait_cnt,
+ u16 v_active,
+ u16 h_pulse_width,
+ u16 h_period,
+ u16 h_wait_cnt,
+ u16 h_active,
+ int in_pixel_format,
+ int out_pixel_format,
+ struct elcdif_signal_cfg sig_cfg,
+ int enable_present)
+{
+ u32 val, rounded_pixel_clk;
+
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ dev_dbg(g_elcdif_dev, "pixel clk = %d\n", pixel_clk);
+ rounded_pixel_clk = clk_round_rate(g_elcdif_pix_clk, pixel_clk);
+ clk_set_rate(g_elcdif_pix_clk, rounded_pixel_clk);
+
+ __raw_writel(BM_ELCDIF_CTRL_DATA_SHIFT_DIR,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+ __raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+ __raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS
+ (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8),
+ elcdif_base + HW_ELCDIF_CTRL2_SET);
+
+ /* Recover on underflow */
+ __raw_writel(BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+ /* Configure the input pixel format */
+ __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+ BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+ BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT |
+ BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT |
+ BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ switch (in_pixel_format) {
+ case ELCDIF_PIX_FMT_RGB565:
+ __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(0) |
+ BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ case ELCDIF_PIX_FMT_RGB24:
+ __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF),
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+ BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ case ELCDIF_PIX_FMT_RGB32:
+ __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7),
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) |
+ BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ default:
+ dev_err(g_elcdif_dev, "ELCDIF unsupported input pixel format "
+ "%d\n", in_pixel_format);
+ break;
+ }
+
+ /* Configure the output pixel format */
+ __raw_writel(BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ switch (out_pixel_format) {
+ case ELCDIF_PIX_FMT_RGB565:
+ __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(0),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ case ELCDIF_PIX_FMT_RGB666:
+ __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(2),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ case ELCDIF_PIX_FMT_RGB24:
+ __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(3),
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+ default:
+ dev_err(g_elcdif_dev, "ELCDIF unsupported output pixel format "
+ "%d\n", out_pixel_format);
+ break;
+ }
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+ val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+ BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+ val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+ BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+ __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+ val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_POL |
+ BM_ELCDIF_VDCTRL0_HSYNC_POL |
+ BM_ELCDIF_VDCTRL0_ENABLE_POL |
+ BM_ELCDIF_VDCTRL0_DOTCLK_POL);
+ if (sig_cfg.Vsync_pol)
+ val |= BM_ELCDIF_VDCTRL0_VSYNC_POL;
+ if (sig_cfg.Hsync_pol)
+ val |= BM_ELCDIF_VDCTRL0_HSYNC_POL;
+ if (sig_cfg.clk_pol)
+ val |= BM_ELCDIF_VDCTRL0_DOTCLK_POL;
+ if (sig_cfg.enable_pol)
+ val |= BM_ELCDIF_VDCTRL0_ENABLE_POL;
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+ /* vsync is output */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+ val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_OEB);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+ /*
+ * need enable sig for true RGB i/f. Or, if not true RGB, leave it
+ * zero.
+ */
+ if (enable_present) {
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+ val |= BM_ELCDIF_VDCTRL0_ENABLE_PRESENT;
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+ }
+
+ /*
+ * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines
+ */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0);
+ val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT);
+ val |= BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT;
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0);
+
+ __raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH,
+ elcdif_base + HW_ELCDIF_VDCTRL0_CLR);
+ __raw_writel(v_pulse_width, elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+ __raw_writel(BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v_period),
+ elcdif_base + HW_ELCDIF_VDCTRL1);
+
+ __raw_writel(BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) |
+ BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(h_period),
+ elcdif_base + HW_ELCDIF_VDCTRL2);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+ val &= ~BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT;
+ val |= BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL3);
+ val &= ~(BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT |
+ BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT);
+ val |= BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) |
+ BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4);
+ val |= BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON;
+ __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4);
+
+ return;
+}
+
+static inline void release_dotclk_panel(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL0);
+ __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL1);
+ __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL2);
+ __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL3);
+
+ return;
+}
+
+static inline void setup_dvi_panel(u16 h_active, u16 v_active,
+ u16 h_blanking, u16 v_lines,
+ u16 v1_blank_start, u16 v1_blank_end,
+ u16 v2_blank_start, u16 v2_blank_end,
+ u16 f1_start, u16 f1_end,
+ u16 f2_start, u16 f2_end)
+{
+ u32 val;
+
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ /* 32bit packed format (RGB) */
+ __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) |
+ BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+ val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT |
+ BM_ELCDIF_TRANSFER_COUNT_H_COUNT);
+ val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+ BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT);
+
+ /* set elcdif to DVI mode */
+ __raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+ __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ /* convert input RGB -> YCbCr */
+ __raw_writel(BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ /* interlace odd and even fields */
+ __raw_writel(BM_ELCDIF_CTRL1_INTERLACE_FIELDS,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+ __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH |
+ BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE |
+ BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */
+ BM_ELCDIF_CTRL_DATA_SELECT | /* data mode */
+ BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */
+ BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+
+ /* ELCDIF_DVI */
+ /* set frame size */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL0);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL0);
+
+ /* set start/end of field-1 and start of field-2 */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL1);
+ val &= ~(BM_ELCDIF_DVICTRL1_F1_START_LINE |
+ BM_ELCDIF_DVICTRL1_F1_END_LINE |
+ BM_ELCDIF_DVICTRL1_F2_START_LINE);
+ val |= BF_ELCDIF_DVICTRL1_F1_START_LINE(f1_start) |
+ BF_ELCDIF_DVICTRL1_F1_END_LINE(f1_end) |
+ BF_ELCDIF_DVICTRL1_F2_START_LINE(f2_start);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL1);
+
+ /* set first vertical blanking interval and end of filed-2 */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL2);
+ val &= ~(BM_ELCDIF_DVICTRL2_F2_END_LINE |
+ BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE |
+ BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE);
+ val |= BF_ELCDIF_DVICTRL2_F2_END_LINE(f2_end) |
+ BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) |
+ BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL2);
+
+ /* set second vertical blanking interval */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL3);
+ val &= ~(BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE |
+ BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE);
+ val |= BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) |
+ BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL3);
+
+ /* fill the rest area black color if the input frame
+ * is not 720 pixels/line
+ */
+ if (h_active != 720) {
+ /* the input frame can't be less then (720-256) pixels/line */
+ if (720 - h_active > 0xff)
+ h_active = 720 - 0xff;
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL4);
+ val &= ~(BM_ELCDIF_DVICTRL4_H_FILL_CNT |
+ BM_ELCDIF_DVICTRL4_Y_FILL_VALUE |
+ BM_ELCDIF_DVICTRL4_CB_FILL_VALUE |
+ BM_ELCDIF_DVICTRL4_CR_FILL_VALUE);
+ val |= BF_ELCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) |
+ BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(16) |
+ BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(128) |
+ BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(128);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL4);
+ }
+
+ /* Color Space Conversion RGB->YCbCr */
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF0);
+ val &= ~(BM_ELCDIF_CSC_COEFF0_C0 |
+ BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER);
+ val |= BF_ELCDIF_CSC_COEFF0_C0(0x41) |
+ BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF0);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF1);
+ val &= ~(BM_ELCDIF_CSC_COEFF1_C1 | BM_ELCDIF_CSC_COEFF1_C2);
+ val |= BF_ELCDIF_CSC_COEFF1_C1(0x81) |
+ BF_ELCDIF_CSC_COEFF1_C2(0x19);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF1);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF2);
+ val &= ~(BM_ELCDIF_CSC_COEFF2_C3 | BM_ELCDIF_CSC_COEFF2_C4);
+ val |= BF_ELCDIF_CSC_COEFF2_C3(0x3DB) |
+ BF_ELCDIF_CSC_COEFF2_C4(0x3B6);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF2);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF3);
+ val &= ~(BM_ELCDIF_CSC_COEFF3_C5 | BM_ELCDIF_CSC_COEFF3_C6);
+ val |= BF_ELCDIF_CSC_COEFF3_C5(0x70) |
+ BF_ELCDIF_CSC_COEFF3_C6(0x70);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF3);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF4);
+ val &= ~(BM_ELCDIF_CSC_COEFF4_C7 | BM_ELCDIF_CSC_COEFF4_C8);
+ val |= BF_ELCDIF_CSC_COEFF4_C7(0x3A2) |
+ BF_ELCDIF_CSC_COEFF4_C8(0x3EE);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF4);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_OFFSET);
+ val &= ~(BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET |
+ BM_ELCDIF_CSC_OFFSET_Y_OFFSET);
+ val |= BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) |
+ BF_ELCDIF_CSC_OFFSET_Y_OFFSET(0x10);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_OFFSET);
+
+ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_LIMIT);
+ val &= ~(BM_ELCDIF_CSC_LIMIT_CBCR_MIN |
+ BM_ELCDIF_CSC_LIMIT_CBCR_MAX |
+ BM_ELCDIF_CSC_LIMIT_Y_MIN |
+ BM_ELCDIF_CSC_LIMIT_Y_MAX);
+ val |= BF_ELCDIF_CSC_LIMIT_CBCR_MIN(16) |
+ BF_ELCDIF_CSC_LIMIT_CBCR_MAX(240) |
+ BF_ELCDIF_CSC_LIMIT_Y_MIN(16) |
+ BF_ELCDIF_CSC_LIMIT_Y_MAX(235);
+ __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_LIMIT);
+
+ return;
+}
+
+static inline void release_dvi_panel(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_DVI_MODE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ return;
+}
+
+static inline void mxc_init_elcdif(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_CLKGATE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ /* Reset controller */
+ __raw_writel(BM_ELCDIF_CTRL_SFTRST,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ udelay(10);
+
+ /* Take controller out of reset */
+ __raw_writel(BM_ELCDIF_CTRL_SFTRST | BM_ELCDIF_CTRL_CLKGATE,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+
+ /* Setup the bus protocol */
+ __raw_writel(BM_ELCDIF_CTRL1_MODE86,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ __raw_writel(BM_ELCDIF_CTRL1_BUSY_ENABLE,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+ /* Take display out of reset */
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+
+ /* VSYNC is an input by default */
+ __raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_OEB,
+ elcdif_base + HW_ELCDIF_VDCTRL0_SET);
+
+ /* Reset display */
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ udelay(10);
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ udelay(10);
+
+ return;
+}
+
+int mxc_elcdif_frame_addr_setup(dma_addr_t phys)
+{
+ int ret = 0;
+
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+
+ __raw_writel(phys, elcdif_base + HW_ELCDIF_CUR_BUF);
+ __raw_writel(phys, elcdif_base + HW_ELCDIF_NEXT_BUF);
+ return ret;
+}
+
+static inline void mxc_elcdif_dma_release(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ return;
+}
+
+static inline void mxc_elcdif_run(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ __raw_writel(BM_ELCDIF_CTRL_RUN,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ return;
+}
+
+static inline void mxc_elcdif_stop(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ __raw_writel(BM_ELCDIF_CTRL_RUN,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ msleep(1);
+ __raw_writel(BM_ELCDIF_CTRL_CLKGATE, elcdif_base + HW_ELCDIF_CTRL_SET);
+ return;
+}
+
+static int mxc_elcdif_blank_panel(int blank)
+{
+ int ret = 0, count;
+
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ switch (blank) {
+ case FB_BLANK_NORMAL:
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ case FB_BLANK_POWERDOWN:
+ __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+ elcdif_base + HW_ELCDIF_CTRL_CLR);
+ for (count = 10000; count; count--) {
+ if (__raw_readl(elcdif_base + HW_ELCDIF_STAT) &
+ BM_ELCDIF_STAT_TXFIFO_EMPTY)
+ break;
+ msleep(1);
+ }
+ break;
+
+ case FB_BLANK_UNBLANK:
+ __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT,
+ elcdif_base + HW_ELCDIF_CTRL_SET);
+ break;
+
+ default:
+ dev_err(g_elcdif_dev, "unknown blank parameter\n");
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int mxc_elcdif_init_panel(void)
+{
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+
+ /*
+ * Make sure we do a high-to-low transition to reset the panel.
+ * First make it low for 100 msec, hi for 10 msec, low for 10 msec,
+ * then hi.
+ */
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR); /* low */
+ msleep(100);
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_SET); /* high */
+ msleep(10);
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR); /* low */
+
+ /* For the Samsung, Reset must be held low at least 30 uSec
+ * Therefore, we'll hold it low for about 10 mSec just to be sure.
+ * Then we'll wait 1 mSec afterwards.
+ */
+ msleep(10);
+ __raw_writel(BM_ELCDIF_CTRL1_RESET,
+ elcdif_base + HW_ELCDIF_CTRL1_SET); /* high */
+ msleep(1);
+
+ return 0;
+}
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+ uint32_t pixfmt = 0;
+
+ if (fbi->var.nonstd)
+ return fbi->var.nonstd;
+
+ switch (fbi->var.bits_per_pixel) {
+ case 32:
+ pixfmt = ELCDIF_PIX_FMT_RGB32;
+ break;
+ case 24:
+ pixfmt = ELCDIF_PIX_FMT_RGB24;
+ break;
+ case 18:
+ pixfmt = ELCDIF_PIX_FMT_RGB666;
+ break;
+ case 16:
+ pixfmt = ELCDIF_PIX_FMT_RGB565;
+ break;
+ case 8:
+ pixfmt = ELCDIF_PIX_FMT_RGB332;
+ break;
+ }
+ return pixfmt;
+}
+
+static int mxc_elcdif_fb_set_fix(struct fb_info *info)
+{
+ struct fb_fix_screeninfo *fix = &info->fix;
+ struct fb_var_screeninfo *var = &info->var;
+
+ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+ fix->type = FB_TYPE_PACKED_PIXELS;
+ fix->accel = FB_ACCEL_NONE;
+ fix->visual = FB_VISUAL_TRUECOLOR;
+ fix->xpanstep = 1;
+ fix->ypanstep = 1;
+
+ return 0;
+}
+
+static irqreturn_t lcd_irq_handler(int irq, void *dev_id)
+{
+ struct mxc_elcdif_fb_data *data = dev_id;
+ u32 status_lcd = __raw_readl(elcdif_base + HW_ELCDIF_CTRL1);
+ dev_dbg(g_elcdif_dev, "%s: irq %d\n", __func__, irq);
+
+ if (status_lcd & BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ) {
+ dev_dbg(g_elcdif_dev, "%s: VSYNC irq\n", __func__);
+ __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ complete(&data->vsync_complete);
+ }
+ if (status_lcd & BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ) {
+ dev_dbg(g_elcdif_dev, "%s: frame done irq\n", __func__);
+ __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ up(&data->flip_sem);
+ }
+ if (status_lcd & BM_ELCDIF_CTRL1_UNDERFLOW_IRQ) {
+ dev_dbg(g_elcdif_dev, "%s: underflow irq\n", __func__);
+ __raw_writel(BM_ELCDIF_CTRL1_UNDERFLOW_IRQ,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ }
+ if (status_lcd & BM_ELCDIF_CTRL1_OVERFLOW_IRQ) {
+ dev_dbg(g_elcdif_dev, "%s: overflow irq\n", __func__);
+ __raw_writel(BM_ELCDIF_CTRL1_OVERFLOW_IRQ,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ }
+ return IRQ_HANDLED;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int mxc_elcdif_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp,
+ struct fb_info *fbi)
+{
+ unsigned int val;
+ int ret = 1;
+
+ /*
+ * If greyscale is true, then we convert the RGB value
+ * to greyscale no matter what visual we are using.
+ */
+ if (fbi->var.grayscale)
+ red = green = blue = (19595 * red + 38470 * green +
+ 7471 * blue) >> 16;
+ switch (fbi->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ /*
+ * 16-bit True Colour. We encode the RGB value
+ * according to the RGB bitfield information.
+ */
+ if (regno < 16) {
+ u32 *pal = fbi->pseudo_palette;
+
+ val = _chan_to_field(red, &fbi->var.red);
+ val |= _chan_to_field(green, &fbi->var.green);
+ val |= _chan_to_field(blue, &fbi->var.blue);
+
+ pal[regno] = val;
+ ret = 0;
+ }
+ break;
+
+ case FB_VISUAL_STATIC_PSEUDOCOLOR:
+ case FB_VISUAL_PSEUDOCOLOR:
+ break;
+ }
+ return ret;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_elcdif_fb_set_par(struct fb_info *fbi)
+{
+ struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+ struct elcdif_signal_cfg sig_cfg;
+ int mem_len;
+
+ dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
+
+ sema_init(&data->flip_sem, 1);
+
+ /* release prev panel */
+ if (!g_elcdif_pix_clk_enable) {
+ clk_enable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = true;
+ }
+ mxc_elcdif_blank_panel(FB_BLANK_POWERDOWN);
+ mxc_elcdif_stop();
+ release_dotclk_panel();
+ mxc_elcdif_dma_release();
+ mxc_elcdif_fb_set_fix(fbi);
+ if (g_elcdif_pix_clk_enable) {
+ clk_disable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = false;
+ }
+
+ mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+ if (fbi->fix.smem_start)
+ mxc_elcdif_fb_unmap_video_memory(fbi);
+
+ if (mxc_elcdif_fb_map_video_memory(fbi) < 0)
+ return -ENOMEM;
+ }
+
+ if (data->next_blank != FB_BLANK_UNBLANK)
+ return 0;
+
+ /* init next panel */
+ if (!g_elcdif_pix_clk_enable) {
+ clk_enable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = true;
+ }
+ mxc_init_elcdif();
+ mxc_elcdif_init_panel();
+
+ dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+ (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+ memset(&sig_cfg, 0, sizeof(sig_cfg));
+ if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+ sig_cfg.Hsync_pol = true;
+ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ sig_cfg.Vsync_pol = true;
+ if (fbi->var.sync & FB_SYNC_CLK_LAT_FALL)
+ sig_cfg.clk_pol = true;
+ if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+ sig_cfg.enable_pol = true;
+
+ setup_dotclk_panel((PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+ fbi->var.vsync_len,
+ fbi->var.upper_margin +
+ fbi->var.yres + fbi->var.lower_margin,
+ fbi->var.upper_margin,
+ fbi->var.yres,
+ fbi->var.hsync_len,
+ fbi->var.left_margin +
+ fbi->var.xres + fbi->var.right_margin,
+ fbi->var.left_margin,
+ fbi->var.xres,
+ bpp_to_pixfmt(fbi),
+ data->output_pix_fmt,
+ sig_cfg,
+ 1);
+ mxc_elcdif_frame_addr_setup(fbi->fix.smem_start);
+ mxc_elcdif_run();
+ mxc_elcdif_blank_panel(FB_BLANK_UNBLANK);
+
+ fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
+ &fbi->modelist);
+ return 0;
+}
+
+static int mxc_elcdif_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ if (var->xres_virtual < var->xres)
+ var->xres_virtual = var->xres;
+ if (var->yres_virtual < var->yres)
+ var->yres_virtual = var->yres;
+
+ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+ var->bits_per_pixel = default_bpp;
+
+ switch (var->bits_per_pixel) {
+ case 8:
+ var->red.length = 3;
+ var->red.offset = 5;
+ var->red.msb_right = 0;
+
+ var->green.length = 3;
+ var->green.offset = 2;
+ var->green.msb_right = 0;
+
+ var->blue.length = 2;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 16:
+ var->red.length = 5;
+ var->red.offset = 11;
+ var->red.msb_right = 0;
+
+ var->green.length = 6;
+ var->green.offset = 5;
+ var->green.msb_right = 0;
+
+ var->blue.length = 5;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 24:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 32:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 8;
+ var->transp.offset = 24;
+ var->transp.msb_right = 0;
+ break;
+ }
+
+ var->height = -1;
+ var->width = -1;
+ var->grayscale = 0;
+
+ return 0;
+}
+
+static int mxc_elcdif_fb_wait_for_vsync(u32 channel, struct fb_info *info)
+{
+ struct mxc_elcdif_fb_data *data =
+ (struct mxc_elcdif_fb_data *)info->par;
+ int ret = 0;
+
+ if (data->cur_blank != FB_BLANK_UNBLANK) {
+ dev_err(info->device, "can't wait for VSYNC when fb "
+ "is blank\n");
+ return -EINVAL;
+ }
+
+ init_completion(&data->vsync_complete);
+
+ __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ ret = wait_for_completion_interruptible_timeout(
+ &data->vsync_complete, 1 * HZ);
+ if (ret == 0) {
+ dev_err(info->device,
+ "MXC ELCDIF wait for vsync: timeout %d\n",
+ ret);
+ ret = -ETIME;
+ } else if (ret > 0) {
+ ret = 0;
+ }
+ __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ if (!ret) {
+ dev_err(info->device, "wait for vsync timed out\n");
+ ret = -ETIMEDOUT;
+ }
+ return ret;
+}
+
+static int mxc_elcdif_fb_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+{
+ u32 channel = 0;
+ int ret = -EINVAL;
+
+ switch (cmd) {
+ case MXCFB_WAIT_FOR_VSYNC:
+ if (!get_user(channel, (__u32 __user *) arg))
+ ret = mxc_elcdif_fb_wait_for_vsync(channel, info);
+ break;
+ case MXCFB_GET_FB_BLANK:
+ {
+ struct mxc_elcdif_fb_data *data =
+ (struct mxc_elcdif_fb_data *)info->par;
+
+ if (put_user(data->cur_blank, (__u32 __user *)arg))
+ return -EFAULT;
+ break;
+ }
+ default:
+ break;
+ }
+ return ret;
+}
+
+static int mxc_elcdif_fb_blank(int blank, struct fb_info *info)
+{
+ struct mxc_elcdif_fb_data *data =
+ (struct mxc_elcdif_fb_data *)info->par;
+ int ret = 0;
+
+ if (data->cur_blank == blank)
+ return ret;
+
+ data->next_blank = blank;
+
+ if (!g_elcdif_pix_clk_enable) {
+ clk_enable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = true;
+ }
+ ret = mxc_elcdif_blank_panel(blank);
+ if (ret == 0)
+ data->cur_blank = blank;
+ else
+ return ret;
+
+ if (blank == FB_BLANK_UNBLANK) {
+ ret = mxc_elcdif_fb_set_par(info);
+ if (ret)
+ return ret;
+ }
+
+ if (data->cur_blank != FB_BLANK_UNBLANK) {
+ if (g_elcdif_axi_clk_enable) {
+ clk_disable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = false;
+ }
+ if (g_elcdif_pix_clk_enable) {
+ clk_disable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = false;
+ }
+ } else {
+ if (!g_elcdif_axi_clk_enable) {
+ clk_enable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = true;
+ }
+ if (!g_elcdif_pix_clk_enable) {
+ clk_enable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = true;
+ }
+ }
+
+ return ret;
+}
+
+static int mxc_elcdif_fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct mxc_elcdif_fb_data *data =
+ (struct mxc_elcdif_fb_data *)info->par;
+ int ret = 0;
+ unsigned long base;
+
+ if (data->cur_blank != FB_BLANK_UNBLANK) {
+ dev_err(info->device, "can't do pan display when fb "
+ "is blank\n");
+ return -EINVAL;
+ }
+
+ if (var->xoffset > 0) {
+ dev_dbg(info->device, "x panning not supported\n");
+ return -EINVAL;
+ }
+
+ if ((var->yoffset + var->yres > var->yres_virtual)) {
+ dev_err(info->device, "y panning exceeds\n");
+ return -EINVAL;
+ }
+
+ /* update framebuffer visual */
+ base = (var->yoffset * var->xres_virtual + var->xoffset);
+ base *= (var->bits_per_pixel) / 8;
+ base += info->fix.smem_start;
+
+ __raw_writel(base, elcdif_base + HW_ELCDIF_NEXT_BUF);
+
+ init_completion(&data->vsync_complete);
+
+ /*
+ * Wait for an interrupt or we will lose frame
+ * if we call pan-dislay too fast.
+ */
+ __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+ __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+ elcdif_base + HW_ELCDIF_CTRL1_SET);
+ down(&data->flip_sem);
+ __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN,
+ elcdif_base + HW_ELCDIF_CTRL1_CLR);
+
+ return ret;
+}
+
+static struct fb_ops mxc_elcdif_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = mxc_elcdif_fb_check_var,
+ .fb_set_par = mxc_elcdif_fb_set_par,
+ .fb_setcolreg = mxc_elcdif_fb_setcolreg,
+ .fb_ioctl = mxc_elcdif_fb_ioctl,
+ .fb_blank = mxc_elcdif_fb_blank,
+ .fb_pan_display = mxc_elcdif_fb_pan_display,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+/*!
+ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache. Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param fbi framebuffer information pointer
+ *
+ * @return Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_map_video_memory(struct fb_info *fbi)
+{
+ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
+ fbi->fix.smem_len = fbi->var.yres_virtual *
+ fbi->fix.line_length;
+
+ fbi->screen_base = dma_alloc_writecombine(fbi->device,
+ fbi->fix.smem_len,
+ (dma_addr_t *)&fbi->fix.smem_start,
+ GFP_DMA);
+ if (fbi->screen_base == 0) {
+ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+ fbi->fix.smem_len = 0;
+ fbi->fix.smem_start = 0;
+ return -EBUSY;
+ }
+
+ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+ fbi->screen_size = fbi->fix.smem_len;
+
+ /* Clear the screen */
+ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+ return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param fbi framebuffer information pointer
+ *
+ * @return Error code indicating success or failure
+ */
+static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *fbi)
+{
+ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+ fbi->screen_base, fbi->fix.smem_start);
+ fbi->screen_base = 0;
+ fbi->fix.smem_start = 0;
+ fbi->fix.smem_len = 0;
+ return 0;
+}
+
+static int mxc_elcdif_fb_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct mxc_elcdif_fb_data *data;
+ struct resource *res;
+ struct fb_info *fbi;
+ struct mxc_fb_platform_data *pdata = pdev->dev.platform_data;
+
+ fbi = framebuffer_alloc(sizeof(struct mxc_elcdif_fb_data), &pdev->dev);
+ if (fbi == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ data = (struct mxc_elcdif_fb_data *)fbi->par;
+ data->cur_blank = data->next_blank = FB_BLANK_UNBLANK;
+
+ fbi->var.activate = FB_ACTIVATE_NOW;
+ fbi->fbops = &mxc_elcdif_fb_ops;
+ fbi->flags = FBINFO_FLAG_DEFAULT;
+ fbi->pseudo_palette = data->pseudo_palette;
+
+ ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
+ if (ret)
+ goto out;
+
+ g_elcdif_dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "cannot get IRQ resource\n");
+ ret = -ENODEV;
+ goto err0;
+ }
+ data->dma_irq = res->start;
+
+ ret = request_irq(data->dma_irq, lcd_irq_handler, 0,
+ "mxc_elcdif_fb", data);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+ data->dma_irq, ret);
+ goto err0;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ ret = -ENODEV;
+ goto err1;
+ }
+ elcdif_base = ioremap(res->start, SZ_4K);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (res) {
+ fbi->fix.smem_len = res->end - res->start + 1;
+ fbi->fix.smem_start = res->start;
+ fbi->screen_base = ioremap(fbi->fix.smem_start,
+ fbi->fix.smem_len);
+ }
+
+ strcpy(fbi->fix.id, "mxc_elcdif_fb");
+
+ fbi->var.xres = 800;
+ fbi->var.yres = 480;
+
+ if (pdata && !data->output_pix_fmt)
+ data->output_pix_fmt = pdata->interface_pix_fmt;
+
+ if (pdata && pdata->mode && pdata->num_modes)
+ fb_videomode_to_modelist(pdata->mode, pdata->num_modes,
+ &fbi->modelist);
+
+ if (!fb_mode && pdata && pdata->mode_str)
+ fb_mode = pdata->mode_str;
+
+ if (fb_mode) {
+ ret = fb_find_mode(&fbi->var, fbi, fb_mode, NULL, 0, NULL,
+ default_bpp);
+ if ((!ret || (ret > 2)) && pdata && pdata->mode &&
+ pdata->num_modes)
+ fb_find_mode(&fbi->var, fbi, fb_mode, pdata->mode,
+ pdata->num_modes, NULL, default_bpp);
+ }
+
+ mxc_elcdif_fb_check_var(&fbi->var, fbi);
+
+ fbi->var.xres_virtual = fbi->var.xres;
+ fbi->var.yres_virtual = fbi->var.yres * 3;
+
+ mxc_elcdif_fb_set_fix(fbi);
+
+ if (!res || !res->end)
+ if (mxc_elcdif_fb_map_video_memory(fbi) < 0) {
+ ret = -ENOMEM;
+ goto err2;
+ }
+
+ g_elcdif_axi_clk = clk_get(g_elcdif_dev, "elcdif_axi");
+ if (g_elcdif_axi_clk == NULL) {
+ dev_err(&pdev->dev, "can't get ELCDIF axi clk\n");
+ ret = -ENODEV;
+ goto err3;
+ }
+ g_elcdif_pix_clk = clk_get(g_elcdif_dev, "elcdif_pix");
+ if (g_elcdif_pix_clk == NULL) {
+ dev_err(&pdev->dev, "can't get ELCDIF pix clk\n");
+ ret = -ENODEV;
+ goto err3;
+ }
+ /*
+ * Set an appropriate pixel clk rate first, so that we can
+ * access ELCDIF registers.
+ */
+ clk_set_rate(g_elcdif_pix_clk, 25000000);
+
+ ret = register_framebuffer(fbi);
+ if (ret)
+ goto err3;
+
+ platform_set_drvdata(pdev, fbi);
+
+ return 0;
+err3:
+ mxc_elcdif_fb_unmap_video_memory(fbi);
+err2:
+ iounmap(elcdif_base);
+err1:
+ free_irq(data->dma_irq, data);
+err0:
+ fb_dealloc_cmap(&fbi->cmap);
+ framebuffer_release(fbi);
+out:
+ return ret;
+}
+
+static int mxc_elcdif_fb_remove(struct platform_device *pdev)
+{
+ struct fb_info *fbi = platform_get_drvdata(pdev);
+ struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+ mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+ mxc_elcdif_stop();
+ release_dotclk_panel();
+ mxc_elcdif_dma_release();
+
+ if (g_elcdif_axi_clk_enable) {
+ clk_disable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = false;
+ }
+ if (g_elcdif_pix_clk_enable) {
+ clk_disable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = false;
+ }
+ clk_put(g_elcdif_axi_clk);
+ clk_put(g_elcdif_pix_clk);
+
+ free_irq(data->dma_irq, data);
+ mxc_elcdif_fb_unmap_video_memory(fbi);
+
+ if (&fbi->cmap)
+ fb_dealloc_cmap(&fbi->cmap);
+
+ unregister_framebuffer(fbi);
+ framebuffer_release(fbi);
+
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_elcdif_fb_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct fb_info *fbi = platform_get_drvdata(pdev);
+ struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+ int saved_blank;
+
+ acquire_console_sem();
+ fb_set_suspend(fbi, 1);
+ saved_blank = data->cur_blank;
+ mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi);
+ data->next_blank = saved_blank;
+ if (!g_elcdif_pix_clk_enable) {
+ clk_enable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = true;
+ }
+ mxc_elcdif_stop();
+ mxc_elcdif_dma_release();
+ if (g_elcdif_pix_clk_enable) {
+ clk_disable(g_elcdif_pix_clk);
+ g_elcdif_pix_clk_enable = false;
+ }
+ if (g_elcdif_axi_clk_enable) {
+ clk_disable(g_elcdif_axi_clk);
+ g_elcdif_axi_clk_enable = false;
+ }
+ release_console_sem();
+ return 0;
+}
+
+static int mxc_elcdif_fb_resume(struct platform_device *pdev)
+{
+ struct fb_info *fbi = platform_get_drvdata(pdev);
+ struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par;
+
+ acquire_console_sem();
+ mxc_elcdif_fb_blank(data->next_blank, fbi);
+ fb_set_suspend(fbi, 0);
+ release_console_sem();
+
+ return 0;
+}
+#else
+#define mxc_elcdif_fb_suspend NULL
+#define mxc_elcdif_fb_resume NULL
+#endif
+
+static struct platform_driver mxc_elcdif_fb_driver = {
+ .probe = mxc_elcdif_fb_probe,
+ .remove = mxc_elcdif_fb_remove,
+ .suspend = mxc_elcdif_fb_suspend,
+ .resume = mxc_elcdif_fb_resume,
+ .driver = {
+ .name = "mxc_elcdif_fb",
+ .owner = THIS_MODULE,
+ },
+};
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * video=trident:800x600,bpp=16,noaccel
+ */
+int mxc_elcdif_fb_setup(char *options)
+{
+ char *opt;
+ if (!options || !*options)
+ return 0;
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+
+ if (!strncmp(opt, "bpp=", 4))
+ default_bpp = simple_strtoul(opt + 4, NULL, 0);
+ else
+ fb_mode = opt;
+ }
+ return 0;
+}
+
+static int __init mxc_elcdif_fb_init(void)
+{
+ char *option = NULL;
+
+ if (fb_get_options("mxc_elcdif_fb", &option))
+ return -ENODEV;
+ mxc_elcdif_fb_setup(option);
+
+ return platform_driver_register(&mxc_elcdif_fb_driver);
+}
+
+static void __exit mxc_elcdif_fb_exit(void)
+{
+ platform_driver_unregister(&mxc_elcdif_fb_driver);
+}
+
+module_init(mxc_elcdif_fb_init);
+module_exit(mxc_elcdif_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC ELCDIF Framebuffer Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c
new file mode 100644
index 000000000000..e9aa9fc72f9c
--- /dev/null
+++ b/drivers/video/mxc/mxc_epdc_fb.c
@@ -0,0 +1,3187 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X LCDIF
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+#include <linux/firmware.h>
+#include <linux/kthread.h>
+#include <linux/dmaengine.h>
+#include <linux/pxp_dma.h>
+#include <linux/mxcfb.h>
+#include <linux/gpio.h>
+#include <linux/regulator/driver.h>
+
+#include "epdc_regs.h"
+
+/*
+ * Enable this define to have a default panel
+ * loaded during driver initialization
+ */
+/*#define DEFAULT_PANEL_HW_INIT*/
+
+#define NUM_SCREENS 2
+#define NUM_SCREENS_X 16
+#define EPDC_NUM_LUTS 16
+#define EPDC_MAX_NUM_UPDATES 20
+#define INVALID_LUT -1
+#define TEMP_USE_DEFAULT 8
+#define INIT_UPDATE_MARKER 0x12345678
+#define PAN_UPDATE_MARKER 0x12345679
+
+#define LUT_UPDATE_NONE 0
+#define LUT_UPDATE_NEW 1
+#define LUT_UPDATE_COLLISION 2
+
+#define POWER_STATE_OFF 0
+#define POWER_STATE_ON 1
+
+static unsigned long default_bpp = 16;
+static unsigned long g_num_screens = NUM_SCREENS;
+
+struct update_marker_data {
+ u32 update_marker;
+ struct completion update_completion;
+ int lut_num;
+};
+
+/* This structure represents a list node containing both
+ * a memory region allocated as an output buffer for the PxP
+ * update processing task, and the update description (mode, region, etc.) */
+struct update_data_list {
+ struct list_head list;
+ struct mxcfb_update_data upd_data; /* Update parameters */
+ dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */
+ void *virt_addr;
+ u32 epdc_offs; /* Add to buffer pointer to resolve alignment */
+ u32 size;
+ int lut_num; /* Assigned before update is processed into working buffer */
+ int collision_mask; /* Set when update results in collision */
+ /* Represents other LUTs that we collide with */
+ struct update_marker_data *upd_marker_data;
+ bool is_collision;
+};
+
+struct mxc_epdc_fb_data {
+ struct fb_info info;
+ u32 pseudo_palette[16];
+ char *fb_panel_str;
+ struct list_head list;
+ struct mxc_epdc_fb_mode *cur_mode;
+ struct mxc_epdc_fb_platform_data *pdata;
+ int blank;
+ ssize_t map_size;
+ dma_addr_t phys_start;
+ u32 fb_offset;
+ int default_bpp;
+ int native_width;
+ int native_height;
+ int epdc_irq;
+ struct device *dev;
+ wait_queue_head_t vsync_wait_q;
+ u32 vsync_count;
+ void *par;
+ int power_state;
+ struct clk *epdc_clk_axi;
+ struct clk *epdc_clk_pix;
+ struct regulator *display_regulator;
+ struct regulator *vcom_regulator;
+
+ /* FB elements related to EPDC updates */
+ bool in_init;
+ bool hw_ready;
+ bool waiting_for_idle;
+ u32 auto_mode;
+ struct update_data_list *upd_buf_queue;
+ struct update_data_list *upd_buf_free_list;
+ struct update_data_list *upd_buf_collision_list;
+ struct update_data_list *cur_update;
+ spinlock_t queue_lock;
+ int trt_entries;
+ u8 *temp_range_bounds;
+ struct mxcfb_waveform_modes wv_modes;
+ u32 *waveform_buffer_virt;
+ u32 waveform_buffer_phys;
+ u32 waveform_buffer_size;
+ u32 *working_buffer_virt;
+ u32 working_buffer_phys;
+ u32 working_buffer_size;
+ struct update_marker_data update_marker_array[EPDC_MAX_NUM_UPDATES];
+ u32 lut_update_type[EPDC_NUM_LUTS];
+ struct completion updates_done;
+ struct delayed_work epdc_done_work;
+ struct mutex power_mutex;
+ bool powering_down;
+ int pwrdown_delay;
+
+ /* FB elements related to PxP DMA */
+ struct completion pxp_tx_cmpl;
+ struct pxp_channel *pxp_chan;
+ struct pxp_config_data pxp_conf;
+ struct dma_async_tx_descriptor *txd;
+ dma_cookie_t cookie;
+ struct scatterlist sg[2];
+ struct mutex pxp_mutex; /* protects access to PxP */
+};
+
+struct waveform_data_header {
+ unsigned int wi0;
+ unsigned int wi1;
+ unsigned int wi2;
+ unsigned int wi3;
+ unsigned int wi4;
+ unsigned int wi5;
+ unsigned int wi6;
+ unsigned int xwia:24;
+ unsigned int cs1:8;
+ unsigned int wmta:24;
+ unsigned int fvsn:8;
+ unsigned int luts:8;
+ unsigned int mc:8;
+ unsigned int trc:8;
+ unsigned int reserved0_0:8;
+ unsigned int eb:8;
+ unsigned int sb:8;
+ unsigned int reserved0_1:8;
+ unsigned int reserved0_2:8;
+ unsigned int reserved0_3:8;
+ unsigned int reserved0_4:8;
+ unsigned int reserved0_5:8;
+ unsigned int cs2:8;
+};
+
+struct mxcfb_waveform_data_file {
+ struct waveform_data_header wdh;
+ u32 *data; /* Temperature Range Table + Waveform Data */
+};
+
+void __iomem *epdc_base;
+
+/* forward declaration */
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
+static int mxc_epdc_fb_init_hw(struct fb_info *info);
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+ struct mxcfb_rect *update_region,
+ int x_start_offs);
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
+
+#ifdef DEBUG
+static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+ struct pxp_config_data *pxp_conf)
+{
+ dev_err(fb_data->dev, "S0 fmt 0x%x",
+ pxp_conf->s0_param.pixel_fmt);
+ dev_err(fb_data->dev, "S0 width 0x%x",
+ pxp_conf->s0_param.width);
+ dev_err(fb_data->dev, "S0 height 0x%x",
+ pxp_conf->s0_param.height);
+ dev_err(fb_data->dev, "S0 ckey 0x%x",
+ pxp_conf->s0_param.color_key);
+ dev_err(fb_data->dev, "S0 ckey en 0x%x",
+ pxp_conf->s0_param.color_key_enable);
+
+ dev_err(fb_data->dev, "OL0 combine en 0x%x",
+ pxp_conf->ol_param[0].combine_enable);
+ dev_err(fb_data->dev, "OL0 fmt 0x%x",
+ pxp_conf->ol_param[0].pixel_fmt);
+ dev_err(fb_data->dev, "OL0 width 0x%x",
+ pxp_conf->ol_param[0].width);
+ dev_err(fb_data->dev, "OL0 height 0x%x",
+ pxp_conf->ol_param[0].height);
+ dev_err(fb_data->dev, "OL0 ckey 0x%x",
+ pxp_conf->ol_param[0].color_key);
+ dev_err(fb_data->dev, "OL0 ckey en 0x%x",
+ pxp_conf->ol_param[0].color_key_enable);
+ dev_err(fb_data->dev, "OL0 alpha 0x%x",
+ pxp_conf->ol_param[0].global_alpha);
+ dev_err(fb_data->dev, "OL0 alpha en 0x%x",
+ pxp_conf->ol_param[0].global_alpha_enable);
+ dev_err(fb_data->dev, "OL0 local alpha en 0x%x",
+ pxp_conf->ol_param[0].local_alpha_enable);
+
+ dev_err(fb_data->dev, "Out fmt 0x%x",
+ pxp_conf->out_param.pixel_fmt);
+ dev_err(fb_data->dev, "Out width 0x%x",
+ pxp_conf->out_param.width);
+ dev_err(fb_data->dev, "Out height 0x%x",
+ pxp_conf->out_param.height);
+
+ dev_err(fb_data->dev,
+ "drect left 0x%x right 0x%x width 0x%x height 0x%x",
+ pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
+ pxp_conf->proc_data.drect.width,
+ pxp_conf->proc_data.drect.height);
+ dev_err(fb_data->dev,
+ "srect left 0x%x right 0x%x width 0x%x height 0x%x",
+ pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
+ pxp_conf->proc_data.srect.width,
+ pxp_conf->proc_data.srect.height);
+ dev_err(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
+ dev_err(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
+ dev_err(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
+ dev_err(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
+ dev_err(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
+}
+
+static void dump_epdc_reg(void)
+{
+ printk(KERN_DEBUG "\n\n");
+ printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
+ printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
+ printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
+ printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
+ printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
+ printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
+ printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
+ printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
+ printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
+ printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
+ printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
+ printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
+ printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
+ printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
+ printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
+ printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
+ printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
+ printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
+ printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
+ printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
+ printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
+ printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
+ printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
+ printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
+ printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
+ printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
+ printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
+ printk(KERN_DEBUG "EPDC_STATUS_COL 0x%x\n", __raw_readl(EPDC_STATUS_COL));
+ printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
+ printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT0 0x%x\n", __raw_readl(EPDC_DEBUG_LUT0));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT1 0x%x\n", __raw_readl(EPDC_DEBUG_LUT1));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT2 0x%x\n", __raw_readl(EPDC_DEBUG_LUT2));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT3 0x%x\n", __raw_readl(EPDC_DEBUG_LUT3));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT4 0x%x\n", __raw_readl(EPDC_DEBUG_LUT4));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT5 0x%x\n", __raw_readl(EPDC_DEBUG_LUT5));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT6 0x%x\n", __raw_readl(EPDC_DEBUG_LUT6));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT7 0x%x\n", __raw_readl(EPDC_DEBUG_LUT7));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT8 0x%x\n", __raw_readl(EPDC_DEBUG_LUT8));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT9 0x%x\n", __raw_readl(EPDC_DEBUG_LUT9));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT10 0x%x\n", __raw_readl(EPDC_DEBUG_LUT10));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT11 0x%x\n", __raw_readl(EPDC_DEBUG_LUT11));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT12 0x%x\n", __raw_readl(EPDC_DEBUG_LUT12));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT13 0x%x\n", __raw_readl(EPDC_DEBUG_LUT13));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT14 0x%x\n", __raw_readl(EPDC_DEBUG_LUT14));
+ printk(KERN_DEBUG "EPDC_DEBUG_LUT15 0x%x\n", __raw_readl(EPDC_DEBUG_LUT15));
+ printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
+ printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
+ printk(KERN_DEBUG "\n\n");
+}
+
+static void dump_update_data(struct device *dev,
+ struct update_data_list *upd_data_list)
+{
+ dev_err(dev,
+ "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, LUT = %d, Coll Mask = %d\n",
+ upd_data_list->upd_data.update_region.left,
+ upd_data_list->upd_data.update_region.top,
+ upd_data_list->upd_data.update_region.width,
+ upd_data_list->upd_data.update_region.height,
+ upd_data_list->upd_data.waveform_mode, upd_data_list->lut_num,
+ upd_data_list->collision_mask);
+}
+
+static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
+{
+ struct update_data_list *plist;
+
+ dev_err(fb_data->dev, "Collision List:\n");
+ if (list_empty(&fb_data->upd_buf_collision_list->list))
+ dev_err(fb_data->dev, "Empty");
+ list_for_each_entry(plist, &fb_data->upd_buf_collision_list->list, list) {
+ dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+ (u32)plist->virt_addr, plist->phys_addr);
+ dump_update_data(fb_data->dev, plist);
+ }
+}
+
+static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
+{
+ struct update_data_list *plist;
+
+ dev_err(fb_data->dev, "Free List:\n");
+ if (list_empty(&fb_data->upd_buf_free_list->list))
+ dev_err(fb_data->dev, "Empty");
+ list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list) {
+ dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+ (u32)plist->virt_addr, plist->phys_addr);
+ dump_update_data(fb_data->dev, plist);
+ }
+}
+
+static void dump_queue(struct mxc_epdc_fb_data *fb_data)
+{
+ struct update_data_list *plist;
+
+ dev_err(fb_data->dev, "Queue:\n");
+ if (list_empty(&fb_data->upd_buf_queue->list))
+ dev_err(fb_data->dev, "Empty");
+ list_for_each_entry(plist, &fb_data->upd_buf_queue->list, list) {
+ dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
+ (u32)plist->virt_addr, plist->phys_addr);
+ dump_update_data(fb_data->dev, plist);
+ }
+}
+
+static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
+{
+ dump_free_list(fb_data);
+ dump_queue(fb_data);
+ dump_collision_list(fb_data);
+ dev_err(fb_data->dev, "Current update being processed:\n");
+ if (fb_data->cur_update == NULL)
+ dev_err(fb_data->dev, "No current update\n");
+ else
+ dump_update_data(fb_data->dev, fb_data->cur_update);
+}
+#else
+static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
+ struct pxp_config_data *pxp_conf) {}
+static inline void dump_epdc_reg(void) {}
+static inline void dump_update_data(struct device *dev,
+ struct update_data_list *upd_data_list) {}
+static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
+static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
+
+#endif
+
+
+/********************************************************
+ * Start Low-Level EPDC Functions
+ ********************************************************/
+
+static inline void epdc_lut_complete_intr(u32 lut_num, bool enable)
+{
+ if (enable)
+ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
+ else
+ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_working_buf_intr(bool enable)
+{
+ if (enable)
+ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
+ else
+ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
+}
+
+static inline void epdc_clear_working_buf_irq(void)
+{
+ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
+ EPDC_IRQ_CLEAR);
+}
+
+static inline void epdc_set_temp(u32 temp)
+{
+ __raw_writel(temp, EPDC_TEMP);
+}
+
+static inline void epdc_set_screen_res(u32 width, u32 height)
+{
+ u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
+ __raw_writel(val, EPDC_RES);
+}
+
+static inline void epdc_set_update_addr(u32 addr)
+{
+ __raw_writel(addr, EPDC_UPD_ADDR);
+}
+
+static inline void epdc_set_update_coord(u32 x, u32 y)
+{
+ u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
+ __raw_writel(val, EPDC_UPD_CORD);
+}
+
+static inline void epdc_set_update_dimensions(u32 width, u32 height)
+{
+ u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
+ __raw_writel(val, EPDC_UPD_SIZE);
+}
+
+static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
+ bool use_test_mode, u32 np_val)
+{
+ u32 reg_val = 0;
+
+ if (use_test_mode) {
+ reg_val |=
+ ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
+ EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
+
+ __raw_writel(reg_val, EPDC_UPD_FIXED);
+
+ reg_val = EPDC_UPD_CTRL_USE_FIXED;
+ } else {
+ __raw_writel(reg_val, EPDC_UPD_FIXED);
+ }
+
+ reg_val |=
+ ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
+ EPDC_UPD_CTRL_LUT_SEL_MASK) |
+ ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
+ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
+ update_mode;
+
+ __raw_writel(reg_val, EPDC_UPD_CTRL);
+}
+
+static inline bool epdc_is_lut_complete(u32 lut_num)
+{
+ u32 val = __raw_readl(EPDC_IRQ);
+ bool is_compl = val & (1 << lut_num) ? true : false;
+
+ return is_compl;
+}
+
+static inline void epdc_clear_lut_complete_irq(u32 lut_num)
+{
+ __raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
+}
+
+static inline bool epdc_is_lut_active(u32 lut_num)
+{
+ u32 val = __raw_readl(EPDC_STATUS_LUTS);
+ bool is_active = val & (1 << lut_num) ? true : false;
+
+ return is_active;
+}
+
+static inline bool epdc_any_luts_active(void)
+{
+ bool any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
+
+ return any_active;
+}
+
+static inline bool epdc_any_luts_available(void)
+{
+ bool luts_available =
+ (__raw_readl(EPDC_STATUS_NEXTLUT) &
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
+ return luts_available;
+}
+
+static inline int epdc_get_next_lut(void)
+{
+ u32 val =
+ __raw_readl(EPDC_STATUS_NEXTLUT) &
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
+ return val;
+}
+
+static inline bool epdc_is_working_buffer_busy(void)
+{
+ u32 val = __raw_readl(EPDC_STATUS);
+ bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
+
+ return is_busy;
+}
+
+static inline bool epdc_is_working_buffer_complete(void)
+{
+ u32 val = __raw_readl(EPDC_IRQ);
+ bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
+
+ return is_compl;
+}
+
+static inline bool epdc_is_collision(void)
+{
+ u32 val = __raw_readl(EPDC_IRQ);
+ return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
+}
+
+static inline int epdc_get_colliding_luts(void)
+{
+ u32 val = __raw_readl(EPDC_STATUS_COL);
+ return val;
+}
+
+static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
+ u32 hsync_width, u32 hsync_line_length)
+{
+ u32 reg_val =
+ ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
+ | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
+ EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
+ __raw_writel(reg_val, EPDC_TCE_HSCAN1);
+
+ reg_val =
+ ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
+ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
+ | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
+ EPDC_TCE_HSCAN2_LINE_END_MASK);
+ __raw_writel(reg_val, EPDC_TCE_HSCAN2);
+}
+
+static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
+ u32 vsync_width)
+{
+ u32 reg_val =
+ ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
+ | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_END_MASK)
+ | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
+ __raw_writel(reg_val, EPDC_TCE_VSCAN);
+}
+
+void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
+{
+ struct mxc_epdc_fb_mode *epdc_mode = fb_data->cur_mode;
+ struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+ u32 reg_val;
+ int num_ce;
+
+ /* Reset */
+ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
+ while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
+ ;
+ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
+
+ /* Enable clock gating (clear to enable) */
+ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+ while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
+ ;
+
+ /* EPDC_CTRL */
+ reg_val = __raw_readl(EPDC_CTRL);
+ reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
+ reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
+ reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
+ reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
+ __raw_writel(reg_val, EPDC_CTRL_SET);
+
+ /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
+ reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
+ | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
+ | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
+ __raw_writel(reg_val, EPDC_FORMAT);
+
+ /* EPDC_FIFOCTRL (disabled) */
+ reg_val =
+ ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
+ | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
+ | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
+ __raw_writel(reg_val, EPDC_FIFOCTRL);
+
+ /* EPDC_TEMP - 8 for room temperature */
+ epdc_set_temp(8);
+
+ /* EPDC_RES */
+ epdc_set_screen_res(epdc_mode->vmode->xres, epdc_mode->vmode->yres);
+
+ /*
+ * EPDC_TCE_CTRL
+ * VSCAN_HOLDOFF = 4
+ * VCOM_MODE = MANUAL
+ * VCOM_VAL = 0
+ * DDR_MODE = DISABLED
+ * LVDS_MODE_CE = DISABLED
+ * LVDS_MODE = DISABLED
+ * DUAL_SCAN = DISABLED
+ * SDDO_WIDTH = 8bit
+ * PIXELS_PER_SDCLK = 4
+ */
+ reg_val =
+ ((epdc_mode->vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+ | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
+ __raw_writel(reg_val, EPDC_TCE_CTRL);
+
+ /* EPDC_TCE_HSCAN */
+ epdc_set_horizontal_timing(screeninfo->left_margin,
+ screeninfo->right_margin,
+ screeninfo->hsync_len,
+ screeninfo->hsync_len);
+
+ /* EPDC_TCE_VSCAN */
+ epdc_set_vertical_timing(screeninfo->upper_margin,
+ screeninfo->lower_margin,
+ screeninfo->vsync_len);
+
+ /* EPDC_TCE_OE */
+ reg_val =
+ ((epdc_mode->sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+ EPDC_TCE_OE_SDOED_WIDTH_MASK)
+ | ((epdc_mode->sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+ EPDC_TCE_OE_SDOED_DLY_MASK)
+ | ((epdc_mode->sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+ EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+ | ((epdc_mode->sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+ EPDC_TCE_OE_SDOEZ_DLY_MASK);
+ __raw_writel(reg_val, EPDC_TCE_OE);
+
+ /* EPDC_TCE_TIMING1 */
+ __raw_writel(0x0, EPDC_TCE_TIMING1);
+
+ /* EPDC_TCE_TIMING2 */
+ reg_val =
+ ((epdc_mode->gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+ EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+ | ((epdc_mode->gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+ __raw_writel(reg_val, EPDC_TCE_TIMING2);
+
+ /* EPDC_TCE_TIMING3 */
+ reg_val =
+ ((epdc_mode->gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+ | ((epdc_mode->gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+ __raw_writel(reg_val, EPDC_TCE_TIMING3);
+
+ /*
+ * EPDC_TCE_SDCFG
+ * SDCLK_HOLD = 1
+ * SDSHR = 1
+ * NUM_CE = 1
+ * SDDO_REFORMAT = FLIP_PIXELS
+ * SDDO_INVERT = DISABLED
+ * PIXELS_PER_CE = display horizontal resolution
+ */
+ num_ce = epdc_mode->num_ce;
+ if (num_ce == 0)
+ num_ce = 1;
+ reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
+ | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) &
+ EPDC_TCE_SDCFG_NUM_CE_MASK)
+ | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
+ | ((epdc_mode->vmode->xres/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
+ __raw_writel(reg_val, EPDC_TCE_SDCFG);
+
+ /*
+ * EPDC_TCE_GDCFG
+ * GDRL = 1
+ * GDOE_MODE = 0;
+ * GDSP_MODE = 0;
+ */
+ reg_val = EPDC_TCE_SDCFG_GDRL;
+ __raw_writel(reg_val, EPDC_TCE_GDCFG);
+
+ /*
+ * EPDC_TCE_POLARITY
+ * SDCE_POL = ACTIVE LOW
+ * SDLE_POL = ACTIVE HIGH
+ * SDOE_POL = ACTIVE HIGH
+ * GDOE_POL = ACTIVE HIGH
+ * GDSP_POL = ACTIVE LOW
+ */
+ reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
+ | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
+ | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
+ __raw_writel(reg_val, EPDC_TCE_POLARITY);
+
+ /* EPDC_IRQ_MASK */
+ __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
+
+ /*
+ * EPDC_GPIO
+ * PWRCOM = ?
+ * PWRCTRL = ?
+ * BDR = ?
+ */
+ reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
+ | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
+ __raw_writel(reg_val, EPDC_GPIO);
+}
+
+static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
+{
+ mutex_lock(&fb_data->power_mutex);
+
+ /*
+ * If power down request is pending, clear
+ * powering_down to cancel the request.
+ */
+ if (fb_data->powering_down)
+ fb_data->powering_down = false;
+
+ if (fb_data->power_state == POWER_STATE_ON) {
+ mutex_unlock(&fb_data->power_mutex);
+ return;
+ }
+
+ dev_dbg(fb_data->dev, "EPDC Powerup\n");
+
+ /* Enable pins used by EPDC */
+ if (fb_data->pdata->enable_pins)
+ fb_data->pdata->enable_pins();
+
+ /* Enable clocks to EPDC */
+ clk_enable(fb_data->epdc_clk_axi);
+ clk_enable(fb_data->epdc_clk_pix);
+
+ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
+
+ /* Enable power to the EPD panel */
+ regulator_enable(fb_data->display_regulator);
+ regulator_enable(fb_data->vcom_regulator);
+
+ fb_data->power_state = POWER_STATE_ON;
+
+ mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
+{
+ mutex_lock(&fb_data->power_mutex);
+
+ /* If powering_down has been cleared, a powerup
+ * request is pre-empting this powerdown request.
+ */
+ if (!fb_data->powering_down
+ || (fb_data->power_state == POWER_STATE_OFF)) {
+ mutex_unlock(&fb_data->power_mutex);
+ return;
+ }
+
+ dev_dbg(fb_data->dev, "EPDC Powerdown\n");
+
+ /* Disable power to the EPD panel */
+ regulator_disable(fb_data->vcom_regulator);
+ regulator_disable(fb_data->display_regulator);
+
+ /* Disable clocks to EPDC */
+ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
+ clk_disable(fb_data->epdc_clk_pix);
+ clk_disable(fb_data->epdc_clk_axi);
+
+ /* Disable pins used by EPDC (to prevent leakage current) */
+ if (fb_data->pdata->disable_pins)
+ fb_data->pdata->disable_pins();
+
+ fb_data->power_state = POWER_STATE_OFF;
+ fb_data->powering_down = false;
+
+ mutex_unlock(&fb_data->power_mutex);
+}
+
+static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data)
+{
+ /* Initialize EPDC, passing pointer to EPDC registers */
+ epdc_init_settings(fb_data);
+ __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
+ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
+ epdc_powerup(fb_data);
+ draw_mode0(fb_data);
+ epdc_powerdown(fb_data);
+}
+
+static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+ u32 len;
+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+
+ if (offset < info->fix.smem_len) {
+ /* mapping framebuffer memory */
+ len = info->fix.smem_len - offset;
+ vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
+ } else
+ return -EINVAL;
+
+ len = PAGE_ALIGN(len);
+ if (vma->vm_end - vma->vm_start > len)
+ return -EINVAL;
+
+ /* make buffers bufferable */
+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+ vma->vm_flags |= VM_IO | VM_RESERVED;
+
+ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+ dev_dbg(info->device, "mmap remap_pfn_range failed\n");
+ return -ENOBUFS;
+ }
+
+ return 0;
+}
+
+static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp, struct fb_info *info)
+{
+ if (regno >= 256) /* no. of hw registers */
+ return 1;
+ /*
+ * Program hardware... do anything you want with transp
+ */
+
+ /* grayscale works only partially under directcolor */
+ if (info->var.grayscale) {
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+ }
+
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
+ switch (info->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ case FB_VISUAL_PSEUDOCOLOR:
+ red = CNVT_TOHW(red, info->var.red.length);
+ green = CNVT_TOHW(green, info->var.green.length);
+ blue = CNVT_TOHW(blue, info->var.blue.length);
+ transp = CNVT_TOHW(transp, info->var.transp.length);
+ break;
+ case FB_VISUAL_DIRECTCOLOR:
+ red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */
+ green = CNVT_TOHW(green, 8);
+ blue = CNVT_TOHW(blue, 8);
+ /* hey, there is bug in transp handling... */
+ transp = CNVT_TOHW(transp, 8);
+ break;
+ }
+#undef CNVT_TOHW
+ /* Truecolor has hardware independent palette */
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+ if (regno >= 16)
+ return 1;
+
+ ((u32 *) (info->pseudo_palette))[regno] =
+ (red << info->var.red.offset) |
+ (green << info->var.green.offset) |
+ (blue << info->var.blue.offset) |
+ (transp << info->var.transp.offset);
+ }
+ return 0;
+}
+
+static void adjust_coordinates(struct mxc_epdc_fb_data *fb_data, struct mxcfb_rect *update_region)
+{
+ struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+ u32 rotation = fb_data->info.var.rotate;
+ u32 temp;
+
+ switch (rotation) {
+ case FB_ROTATE_UR:
+ /* No adjustment needed */
+ break;
+ case FB_ROTATE_CW:
+ temp = update_region->top;
+ update_region->top = update_region->left;
+ update_region->left = screeninfo->yres - (temp + update_region->height);
+ temp = update_region->width;
+ update_region->width = update_region->height;
+ update_region->height = temp;
+ break;
+ case FB_ROTATE_UD:
+ update_region->top = screeninfo->yres - (update_region->top + update_region->height);
+ update_region->left = screeninfo->xres - (update_region->left + update_region->width);
+ break;
+ case FB_ROTATE_CCW:
+ temp = update_region->left;
+ update_region->left = update_region->top;
+ update_region->top = screeninfo->xres - (temp + update_region->width);
+ temp = update_region->width;
+ update_region->width = update_region->height;
+ update_region->height = temp;
+ break;
+ }
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param info framebuffer information pointer
+ */
+static int mxc_epdc_fb_set_fix(struct fb_info *info)
+{
+ struct fb_fix_screeninfo *fix = &info->fix;
+ struct fb_var_screeninfo *var = &info->var;
+
+ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+ fix->type = FB_TYPE_PACKED_PIXELS;
+ fix->accel = FB_ACCEL_NONE;
+ fix->visual = FB_VISUAL_TRUECOLOR;
+ fix->xpanstep = 1;
+ fix->ypanstep = 1;
+
+ return 0;
+}
+
+/*
+ * This routine actually sets the video mode. It's in here where we
+ * the hardware state info->par and fix which can be affected by the
+ * change in par. For this driver it doesn't do much.
+ *
+ */
+static int mxc_epdc_fb_set_par(struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
+ struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
+ int i;
+ int ret;
+
+ /*
+ * Update PxP config data (used to process FB regions for updates)
+ * based on FB info and processing tasks required
+ */
+
+ /* Initialize non-channel-specific PxP parameters */
+ proc_data->drect.left = proc_data->srect.left = 0;
+ proc_data->drect.top = proc_data->srect.top = 0;
+ proc_data->drect.width = proc_data->srect.width = screeninfo->xres;
+ proc_data->drect.height = proc_data->srect.height = screeninfo->yres;
+ proc_data->scaling = 0;
+ proc_data->hflip = 0;
+ proc_data->vflip = 0;
+ proc_data->rotate = screeninfo->rotate;
+ proc_data->bgcolor = 0;
+ proc_data->overlay_state = 0;
+ proc_data->lut_transform = PXP_LUT_NONE;
+
+ /*
+ * configure S0 channel parameters
+ * Parameters should match FB format/width/height
+ */
+ if (screeninfo->grayscale) {
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY;
+ if (screeninfo->grayscale == GRAYSCALE_8BIT_INVERTED)
+ proc_data->lut_transform = PXP_LUT_INVERT;
+ } else {
+ switch (screeninfo->bits_per_pixel) {
+ case 16:
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+ break;
+ case 24:
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24;
+ break;
+ case 32:
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32;
+ break;
+ default:
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+ break;
+ }
+ }
+ pxp_conf->s0_param.width = screeninfo->xres_virtual;
+ pxp_conf->s0_param.height = screeninfo->yres;
+ pxp_conf->s0_param.color_key = -1;
+ pxp_conf->s0_param.color_key_enable = false;
+
+ /*
+ * Initialize Output channel parameters
+ * Output is Y-only greyscale
+ * Output width/height will vary based on update region size
+ */
+ pxp_conf->out_param.width = screeninfo->xres;
+ pxp_conf->out_param.height = screeninfo->yres;
+ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+ /*
+ * If HW not yet initialized, check to see if we are being sent
+ * an initialization request.
+ */
+ if (!fb_data->hw_ready) {
+ for (i = 0; i < fb_data->pdata->num_modes; i++) {
+ struct fb_videomode *vmode =
+ fb_data->pdata->epdc_mode[i].vmode;
+ /* Check resolution for a match
+ with supported panel types */
+ if ((screeninfo->xres != vmode->xres) ||
+ (screeninfo->yres != vmode->yres))
+ continue;
+
+ fb_data->cur_mode = &fb_data->pdata->epdc_mode[i];
+
+ /* Found a match - Grab timing params */
+ screeninfo->left_margin = vmode->left_margin;
+ screeninfo->right_margin = vmode->right_margin;
+ screeninfo->upper_margin = vmode->upper_margin;
+ screeninfo->lower_margin = vmode->lower_margin;
+ screeninfo->hsync_len = vmode->hsync_len;
+ screeninfo->vsync_len = vmode->vsync_len;
+
+ /* Initialize EPDC settings and init panel */
+ ret =
+ mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+ if (ret) {
+ dev_err(fb_data->dev, "Failed to load panel waveform data\n");
+ return ret;
+ }
+
+ break;
+ }
+ }
+
+ mxc_epdc_fb_set_fix(info);
+
+ return 0;
+}
+
+static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+ if (!var->xres)
+ var->xres = 1;
+ if (!var->yres)
+ var->yres = 1;
+
+ if (var->xres_virtual < var->xoffset + var->xres)
+ var->xres_virtual = var->xoffset + var->xres;
+ if (var->yres_virtual < var->yoffset + var->yres)
+ var->yres_virtual = var->yoffset + var->yres;
+
+ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+ var->bits_per_pixel = default_bpp;
+
+ switch (var->bits_per_pixel) {
+ case 8:
+ if (var->grayscale != 0) {
+ /*
+ * For 8-bit grayscale, R, G, and B offset are equal.
+ *
+ */
+ var->red.length = 8;
+ var->red.offset = 0;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 0;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ } else {
+ var->red.length = 3;
+ var->red.offset = 5;
+ var->red.msb_right = 0;
+
+ var->green.length = 3;
+ var->green.offset = 2;
+ var->green.msb_right = 0;
+
+ var->blue.length = 2;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ }
+ break;
+ case 16:
+ var->red.length = 5;
+ var->red.offset = 11;
+ var->red.msb_right = 0;
+
+ var->green.length = 6;
+ var->green.offset = 5;
+ var->green.msb_right = 0;
+
+ var->blue.length = 5;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 24:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 32:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 8;
+ var->transp.offset = 24;
+ var->transp.msb_right = 0;
+ break;
+ }
+
+ switch (var->rotate) {
+ case FB_ROTATE_UR:
+ case FB_ROTATE_UD:
+ var->xres = fb_data->native_width;
+ var->yres = fb_data->native_height;
+ break;
+ case FB_ROTATE_CW:
+ case FB_ROTATE_CCW:
+ var->xres = fb_data->native_height;
+ var->yres = fb_data->native_width;
+ break;
+ default:
+ /* Invalid rotation value */
+ var->rotate = 0;
+ dev_dbg(fb_data->dev, "Invalid rotation request\n");
+ return -EINVAL;
+ }
+
+ var->xres_virtual = ALIGN(var->xres, 32);
+ var->yres_virtual = ALIGN(var->yres, 128) * g_num_screens;
+
+ var->height = -1;
+ var->width = -1;
+
+ return 0;
+}
+
+static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp)
+{
+ int i;
+ int index = -1;
+
+ if (fb_data->trt_entries == 0) {
+ dev_err(fb_data->dev,
+ "No TRT exists...using default temp index\n");
+ return TEMP_USE_DEFAULT;
+ }
+
+ /* Search temperature ranges for a match */
+ for (i = 0; i < fb_data->trt_entries - 1; i++) {
+ if ((temp >= fb_data->temp_range_bounds[i])
+ && (temp < fb_data->temp_range_bounds[i+1])) {
+ index = i;
+ break;
+ }
+ }
+
+ if (index < 0) {
+ dev_err(fb_data->dev,
+ "No TRT index match...using default temp index\n");
+ return TEMP_USE_DEFAULT;
+ }
+
+ dev_dbg(fb_data->dev, "Using temperature index %d\n", index);
+
+ return index;
+}
+
+static int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ int temp_index;
+
+ if (temperature != TEMP_USE_AMBIENT) {
+ temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature);
+ epdc_set_temp(temp_index);
+ }
+
+ return 0;
+}
+
+static int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+ dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode);
+
+ if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+ || (auto_mode == AUTO_UPDATE_MODE_REGION_MODE))
+ fb_data->auto_mode = auto_mode;
+ else {
+ dev_err(fb_data->dev, "Invalid auto update mode parameter.\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
+ struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ struct update_data_list *upd_data_list = NULL;
+ struct mxcfb_rect *screen_upd_region; /* Region on screen to update */
+ struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */
+ struct mxcfb_rect pxp_upd_region;
+ u32 src_width;
+ unsigned long flags;
+ int i;
+ u32 offset_from_8, bytes_per_pixel;
+ u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks;
+ u32 pxp_input_offs, pxp_output_offs, pxp_output_shift;
+ int x_start_offs = 0;
+ u32 hist_stat = 0;
+ int temp_index;
+ bool wait_for_power = false;
+
+ int ret;
+
+ /* Has EPDC HW been initialized? */
+ if (!fb_data->hw_ready) {
+ dev_err(fb_data->dev, "Display HW not properly initialized. Aborting update.\n");
+ return -EPERM;
+ }
+
+ /* Check validity of update params */
+ if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) &&
+ (upd_data->update_mode != UPDATE_MODE_FULL)) {
+ dev_err(fb_data->dev,
+ "Update mode 0x%x is invalid. Aborting update.\n",
+ upd_data->update_mode);
+ return -EINVAL;
+ }
+ if ((upd_data->waveform_mode > 255) &&
+ (upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) {
+ dev_err(fb_data->dev,
+ "Update waveform mode 0x%x is invalid. Aborting update.\n",
+ upd_data->waveform_mode);
+ return -EINVAL;
+ }
+ if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->info.var.xres) ||
+ (upd_data->update_region.top + upd_data->update_region.height > fb_data->info.var.yres)) {
+ dev_err(fb_data->dev,
+ "Update region is outside bounds of framebuffer. Aborting update.\n");
+ return -EINVAL;
+ }
+ if (upd_data->use_alt_buffer &&
+ ((upd_data->update_region.width != upd_data->alt_buffer_data.alt_update_region.width) ||
+ (upd_data->update_region.height != upd_data->alt_buffer_data.alt_update_region.height))) {
+ dev_err(fb_data->dev,
+ "Alternate update region dimensions must match screen update region dimensions.\n");
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+ /*
+ * If we are waiting to go into suspend, or the FB is blanked,
+ * we do not accept new updates
+ */
+ if ((fb_data->waiting_for_idle) || (fb_data->blank != FB_BLANK_UNBLANK)) {
+ dev_dbg(fb_data->dev, "EPDC not active. Update request abort.\n");
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return -EPERM;
+ }
+
+ /*
+ * Get available intermediate (PxP output) buffer to hold
+ * processed update region
+ */
+ if (list_empty(&fb_data->upd_buf_free_list->list)) {
+ dev_err(fb_data->dev, "No free intermediate buffers available.\n");
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return -ENOMEM;
+ }
+
+ /* Grab first available buffer and delete it from the free list */
+ upd_data_list =
+ list_entry(fb_data->upd_buf_free_list->list.next,
+ struct update_data_list, list);
+
+ list_del_init(&upd_data_list->list);
+
+ /*
+ * We can release lock on queues now
+ * that we have grabbed the one we need
+ */
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+ /* copy update parameters to the current update data object */
+ memcpy(&upd_data_list->upd_data, upd_data,
+ sizeof(struct mxcfb_update_data));
+ memcpy(&upd_data_list->upd_data.update_region, &upd_data->update_region,
+ sizeof(struct mxcfb_rect));
+
+ /*
+ * Hold on to original screen update region, which we
+ * will ultimately use when telling EPDC where to update on panel
+ */
+ screen_upd_region = &upd_data_list->upd_data.update_region;
+
+ /*
+ * Gotta do a whole bunch of buffer ptr manipulation to
+ * work around HW restrictions for PxP & EPDC
+ */
+
+ /*
+ * Are we using FB or an alternate (overlay)
+ * buffer for source of update?
+ */
+ if (upd_data->use_alt_buffer) {
+ src_width = upd_data->alt_buffer_data.width;
+ src_upd_region = &upd_data->alt_buffer_data.alt_update_region;
+ } else {
+ src_width = fb_data->info.var.xres_virtual;
+ src_upd_region = screen_upd_region;
+ }
+
+ /*
+ * Compute buffer offset to account for
+ * PxP limitation (must read 8x8 pixel blocks)
+ */
+ offset_from_8 = src_upd_region->left & 0x7;
+ bytes_per_pixel = fb_data->info.var.bits_per_pixel/8;
+ if ((offset_from_8 * fb_data->info.var.bits_per_pixel/8 % 4) != 0) {
+ /* Leave a gap between PxP input addr and update region pixels */
+ pxp_input_offs =
+ (src_upd_region->top * src_width + src_upd_region->left)
+ * bytes_per_pixel & 0xFFFFFFFC;
+ /* Update region should change to reflect relative position to input ptr */
+ pxp_upd_region.top = 0;
+ pxp_upd_region.left = (offset_from_8 & 0x3) % bytes_per_pixel;
+ } else {
+ pxp_input_offs =
+ (src_upd_region->top * src_width + src_upd_region->left)
+ * bytes_per_pixel;
+ /* Update region should change to reflect relative position to input ptr */
+ pxp_upd_region.top = 0;
+ pxp_upd_region.left = 0;
+ }
+
+ /*
+ * We want PxP processing region to start at the first pixel
+ * that we have to process in each row, but PxP alignment
+ * restricts the input mem address to be 32-bit aligned
+ *
+ * We work around this by using x_start_offs to offset
+ * to offset from our starting pixel location to the
+ * first pixel that is in the relevant update region
+ * for each row.
+ */
+ x_start_offs = pxp_upd_region.left & 0x7;
+
+ /* Update region to meet 8x8 pixel requirement */
+ pxp_upd_region.width = ALIGN(src_upd_region->width, 8);
+ pxp_upd_region.height = ALIGN(src_upd_region->height, 8);
+ pxp_upd_region.top &= ~0x7;
+ pxp_upd_region.left &= ~0x7;
+
+ switch (fb_data->info.var.rotate) {
+ case FB_ROTATE_UR:
+ default:
+ post_rotation_xcoord = pxp_upd_region.left;
+ post_rotation_ycoord = pxp_upd_region.top;
+ width_pxp_blocks = pxp_upd_region.width;
+ break;
+ case FB_ROTATE_CW:
+ width_pxp_blocks = pxp_upd_region.height;
+ post_rotation_xcoord = width_pxp_blocks - src_upd_region->height;
+ post_rotation_ycoord = pxp_upd_region.left;
+ break;
+ case FB_ROTATE_UD:
+ width_pxp_blocks = pxp_upd_region.width;
+ post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left;
+ post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top;
+ break;
+ case FB_ROTATE_CCW:
+ width_pxp_blocks = pxp_upd_region.height;
+ post_rotation_xcoord = pxp_upd_region.top;
+ post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left;
+ break;
+ }
+
+ pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
+ + post_rotation_xcoord;
+
+ pxp_output_shift = ALIGN(pxp_output_offs, 8) - pxp_output_offs;
+
+ upd_data_list->epdc_offs = pxp_output_offs + pxp_output_shift;
+
+ /* Source address either comes from alternate buffer
+ provided in update data, or from the framebuffer. */
+ if (upd_data->use_alt_buffer)
+ sg_dma_address(&fb_data->sg[0]) =
+ upd_data->alt_buffer_data.phys_addr + pxp_input_offs;
+ else {
+ sg_dma_address(&fb_data->sg[0]) =
+ fb_data->info.fix.smem_start + fb_data->fb_offset
+ + pxp_input_offs;
+ sg_set_page(&fb_data->sg[0],
+ virt_to_page(fb_data->info.screen_base),
+ fb_data->info.fix.smem_len,
+ offset_in_page(fb_data->info.screen_base));
+ }
+
+ /* Update sg[1] to point to output of PxP proc task */
+ sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr + pxp_output_offs;
+ sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr),
+ upd_data_list->size,
+ offset_in_page(upd_data_list->virt_addr));
+
+ mutex_lock(&fb_data->pxp_mutex);
+
+ /* This is a blocking call, so upon return PxP tx should be done */
+ ret = pxp_process_update(fb_data, &pxp_upd_region,
+ x_start_offs);
+ if (ret) {
+ dev_err(fb_data->dev, "Unable to submit PxP update task.\n");
+ mutex_unlock(&fb_data->pxp_mutex);
+ return ret;
+ }
+
+ mutex_unlock(&fb_data->pxp_mutex);
+
+ /* If needed, enable EPDC HW while ePxP is processing */
+ if ((fb_data->power_state == POWER_STATE_OFF)
+ || fb_data->powering_down) {
+ wait_for_power = true;
+ epdc_powerup(fb_data);
+ }
+
+ mutex_lock(&fb_data->pxp_mutex);
+
+ /* This is a blocking call, so upon return PxP tx should be done */
+ ret = pxp_complete_update(fb_data, &hist_stat);
+ if (ret) {
+ dev_err(fb_data->dev, "Unable to complete PxP update task.\n");
+ mutex_unlock(&fb_data->pxp_mutex);
+ return ret;
+ }
+
+ mutex_unlock(&fb_data->pxp_mutex);
+
+ /* Grab lock for queue manipulation and update submission */
+ spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+ /* Update coordinates for rotation */
+ adjust_coordinates(fb_data, &upd_data_list->upd_data.update_region);
+
+ /* Update waveform mode from PxP histogram results */
+ if (upd_data_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO) {
+ if (hist_stat & 0x1)
+ upd_data_list->upd_data.waveform_mode =
+ fb_data->wv_modes.mode_du;
+ else if (hist_stat & 0x2)
+ upd_data_list->upd_data.waveform_mode =
+ fb_data->wv_modes.mode_gc4;
+ else if (hist_stat & 0x4)
+ upd_data_list->upd_data.waveform_mode =
+ fb_data->wv_modes.mode_gc8;
+ else if (hist_stat & 0x8)
+ upd_data_list->upd_data.waveform_mode =
+ fb_data->wv_modes.mode_gc16;
+ else
+ upd_data_list->upd_data.waveform_mode =
+ fb_data->wv_modes.mode_gc32;
+
+ /* Pass selected waveform mode back to user */
+ upd_data->waveform_mode = upd_data_list->upd_data.waveform_mode;
+
+ dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n",
+ hist_stat, upd_data_list->upd_data.waveform_mode);
+ }
+
+ /* If marker specified, associate it with a completion */
+ if (upd_data->update_marker != 0) {
+ /* Find available update marker and set it up */
+ for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+ /* Marker value set to 0 signifies it is not currently in use */
+ if (fb_data->update_marker_array[i].update_marker == 0) {
+ fb_data->update_marker_array[i].update_marker = upd_data->update_marker;
+ init_completion(&fb_data->update_marker_array[i].update_completion);
+ upd_data_list->upd_marker_data = &fb_data->update_marker_array[i];
+ break;
+ }
+ }
+ } else {
+ if (upd_data_list->upd_marker_data)
+ upd_data_list->upd_marker_data->update_marker = 0;
+ }
+
+ upd_data_list->is_collision = false;
+
+ /*
+ * Is the working buffer idle?
+ * If either the working buffer is busy, or there are no LUTs available,
+ * then we return and let the ISR handle the update later
+ */
+ if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) {
+ /* Add processed Y buffer to update list */
+ list_add_tail(&upd_data_list->list,
+ &fb_data->upd_buf_queue->list);
+
+ /* Return and allow the udpate to be submitted by the ISR. */
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return 0;
+ }
+
+ /* Save current update */
+ fb_data->cur_update = upd_data_list;
+
+ /* LUTs are available, so we get one here */
+ upd_data_list->lut_num = epdc_get_next_lut();
+
+ /* Associate LUT with update marker */
+ if (upd_data_list->upd_marker_data)
+ if (upd_data_list->upd_marker_data->update_marker != 0)
+ upd_data_list->upd_marker_data->lut_num = upd_data_list->lut_num;
+
+ /* Mark LUT as containing new update */
+ fb_data->lut_update_type[upd_data_list->lut_num] = LUT_UPDATE_NEW;
+
+ /* Clear status and Enable LUT complete and WB complete IRQs */
+ epdc_working_buf_intr(true);
+ epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+ /* Program EPDC update to process buffer */
+ epdc_set_update_addr(upd_data_list->phys_addr + upd_data_list->epdc_offs);
+ epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top);
+ epdc_set_update_dimensions(screen_upd_region->width, screen_upd_region->height);
+ if (upd_data_list->upd_data.temp != TEMP_USE_AMBIENT) {
+ temp_index = mxc_epdc_fb_get_temp_index(fb_data, upd_data_list->upd_data.temp);
+ epdc_set_temp(temp_index);
+ }
+ epdc_submit_update(upd_data_list->lut_num,
+ upd_data_list->upd_data.waveform_mode,
+ upd_data_list->upd_data.update_mode, false, 0);
+
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+ return 0;
+}
+
+static int mxc_epdc_fb_wait_update_complete(u32 update_marker,
+ struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ int ret;
+ int i;
+
+ /* 0 is an invalid update_marker value */
+ if (update_marker == 0)
+ return -EINVAL;
+
+ /* Wait for completion associated with update_marker requested */
+ for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+ if (fb_data->update_marker_array[i].update_marker == update_marker) {
+ dev_dbg(fb_data->dev, "Waiting for marker %d\n", update_marker);
+ ret = wait_for_completion_timeout(&fb_data->update_marker_array[i].update_completion, msecs_to_jiffies(5000));
+ if (!ret)
+ dev_err(fb_data->dev, "Timed out waiting for update completion\n");
+
+ dev_dbg(fb_data->dev, "marker %d signalled!\n", update_marker);
+
+ /* Reset marker so it can be reused */
+ fb_data->update_marker_array[i].update_marker = 0;
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
+ struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+ fb_data->pwrdown_delay = pwrdown_delay;
+
+ return 0;
+}
+
+static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+{
+ void __user *argp = (void __user *)arg;
+ int ret = -EINVAL;
+
+ switch (cmd) {
+ case MXCFB_SET_WAVEFORM_MODES:
+ {
+ struct mxcfb_waveform_modes modes;
+ struct mxc_epdc_fb_data *fb_data =
+ (struct mxc_epdc_fb_data *)info;
+ if (!copy_from_user(&modes, argp, sizeof(modes))) {
+ memcpy(&fb_data->wv_modes, &modes,
+ sizeof(modes));
+ ret = 0;
+ }
+ break;
+ }
+ case MXCFB_SET_TEMPERATURE:
+ {
+ int temperature;
+ if (!get_user(temperature, (int32_t __user *) arg))
+ ret =
+ mxc_epdc_fb_set_temperature(temperature,
+ info);
+ break;
+ }
+ case MXCFB_SET_AUTO_UPDATE_MODE:
+ {
+ u32 auto_mode = 0;
+ if (!get_user(auto_mode, (__u32 __user *) arg))
+ ret =
+ mxc_epdc_fb_set_auto_update(auto_mode,
+ info);
+ break;
+ }
+ case MXCFB_SEND_UPDATE:
+ {
+ struct mxcfb_update_data upd_data;
+ if (!copy_from_user(&upd_data, argp,
+ sizeof(upd_data))) {
+ ret = mxc_epdc_fb_send_update(&upd_data, info);
+ if (ret == 0 && copy_to_user(argp, &upd_data,
+ sizeof(upd_data)))
+ ret = -EFAULT;
+ } else {
+ ret = -EFAULT;
+ }
+
+ break;
+ }
+ case MXCFB_WAIT_FOR_UPDATE_COMPLETE:
+ {
+ u32 update_marker = 0;
+ if (!get_user(update_marker, (__u32 __user *) arg))
+ ret =
+ mxc_epdc_fb_wait_update_complete(update_marker,
+ info);
+ break;
+ }
+
+ case MXCFB_SET_PWRDOWN_DELAY:
+ {
+ int delay = 0;
+ if (!get_user(delay, (__u32 __user *) arg))
+ ret =
+ mxc_epdc_fb_set_pwrdown_delay(delay, info);
+ break;
+ }
+
+ case MXCFB_GET_PWRDOWN_DELAY:
+ {
+ struct mxc_epdc_fb_data *fb_data =
+ (struct mxc_epdc_fb_data *)info;
+ if (put_user(fb_data->pwrdown_delay,
+ (int __user *)argp))
+ ret = -EFAULT;
+ ret = 0;
+ break;
+ }
+ default:
+ break;
+ }
+ return ret;
+}
+
+static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data,
+ u16 y1, u16 y2)
+{
+ struct mxcfb_update_data update;
+
+ /* Do partial screen update, Update full horizontal lines */
+ update.update_region.left = 0;
+ update.update_region.width = fb_data->info.var.xres;
+ update.update_region.top = y1;
+ update.update_region.height = y2 - y1;
+ update.waveform_mode = WAVEFORM_MODE_AUTO;
+ update.update_mode = UPDATE_MODE_FULL;
+ update.update_marker = 0;
+ update.temp = TEMP_USE_AMBIENT;
+ update.use_alt_buffer = false;
+
+ mxc_epdc_fb_send_update(&update, &fb_data->info);
+}
+
+/* this is called back from the deferred io workqueue */
+static void mxc_epdc_fb_deferred_io(struct fb_info *info,
+ struct list_head *pagelist)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ struct page *page;
+ unsigned long beg, end;
+ int y1, y2, miny, maxy;
+
+ if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE)
+ return;
+
+ miny = INT_MAX;
+ maxy = 0;
+ list_for_each_entry(page, pagelist, lru) {
+ beg = page->index << PAGE_SHIFT;
+ end = beg + PAGE_SIZE - 1;
+ y1 = beg / info->fix.line_length;
+ y2 = end / info->fix.line_length;
+ if (y2 >= info->var.yres)
+ y2 = info->var.yres - 1;
+ if (miny > y1)
+ miny = y1;
+ if (maxy < y2)
+ maxy = y2;
+ }
+
+ mxc_epdc_fb_update_pages(fb_data, miny, maxy);
+}
+
+static void mxc_epdc_fb_disable(struct mxc_epdc_fb_data *fb_data)
+{
+ unsigned long flags;
+ /* Grab queue lock to prevent any new updates from being submitted */
+
+ spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+ /* If any updates in flight, we must wait for them to complete */
+ if (!(list_empty(&fb_data->upd_buf_collision_list->list) &&
+ list_empty(&fb_data->upd_buf_queue->list) &&
+ (fb_data->cur_update == NULL))) {
+ /* Initialize event signalling updates are done */
+ init_completion(&fb_data->updates_done);
+ fb_data->waiting_for_idle = true;
+
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ /* Wait for any currently active updates to complete */
+ wait_for_completion_timeout(&fb_data->updates_done, msecs_to_jiffies(2000));
+ spin_lock_irqsave(&fb_data->queue_lock, flags);
+ fb_data->waiting_for_idle = false;
+ }
+
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+}
+
+static int mxc_epdc_fb_blank(int blank, struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+ dev_dbg(fb_data->dev, "blank = %d\n", blank);
+
+ if (fb_data->blank == blank)
+ return 0;
+
+ fb_data->blank = blank;
+
+ switch (blank) {
+ case FB_BLANK_POWERDOWN:
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ case FB_BLANK_NORMAL:
+ mxc_epdc_fb_disable(fb_data);
+ break;
+ }
+ return 0;
+}
+
+static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ u_int y_bottom;
+
+ dev_dbg(info->device, "%s: var->xoffset %d, info->var.xoffset %d\n",
+ __func__, var->xoffset, info->var.xoffset);
+ /* check if var is valid; also, xpan is not supported */
+ if (!var || (var->xoffset != info->var.xoffset) ||
+ (var->yoffset + var->yres > var->yres_virtual)) {
+ dev_dbg(info->device, "x panning not supported\n");
+ return -EINVAL;
+ }
+
+ if ((info->var.xoffset == var->xoffset) &&
+ (info->var.yoffset == var->yoffset))
+ return 0; /* No change, do nothing */
+
+ y_bottom = var->yoffset;
+
+ if (!(var->vmode & FB_VMODE_YWRAP))
+ y_bottom += var->yres;
+
+ if (y_bottom > info->var.yres_virtual)
+ return -EINVAL;
+
+ fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset)
+ * (var->bits_per_pixel) / 8;
+
+ info->var.xoffset = var->xoffset;
+ info->var.yoffset = var->yoffset;
+
+ if (var->vmode & FB_VMODE_YWRAP)
+ info->var.vmode |= FB_VMODE_YWRAP;
+ else
+ info->var.vmode &= ~FB_VMODE_YWRAP;
+
+ return 0;
+}
+
+static struct fb_ops mxc_epdc_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = mxc_epdc_fb_check_var,
+ .fb_set_par = mxc_epdc_fb_set_par,
+ .fb_setcolreg = mxc_epdc_fb_setcolreg,
+ .fb_pan_display = mxc_epdc_fb_pan_display,
+ .fb_ioctl = mxc_epdc_fb_ioctl,
+ .fb_mmap = mxc_epdc_fb_mmap,
+ .fb_blank = mxc_epdc_fb_blank,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_deferred_io mxc_epdc_fb_defio = {
+ .delay = HZ,
+ .deferred_io = mxc_epdc_fb_deferred_io,
+};
+
+static void epdc_done_work_func(struct work_struct *work)
+{
+ struct mxc_epdc_fb_data *fb_data =
+ container_of(work, struct mxc_epdc_fb_data,
+ epdc_done_work.work);
+ epdc_powerdown(fb_data);
+}
+
+static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data)
+{
+ int count = 0;
+ struct update_data_list *plist;
+
+ /* Count buffers in free buffer list */
+ list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list)
+ count++;
+
+ /* Check to see if all buffers are in this list */
+ if (count == EPDC_MAX_NUM_UPDATES)
+ return true;
+ else
+ return false;
+}
+
+static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id)
+{
+ struct mxc_epdc_fb_data *fb_data = dev_id;
+ struct update_data_list *collision_update;
+ struct mxcfb_rect *next_upd_region;
+ unsigned long flags;
+ int temp_index;
+ u32 luts_completed_mask;
+ u32 temp_mask;
+ u32 lut;
+ bool ignore_collision = false;
+ int i, j;
+
+ /*
+ * If we just completed one-time panel init, bypass
+ * queue handling, clear interrupt and return
+ */
+ if (fb_data->in_init) {
+ if (epdc_is_working_buffer_complete()) {
+ epdc_working_buf_intr(false);
+ epdc_clear_working_buf_irq();
+ dev_dbg(fb_data->dev, "Cleared WB for init update\n");
+ }
+
+ if (epdc_is_lut_complete(0)) {
+ epdc_lut_complete_intr(0, false);
+ epdc_clear_lut_complete_irq(0);
+ fb_data->in_init = false;
+ dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n");
+ }
+
+ return IRQ_HANDLED;
+ }
+
+ if (!(__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)))
+ return IRQ_HANDLED;
+
+ if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) {
+ dev_err(fb_data->dev, "TCE underrun! Panel may lock up.\n");
+ return IRQ_HANDLED;
+ }
+
+ /* Protect access to buffer queues and to update HW */
+ spin_lock_irqsave(&fb_data->queue_lock, flags);
+
+ /* Free any LUTs that have completed */
+ luts_completed_mask = 0;
+ for (i = 0; i < EPDC_NUM_LUTS; i++) {
+ if (!epdc_is_lut_complete(i))
+ continue;
+
+ dev_dbg(fb_data->dev, "\nLUT %d completed\n", i);
+
+ /* Disable IRQ for completed LUT */
+ epdc_lut_complete_intr(i, false);
+
+ /*
+ * Go through all updates in the collision list and
+ * unmask any updates that were colliding with
+ * the completed LUT.
+ */
+ list_for_each_entry(collision_update,
+ &fb_data->upd_buf_collision_list->
+ list, list) {
+ collision_update->collision_mask =
+ collision_update->collision_mask & ~(1 << i);
+ }
+
+ epdc_clear_lut_complete_irq(i);
+
+ luts_completed_mask |= 1 << i;
+
+ fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+ /* Signal completion if anyone waiting on this LUT */
+ for (j = 0; j < EPDC_MAX_NUM_UPDATES; j++) {
+ if (fb_data->update_marker_array[j].lut_num != i)
+ continue;
+
+ /* Signal completion of update */
+ dev_dbg(fb_data->dev,
+ "Signaling marker %d\n",
+ fb_data->update_marker_array[j].update_marker);
+ complete(&fb_data->update_marker_array[j].update_completion);
+ /* Ensure this doesn't get signaled again inadvertently */
+ fb_data->update_marker_array[j].lut_num = INVALID_LUT;
+ }
+ }
+
+ /* Check to see if all updates have completed */
+ if (is_free_list_full(fb_data) &&
+ (fb_data->cur_update == NULL) &&
+ !epdc_any_luts_active()) {
+
+ if (fb_data->pwrdown_delay != FB_POWERDOWN_DISABLE) {
+ /*
+ * Set variable to prevent overlapping
+ * enable/disable requests
+ */
+ fb_data->powering_down = true;
+
+ /* Schedule task to disable EPDC HW until next update */
+ schedule_delayed_work(&fb_data->epdc_done_work,
+ msecs_to_jiffies(fb_data->pwrdown_delay));
+ }
+
+ if (fb_data->waiting_for_idle)
+ complete(&fb_data->updates_done);
+ }
+
+ /* Is Working Buffer busy? */
+ if (epdc_is_working_buffer_busy()) {
+ /* Can't submit another update until WB is done */
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /*
+ * Were we waiting on working buffer?
+ * If so, update queues and check for collisions
+ */
+ if (fb_data->cur_update != NULL) {
+ dev_dbg(fb_data->dev, "\nWorking buffer completed\n");
+
+ /* Was there a collision? */
+ if (epdc_is_collision()) {
+ /* Check list of colliding LUTs, and add to our collision mask */
+ fb_data->cur_update->collision_mask =
+ epdc_get_colliding_luts();
+
+ dev_dbg(fb_data->dev, "\nCollision mask = 0x%x\n",
+ epdc_get_colliding_luts());
+
+ /* Clear collisions that just completed */
+ fb_data->cur_update->collision_mask &= ~luts_completed_mask;
+
+ /*
+ * If this is a re-collision, AND we re-collide
+ * with only new updates, then we don't want
+ * to re-submit it again.
+ */
+ if (fb_data->cur_update->is_collision) {
+ /*
+ * Check whether collided LUTs are
+ * new updates or resubmitted collisions
+ */
+ temp_mask = fb_data->cur_update->collision_mask;
+ lut = 0;
+ while (temp_mask != 0) {
+ if ((temp_mask & 0x1) &&
+ (fb_data->lut_update_type[lut] == LUT_UPDATE_NEW)) {
+ dev_dbg(fb_data->dev, "Ignoring collision with new update.\n");
+ ignore_collision = true;
+ break;
+ }
+ lut++;
+ temp_mask = temp_mask >> 1;
+ }
+ }
+
+ if (ignore_collision) {
+ /* Add to free buffer list */
+ list_add_tail(&fb_data->cur_update->list,
+ &fb_data->upd_buf_free_list->list);
+ } else {
+ /*
+ * If update has a marker, clear the LUT, since we
+ * don't want to signal that it is complete.
+ */
+ if (fb_data->cur_update->upd_marker_data)
+ if (fb_data->cur_update->upd_marker_data->update_marker != 0)
+ fb_data->cur_update->upd_marker_data->lut_num = INVALID_LUT;
+
+ fb_data->cur_update->is_collision = true;
+
+ /* Move to collision list */
+ list_add_tail(&fb_data->cur_update->list,
+ &fb_data->upd_buf_collision_list->list);
+ }
+ } else {
+ /* Add to free buffer list */
+ list_add_tail(&fb_data->cur_update->list,
+ &fb_data->upd_buf_free_list->list);
+ }
+ /* Clear current update */
+ fb_data->cur_update = NULL;
+
+ /* Clear IRQ for working buffer */
+ epdc_working_buf_intr(false);
+ epdc_clear_working_buf_irq();
+ }
+
+ /* Check to see if any LUTs are free */
+ if (!epdc_any_luts_available()) {
+ dev_dbg(fb_data->dev, "No luts available.\n");
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /*
+ * Are any of our collision updates able to go now?
+ * Go through all updates in the collision list and check to see
+ * if the collision mask has been fully cleared
+ */
+ list_for_each_entry(collision_update,
+ &fb_data->upd_buf_collision_list->list, list) {
+
+ if (collision_update->collision_mask != 0)
+ continue;
+
+ dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
+ /*
+ * We have a collision cleared, so select it
+ * and we will retry the update
+ */
+ fb_data->cur_update = collision_update;
+ list_del_init(&fb_data->cur_update->list);
+ break;
+ }
+
+ /*
+ * If we didn't find a collision update ready to go,
+ * we try to grab one from the update queue
+ */
+ if (fb_data->cur_update == NULL) {
+ /* Is update list empty? */
+ if (list_empty(&fb_data->upd_buf_queue->list)) {
+ dev_dbg(fb_data->dev, "No pending updates.\n");
+
+ /* No updates pending, so we are done */
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+ return IRQ_HANDLED;
+ } else {
+ dev_dbg(fb_data->dev, "Found a pending update!\n");
+
+ /* Process next item in update list */
+ fb_data->cur_update =
+ list_entry(fb_data->upd_buf_queue->list.next,
+ struct update_data_list, list);
+ list_del_init(&fb_data->cur_update->list);
+ }
+ }
+
+ /* LUTs are available, so we get one here */
+ fb_data->cur_update->lut_num = epdc_get_next_lut();
+
+ /* Associate LUT with update marker */
+ if ((fb_data->cur_update->upd_marker_data)
+ && (fb_data->cur_update->upd_marker_data->update_marker != 0))
+ fb_data->cur_update->upd_marker_data->lut_num =
+ fb_data->cur_update->lut_num;
+
+ /* Mark LUT as containing new update */
+ if (fb_data->cur_update->is_collision)
+ fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_COLLISION;
+ else
+ fb_data->lut_update_type[fb_data->cur_update->lut_num] = LUT_UPDATE_NEW;
+
+ /* Enable Collision and WB complete IRQs */
+ epdc_working_buf_intr(true);
+ epdc_lut_complete_intr(fb_data->cur_update->lut_num, true);
+
+ /* Program EPDC update to process buffer */
+ next_upd_region = &fb_data->cur_update->upd_data.update_region;
+ if (fb_data->cur_update->upd_data.temp != TEMP_USE_AMBIENT) {
+ temp_index = mxc_epdc_fb_get_temp_index(fb_data, fb_data->cur_update->upd_data.temp);
+ epdc_set_temp(temp_index);
+ }
+ epdc_set_update_addr(fb_data->cur_update->phys_addr + fb_data->cur_update->epdc_offs);
+ epdc_set_update_coord(next_upd_region->left, next_upd_region->top);
+ epdc_set_update_dimensions(next_upd_region->width,
+ next_upd_region->height);
+ epdc_submit_update(fb_data->cur_update->lut_num,
+ fb_data->cur_update->upd_data.waveform_mode,
+ fb_data->cur_update->upd_data.update_mode, false, 0);
+
+ /* Release buffer queues */
+ spin_unlock_irqrestore(&fb_data->queue_lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static void draw_mode0(struct mxc_epdc_fb_data *fb_data)
+{
+ u32 *upd_buf_ptr;
+ int i;
+
+ upd_buf_ptr = (u32 *)fb_data->info.screen_base;
+
+ epdc_working_buf_intr(true);
+ epdc_lut_complete_intr(0, true);
+ fb_data->in_init = true;
+
+ /* Program EPDC update to process buffer */
+ epdc_set_update_addr(fb_data->phys_start);
+ epdc_set_update_coord(0, 0);
+ epdc_set_update_dimensions(fb_data->info.var.xres,
+ fb_data->info.var.yres);
+ epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL, true, 0xFF);
+
+ dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n");
+
+ /* Will timeout after ~4-5 seconds */
+
+ for (i = 0; i < 40; i++) {
+ if (!epdc_is_lut_active(0)) {
+ dev_dbg(fb_data->dev, "Mode0 init complete\n");
+ return;
+ }
+ msleep(100);
+ }
+
+ dev_err(fb_data->dev, "Mode0 init failed!\n");
+
+ return;
+}
+
+static int mxc_epdc_fb_init_hw(struct fb_info *info)
+{
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+ const struct firmware *fw;
+ char *fw_str = "imx/epdc";
+ struct mxcfb_update_data update;
+ struct mxcfb_waveform_data_file *wv_file;
+ int wv_data_offs;
+ int ret;
+ int i;
+
+ /*
+ * Create fw search string based on ID string in selected videomode.
+ * Format is "imx/epdc_[panel string].fw"
+ */
+ if (fb_data->cur_mode) {
+ strcat(fw_str, "_");
+ strcat(fw_str, fb_data->cur_mode->vmode->name);
+ strcat(fw_str, ".fw");
+ }
+
+ ret = request_firmware(&fw, fw_str, fb_data->dev);
+ if (ret) {
+ printk(KERN_ERR "Failed to load image imx/epdc.ihex err %d\n",
+ ret);
+ return ret;
+ }
+
+ wv_file = (struct mxcfb_waveform_data_file *)fw->data;
+
+ /* Get size and allocate temperature range table */
+ fb_data->trt_entries = wv_file->wdh.trc + 1;
+ fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL);
+
+ for (i = 0; i < fb_data->trt_entries; i++)
+ dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i));
+
+ /* Copy TRT data */
+ memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries);
+
+ /* Get offset and size for waveform data */
+ wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1;
+ fb_data->waveform_buffer_size = fw->size - wv_data_offs;
+
+ /* Allocate memory for waveform data */
+ fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev,
+ fb_data->waveform_buffer_size,
+ &fb_data->waveform_buffer_phys,
+ GFP_DMA);
+ if (fb_data->waveform_buffer_virt == NULL) {
+ dev_err(fb_data->dev, "Can't allocate mem for waveform!\n");
+ ret = -ENOMEM;
+ }
+
+ memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs,
+ fb_data->waveform_buffer_size);
+
+ release_firmware(fw);
+
+ /* Enable clocks to access EPDC regs */
+ clk_enable(fb_data->epdc_clk_axi);
+
+ /* Enable pix clk for EPDC */
+ clk_enable(fb_data->epdc_clk_pix);
+ clk_set_rate(fb_data->epdc_clk_pix, fb_data->cur_mode->vmode->pixclock);
+
+ epdc_init_sequence(fb_data);
+
+ /* Enable clocks to access EPDC regs */
+ clk_disable(fb_data->epdc_clk_axi);
+ clk_disable(fb_data->epdc_clk_pix);
+
+ fb_data->hw_ready = true;
+
+ update.update_region.left = 0;
+ update.update_region.width = info->var.xres;
+ update.update_region.top = 0;
+ update.update_region.height = info->var.yres;
+ update.update_mode = UPDATE_MODE_FULL;
+ update.waveform_mode = WAVEFORM_MODE_AUTO;
+ update.update_marker = INIT_UPDATE_MARKER;
+ update.temp = TEMP_USE_AMBIENT;
+ update.use_alt_buffer = false;
+
+ mxc_epdc_fb_send_update(&update, info);
+
+ /* Block on initial update */
+ ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+ if (ret < 0)
+ dev_err(fb_data->dev,
+ "Wait for update complete failed. Error = 0x%x", ret);
+
+ return 0;
+}
+
+static ssize_t store_update(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mxcfb_update_data update;
+ struct fb_info *info = dev_get_drvdata(device);
+ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
+
+ if (strncmp(buf, "direct", 6) == 0)
+ update.waveform_mode = fb_data->wv_modes.mode_du;
+ else if (strncmp(buf, "gc16", 4) == 0)
+ update.waveform_mode = fb_data->wv_modes.mode_gc16;
+ else if (strncmp(buf, "gc4", 3) == 0)
+ update.waveform_mode = fb_data->wv_modes.mode_gc4;
+
+ /* Now, request full screen update */
+ update.update_region.left = 0;
+ update.update_region.width = info->var.xres;
+ update.update_region.top = 0;
+ update.update_region.height = info->var.yres;
+ update.update_mode = UPDATE_MODE_FULL;
+ update.temp = TEMP_USE_AMBIENT;
+ update.update_marker = 0;
+ update.use_alt_buffer = false;
+
+ mxc_epdc_fb_send_update(&update, info);
+
+ return count;
+}
+
+static struct device_attribute fb_attrs[] = {
+ __ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update),
+};
+
+int __devinit mxc_epdc_fb_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct mxc_epdc_fb_data *fb_data;
+ struct resource *res;
+ struct fb_info *info;
+ char *options, *opt;
+ char *panel_str = NULL;
+ char name[] = "mxcepdcfb";
+ struct fb_videomode *vmode;
+ int xres_virt, yres_virt, buf_size;
+ struct fb_var_screeninfo *var_info;
+ struct fb_fix_screeninfo *fix_info;
+ struct pxp_config_data *pxp_conf;
+ struct pxp_proc_data *proc_data;
+ struct scatterlist *sg;
+ struct update_data_list *upd_list;
+ struct update_data_list *plist, *temp_list;
+ int i;
+ unsigned long x_mem_size = 0;
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+ struct mxcfb_update_data update;
+#endif
+
+ fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc(
+ sizeof(struct mxc_epdc_fb_data), &pdev->dev);
+ if (fb_data == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* Get platform data and check validity */
+ fb_data->pdata = pdev->dev.platform_data;
+ if ((fb_data->pdata == NULL) || (fb_data->pdata->num_modes < 1)
+ || (fb_data->pdata->epdc_mode == NULL)
+ || (fb_data->pdata->epdc_mode->vmode == NULL)) {
+ ret = -EINVAL;
+ goto out_fbdata;
+ }
+
+ if (fb_get_options(name, &options)) {
+ ret = -ENODEV;
+ goto out_fbdata;
+ }
+
+ if (options)
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+
+ if (!strncmp(opt, "bpp=", 4))
+ fb_data->default_bpp =
+ simple_strtoul(opt + 4, NULL, 0);
+ else if (!strncmp(opt, "x_mem=", 6))
+ x_mem_size =
+ simple_strtoul(opt + 6, NULL, 0);
+ else
+ panel_str = opt;
+ }
+
+ fb_data->dev = &pdev->dev;
+
+ if (!fb_data->default_bpp)
+ fb_data->default_bpp = 16;
+
+ /* Set default (first defined mode) before searching for a match */
+ fb_data->cur_mode = &fb_data->pdata->epdc_mode[0];
+
+ if (panel_str)
+ for (i = 0; i < fb_data->pdata->num_modes; i++)
+ if (!strcmp(fb_data->pdata->epdc_mode[i].vmode->name,
+ panel_str)) {
+ fb_data->cur_mode =
+ &fb_data->pdata->epdc_mode[i];
+ break;
+ }
+
+ vmode = fb_data->cur_mode->vmode;
+
+ platform_set_drvdata(pdev, fb_data);
+ info = &fb_data->info;
+
+ /* Allocate color map for the FB */
+ ret = fb_alloc_cmap(&info->cmap, 256, 0);
+ if (ret)
+ goto out_fbdata;
+
+ dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n",
+ fb_data->cur_mode->vmode->xres,
+ fb_data->cur_mode->vmode->yres, fb_data->default_bpp);
+
+ /*
+ * GPU alignment restrictions dictate framebuffer parameters:
+ * - 32-byte alignment for buffer width
+ * - 128-byte alignment for buffer height
+ * => 4K buffer alignment for buffer start
+ */
+ xres_virt = ALIGN(vmode->xres, 32);
+ yres_virt = ALIGN(vmode->yres, 128);
+ buf_size = xres_virt * yres_virt * fb_data->default_bpp/8;
+
+ if (x_mem_size > 0)
+ g_num_screens = NUM_SCREENS_X;
+
+ fb_data->map_size = PAGE_ALIGN(buf_size) * g_num_screens;
+ dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ ret = -ENODEV;
+ goto out_cmap;
+ }
+
+ epdc_base = ioremap(res->start, SZ_4K);
+ if (epdc_base == NULL) {
+ ret = -ENOMEM;
+ goto out_cmap;
+ }
+
+ /* Allocate FB memory */
+ info->screen_base = dma_alloc_writecombine(&pdev->dev,
+ fb_data->map_size,
+ &fb_data->phys_start,
+ GFP_KERNEL);
+
+ if (info->screen_base == NULL) {
+ ret = -ENOMEM;
+ goto out_mapregs;
+ }
+ dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base,
+ fb_data->phys_start);
+
+ var_info = &info->var;
+
+ var_info->activate = FB_ACTIVATE_TEST;
+ var_info->bits_per_pixel = fb_data->default_bpp;
+ var_info->xres = vmode->xres;
+ var_info->yres = vmode->yres;
+ var_info->xres_virtual = xres_virt;
+ /* Additional screens allow for panning and buffer flipping */
+ var_info->yres_virtual = yres_virt * g_num_screens;
+
+ var_info->pixclock = vmode->pixclock;
+ var_info->left_margin = vmode->left_margin;
+ var_info->right_margin = vmode->right_margin;
+ var_info->upper_margin = vmode->upper_margin;
+ var_info->lower_margin = vmode->lower_margin;
+ var_info->hsync_len = vmode->hsync_len;
+ var_info->vsync_len = vmode->vsync_len;
+ var_info->vmode = FB_VMODE_NONINTERLACED;
+
+ switch (fb_data->default_bpp) {
+ case 32:
+ case 24:
+ var_info->red.offset = 16;
+ var_info->red.length = 8;
+ var_info->green.offset = 8;
+ var_info->green.length = 8;
+ var_info->blue.offset = 0;
+ var_info->blue.length = 8;
+ break;
+
+ case 16:
+ var_info->red.offset = 11;
+ var_info->red.length = 5;
+ var_info->green.offset = 5;
+ var_info->green.length = 6;
+ var_info->blue.offset = 0;
+ var_info->blue.length = 5;
+ break;
+
+ default:
+ dev_err(&pdev->dev, "unsupported bitwidth %d\n",
+ fb_data->default_bpp);
+ ret = -EINVAL;
+ goto out_dma_fb;
+ }
+
+ fix_info = &info->fix;
+
+ strcpy(fix_info->id, "mxc_epdc_fb");
+ fix_info->type = FB_TYPE_PACKED_PIXELS;
+ fix_info->visual = FB_VISUAL_TRUECOLOR;
+ fix_info->xpanstep = 0;
+ fix_info->ypanstep = 0;
+ fix_info->ywrapstep = 0;
+ fix_info->accel = FB_ACCEL_NONE;
+ fix_info->smem_start = fb_data->phys_start;
+ fix_info->smem_len = fb_data->map_size;
+ fix_info->ypanstep = 0;
+
+ fb_data->native_width = vmode->xres;
+ fb_data->native_height = vmode->yres;
+
+ info->fbops = &mxc_epdc_fb_ops;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->pseudo_palette = fb_data->pseudo_palette;
+ info->screen_size = info->fix.smem_len;
+ fb_data->par = NULL;
+ info->flags = FBINFO_FLAG_DEFAULT;
+
+ mxc_epdc_fb_set_fix(info);
+
+ fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE;
+
+ init_waitqueue_head(&fb_data->vsync_wait_q);
+ fb_data->vsync_count = 0;
+
+ fb_data->fb_offset = 0;
+
+ /* Allocate head objects for our lists */
+ fb_data->upd_buf_queue =
+ kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+ fb_data->upd_buf_collision_list =
+ kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+ fb_data->upd_buf_free_list =
+ kzalloc(sizeof(struct update_data_list), GFP_KERNEL);
+ if ((fb_data->upd_buf_queue == NULL) || (fb_data->upd_buf_free_list == NULL)
+ || (fb_data->upd_buf_collision_list == NULL)) {
+ ret = -ENOMEM;
+ goto out_dma_fb;
+ }
+
+ /*
+ * Initialize lists for update requests, update collisions,
+ * and available update (PxP output) buffers
+ */
+ INIT_LIST_HEAD(&fb_data->upd_buf_queue->list);
+ INIT_LIST_HEAD(&fb_data->upd_buf_free_list->list);
+ INIT_LIST_HEAD(&fb_data->upd_buf_collision_list->list);
+
+ /* Allocate update buffers and add them to the list */
+ for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+ upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL);
+ if (upd_list == NULL) {
+ ret = -ENOMEM;
+ goto out_upd_buffers;
+ }
+
+ /* Clear update data structure */
+ memset(&upd_list->upd_data, 0,
+ sizeof(struct mxcfb_update_data));
+
+ /*
+ * Each update buffer is 1 byte per pixel, and can
+ * be as big as the full-screen frame buffer
+ */
+ upd_list->size = info->var.xres * info->var.yres;
+
+ /* Allocate memory for PxP output buffer */
+ upd_list->virt_addr =
+ dma_alloc_coherent(fb_data->info.device, upd_list->size,
+ &upd_list->phys_addr, GFP_DMA);
+ if (upd_list->virt_addr == NULL) {
+ kfree(upd_list);
+ ret = -ENOMEM;
+ goto out_upd_buffers;
+ }
+
+ /* Add newly allocated buffer to free list */
+ list_add(&upd_list->list, &fb_data->upd_buf_free_list->list);
+
+ dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n",
+ upd_list->size, upd_list->phys_addr);
+ }
+
+ fb_data->working_buffer_size = vmode->yres * vmode->xres * 2;
+ /* Allocate memory for EPDC working buffer */
+ fb_data->working_buffer_virt =
+ dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size,
+ &fb_data->working_buffer_phys, GFP_DMA);
+ if (fb_data->working_buffer_virt == NULL) {
+ dev_err(&pdev->dev, "Can't allocate mem for working buf!\n");
+ ret = -ENOMEM;
+ goto out_upd_buffers;
+ }
+
+ /* Initialize EPDC pins */
+ if (fb_data->pdata->get_pins)
+ fb_data->pdata->get_pins();
+
+ fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi");
+ fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix");
+
+ fb_data->in_init = false;
+
+ fb_data->hw_ready = false;
+
+ /*
+ * Set default waveform mode values.
+ * Should be overwritten via ioctl.
+ */
+ fb_data->wv_modes.mode_init = 0;
+ fb_data->wv_modes.mode_du = 1;
+ fb_data->wv_modes.mode_gc4 = 3;
+ fb_data->wv_modes.mode_gc8 = 2;
+ fb_data->wv_modes.mode_gc16 = 2;
+ fb_data->wv_modes.mode_gc32 = 2;
+
+ /* Initialize markers */
+ for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) {
+ fb_data->update_marker_array[i].update_marker = 0;
+ fb_data->update_marker_array[i].lut_num = INVALID_LUT;
+ }
+
+ /* Initialize all LUTs to inactive */
+ for (i = 0; i < EPDC_NUM_LUTS; i++)
+ fb_data->lut_update_type[i] = LUT_UPDATE_NONE;
+
+ /* Retrieve EPDC IRQ num */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "cannot get IRQ resource\n");
+ ret = -ENODEV;
+ goto out_dma_work_buf;
+ }
+ fb_data->epdc_irq = res->start;
+
+ /* Register IRQ handler */
+ ret = request_irq(fb_data->epdc_irq, mxc_epdc_irq_handler, 0,
+ "fb_dma", fb_data);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
+ fb_data->epdc_irq, ret);
+ ret = -ENODEV;
+ goto out_dma_work_buf;
+ }
+
+ INIT_DELAYED_WORK(&fb_data->epdc_done_work, epdc_done_work_func);
+
+ info->fbdefio = &mxc_epdc_fb_defio;
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+ fb_deferred_io_init(info);
+#endif
+
+ /* get pmic regulators */
+ fb_data->display_regulator = regulator_get(NULL, "DISPLAY");
+ if (IS_ERR(fb_data->display_regulator)) {
+ dev_err(&pdev->dev, "Unable to get display PMIC regulator."
+ "err = 0x%x\n", (int)fb_data->display_regulator);
+ ret = -ENODEV;
+ goto out_irq;
+ }
+ fb_data->vcom_regulator = regulator_get(NULL, "VCOM");
+ if (IS_ERR(fb_data->vcom_regulator)) {
+ regulator_put(fb_data->display_regulator);
+ dev_err(&pdev->dev, "Unable to get VCOM regulator."
+ "err = 0x%x\n", (int)fb_data->vcom_regulator);
+ ret = -ENODEV;
+ goto out_irq;
+ }
+
+ if (device_create_file(info->dev, &fb_attrs[0]))
+ dev_err(&pdev->dev, "Unable to create file from fb_attrs\n");
+
+ fb_data->cur_update = NULL;
+
+ spin_lock_init(&fb_data->queue_lock);
+
+ mutex_init(&fb_data->pxp_mutex);
+
+ mutex_init(&fb_data->power_mutex);
+
+ /* PxP DMA interface */
+ dmaengine_get();
+
+ /*
+ * Fill out PxP config data structure based on FB info and
+ * processing tasks required
+ */
+ pxp_conf = &fb_data->pxp_conf;
+ proc_data = &pxp_conf->proc_data;
+
+ /* Initialize non-channel-specific PxP parameters */
+ proc_data->drect.left = proc_data->srect.left = 0;
+ proc_data->drect.top = proc_data->srect.top = 0;
+ proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres;
+ proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres;
+ proc_data->scaling = 0;
+ proc_data->hflip = 0;
+ proc_data->vflip = 0;
+ proc_data->rotate = 0;
+ proc_data->bgcolor = 0;
+ proc_data->overlay_state = 0;
+ proc_data->lut_transform = PXP_LUT_NONE;
+
+ /*
+ * We initially configure PxP for RGB->YUV conversion,
+ * and only write out Y component of the result.
+ */
+
+ /*
+ * Initialize S0 channel parameters
+ * Parameters should match FB format/width/height
+ */
+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
+ pxp_conf->s0_param.width = fb_data->info.var.xres_virtual;
+ pxp_conf->s0_param.height = fb_data->info.var.yres;
+ pxp_conf->s0_param.color_key = -1;
+ pxp_conf->s0_param.color_key_enable = false;
+
+ /*
+ * Initialize OL0 channel parameters
+ * No overlay will be used for PxP operation
+ */
+ for (i = 0; i < 8; i++) {
+ pxp_conf->ol_param[i].combine_enable = false;
+ pxp_conf->ol_param[i].width = 0;
+ pxp_conf->ol_param[i].height = 0;
+ pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
+ pxp_conf->ol_param[i].color_key_enable = false;
+ pxp_conf->ol_param[i].color_key = -1;
+ pxp_conf->ol_param[i].global_alpha_enable = false;
+ pxp_conf->ol_param[i].global_alpha = 0;
+ pxp_conf->ol_param[i].local_alpha_enable = false;
+ }
+
+ /*
+ * Initialize Output channel parameters
+ * Output is Y-only greyscale
+ * Output width/height will vary based on update region size
+ */
+ pxp_conf->out_param.width = fb_data->info.var.xres;
+ pxp_conf->out_param.height = fb_data->info.var.yres;
+ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
+
+ /*
+ * Ensure this is set to NULL here...we will initialize pxp_chan
+ * later in our thread.
+ */
+ fb_data->pxp_chan = NULL;
+
+ /* Initialize Scatter-gather list containing 2 buffer addresses. */
+ sg = fb_data->sg;
+ sg_init_table(sg, 2);
+
+ /*
+ * For use in PxP transfers:
+ * sg[0] holds the FB buffer pointer
+ * sg[1] holds the Output buffer pointer (configured before TX request)
+ */
+ sg_dma_address(&sg[0]) = info->fix.smem_start;
+ sg_set_page(&sg[0], virt_to_page(info->screen_base),
+ info->fix.smem_len, offset_in_page(info->screen_base));
+
+ fb_data->waiting_for_idle = false;
+ fb_data->blank = FB_BLANK_UNBLANK;
+ fb_data->power_state = POWER_STATE_OFF;
+ fb_data->powering_down = false;
+ fb_data->pwrdown_delay = 0;
+
+ /* Register FB */
+ ret = register_framebuffer(info);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "register_framebuffer failed with error %d\n", ret);
+ goto out_dmaengine;
+ }
+
+#ifdef DEFAULT_PANEL_HW_INIT
+ ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to initialize HW!\n");
+ }
+#endif
+
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+ /* If FB console included, update display to show logo */
+ update.update_region.left = 0;
+ update.update_region.width = info->var.xres;
+ update.update_region.top = 0;
+ update.update_region.height = info->var.yres;
+ update.update_mode = UPDATE_MODE_PARTIAL;
+ update.waveform_mode = WAVEFORM_MODE_AUTO;
+ update.update_marker = INIT_UPDATE_MARKER;
+ update.temp = TEMP_USE_AMBIENT;
+ update.use_alt_buffer = false;
+
+ mxc_epdc_fb_send_update(&update, info);
+
+ ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info);
+ if (ret < 0)
+ dev_err(fb_data->dev,
+ "Wait for update complete failed. Error = 0x%x", ret);
+#endif
+
+ goto out;
+
+out_dmaengine:
+ dmaengine_put();
+out_irq:
+ free_irq(fb_data->epdc_irq, fb_data);
+out_dma_work_buf:
+ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
+ fb_data->working_buffer_virt, fb_data->working_buffer_phys);
+ if (fb_data->pdata->put_pins)
+ fb_data->pdata->put_pins();
+out_upd_buffers:
+ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+ list_del(&plist->list);
+ dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+ plist->phys_addr);
+ kfree(plist);
+ }
+out_dma_fb:
+ dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base,
+ fb_data->phys_start);
+
+out_mapregs:
+ iounmap(epdc_base);
+out_cmap:
+ fb_dealloc_cmap(&info->cmap);
+out_fbdata:
+ kfree(fb_data);
+out:
+ return ret;
+}
+
+static int mxc_epdc_fb_remove(struct platform_device *pdev)
+{
+ struct update_data_list *plist, *temp_list;
+ struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
+
+ mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
+
+ regulator_put(fb_data->display_regulator);
+ regulator_put(fb_data->vcom_regulator);
+
+ unregister_framebuffer(&fb_data->info);
+ free_irq(fb_data->epdc_irq, fb_data);
+
+ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
+ fb_data->working_buffer_virt,
+ fb_data->working_buffer_phys);
+ if (fb_data->waveform_buffer_virt != NULL)
+ dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size,
+ fb_data->waveform_buffer_virt,
+ fb_data->waveform_buffer_phys);
+ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) {
+ list_del(&plist->list);
+ dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr,
+ plist->phys_addr);
+ kfree(plist);
+ }
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+ fb_deferred_io_cleanup(&fb_data->info);
+#endif
+
+ dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base,
+ fb_data->phys_start);
+
+ if (fb_data->pdata->put_pins)
+ fb_data->pdata->put_pins();
+
+ /* Release PxP-related resources */
+ if (fb_data->pxp_chan != NULL)
+ dma_release_channel(&fb_data->pxp_chan->dma_chan);
+
+ dmaengine_put();
+
+ iounmap(epdc_base);
+
+#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
+ fb_deferred_io_cleanup(&fb_data->info);
+#endif
+ fb_dealloc_cmap(&fb_data->info.cmap);
+
+ framebuffer_release(&fb_data->info);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_epdc_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
+ if (ret)
+ goto out;
+
+out:
+ return ret;
+}
+
+static int mxc_epdc_fb_resume(struct platform_device *pdev)
+{
+ struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
+
+ mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
+ return 0;
+}
+#else
+#define mxc_epdc_fb_suspend NULL
+#define mxc_epdc_fb_resume NULL
+#endif
+
+static struct platform_driver mxc_epdc_fb_driver = {
+ .probe = mxc_epdc_fb_probe,
+ .remove = mxc_epdc_fb_remove,
+ .suspend = mxc_epdc_fb_suspend,
+ .resume = mxc_epdc_fb_resume,
+ .driver = {
+ .name = "mxc_epdc_fb",
+ .owner = THIS_MODULE,
+ },
+};
+
+/* Callback function triggered after PxP receives an EOF interrupt */
+static void pxp_dma_done(void *arg)
+{
+ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
+ struct dma_chan *chan = tx_desc->txd.chan;
+ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
+ struct mxc_epdc_fb_data *fb_data = pxp_chan->client;
+
+ /* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */
+ complete(&fb_data->pxp_tx_cmpl);
+}
+
+/* Function to request PXP DMA channel */
+static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data)
+{
+ dma_cap_mask_t mask;
+ struct dma_chan *chan;
+
+ /*
+ * Request a free channel
+ */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ dma_cap_set(DMA_PRIVATE, mask);
+ chan = dma_request_channel(mask, NULL, NULL);
+ if (!chan) {
+ dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(fb_data->dev, "Successfully received channel.\n");
+
+ fb_data->pxp_chan = to_pxp_channel(chan);
+
+ fb_data->pxp_chan->client = fb_data;
+
+ init_completion(&fb_data->pxp_tx_cmpl);
+
+ return 0;
+}
+
+/*
+ * Function to call PxP DMA driver and send our latest FB update region
+ * through the PxP and out to an intermediate buffer.
+ * Note: This is a blocking call, so upon return the PxP tx should be complete.
+ */
+static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
+ struct mxcfb_rect *update_region,
+ int x_start_offs)
+{
+ dma_cookie_t cookie;
+ struct scatterlist *sg = fb_data->sg;
+ struct dma_chan *dma_chan;
+ struct pxp_tx_desc *desc;
+ struct dma_async_tx_descriptor *txd;
+ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
+ struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data;
+ int i, ret;
+ int length;
+
+ dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n");
+
+ /* First, check to see that we have acquired a PxP Channel object */
+ if (fb_data->pxp_chan == NULL) {
+ /*
+ * PxP Channel has not yet been created and initialized,
+ * so let's go ahead and try
+ */
+ ret = pxp_chan_init(fb_data);
+ if (ret) {
+ /*
+ * PxP channel init failed, and we can't use the
+ * PxP until the PxP DMA driver has loaded, so we abort
+ */
+ dev_err(fb_data->dev, "PxP chan init failed\n");
+ return -ENODEV;
+ }
+ }
+
+ /*
+ * Init completion, so that we
+ * can be properly informed of the completion
+ * of the PxP task when it is done.
+ */
+ init_completion(&fb_data->pxp_tx_cmpl);
+
+ dev_dbg(fb_data->dev, "sg[0] = 0x%x, sg[1] = 0x%x\n",
+ sg_dma_address(&sg[0]), sg_dma_address(&sg[1]));
+
+ dma_chan = &fb_data->pxp_chan->dma_chan;
+
+ txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
+ DMA_TO_DEVICE,
+ DMA_PREP_INTERRUPT);
+ if (!txd) {
+ dev_err(fb_data->info.device,
+ "Error preparing a DMA transaction descriptor.\n");
+ return -EIO;
+ }
+
+ txd->callback_param = txd;
+ txd->callback = pxp_dma_done;
+
+ /*
+ * Configure PxP for processing of new update region
+ * The rest of our config params were set up in
+ * probe() and should not need to be changed.
+ */
+ proc_data->srect.top = update_region->top;
+ proc_data->srect.left = update_region->left + x_start_offs;
+ proc_data->srect.width = update_region->width;
+ proc_data->srect.height = update_region->height;
+
+ /*
+ * Because only YUV/YCbCr image can be scaled, configure
+ * drect equivalent to srect, as such do not perform scaling.
+ */
+ proc_data->drect.top = 0;
+ proc_data->drect.left = 0;
+ proc_data->drect.width = proc_data->srect.width;
+ proc_data->drect.height = proc_data->srect.height;
+
+ /* PXP expects rotation in terms of degrees */
+ proc_data->rotate = fb_data->info.var.rotate * 90;
+ if (proc_data->rotate > 270)
+ proc_data->rotate = 0;
+
+ pxp_conf->out_param.width = update_region->width;
+ pxp_conf->out_param.height = update_region->height;
+
+ desc = to_tx_desc(txd);
+ length = desc->len;
+ for (i = 0; i < length; i++) {
+ if (i == 0) {/* S0 */
+ memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data));
+ pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
+ memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
+ sizeof(struct pxp_layer_param));
+ } else if (i == 1) {
+ pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
+ memcpy(&desc->layer_param.out_param, &pxp_conf->out_param,
+ sizeof(struct pxp_layer_param));
+ }
+ /* TODO: OverLay */
+
+ desc = desc->next;
+ }
+
+ /* Submitting our TX starts the PxP processing task */
+ cookie = txd->tx_submit(txd);
+ dev_dbg(fb_data->info.device, "%d: Submit %p #%d\n", __LINE__, txd,
+ cookie);
+ if (cookie < 0) {
+ dev_err(fb_data->info.device, "Error sending FB through PxP\n");
+ return -EIO;
+ }
+
+ fb_data->txd = txd;
+
+ /* trigger ePxP */
+ dma_async_issue_pending(dma_chan);
+
+ return 0;
+}
+
+static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat)
+{
+ int ret;
+ /*
+ * Wait for completion event, which will be set
+ * through our TX callback function.
+ */
+ ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10);
+ if (ret <= 0) {
+ dev_info(fb_data->info.device,
+ "PxP operation failed due to %s\n",
+ ret < 0 ? "user interrupt" : "timeout");
+ dma_release_channel(&fb_data->pxp_chan->dma_chan);
+ fb_data->pxp_chan = NULL;
+ return ret ? : -ETIMEDOUT;
+ }
+
+ *hist_stat = to_tx_desc(fb_data->txd)->hist_status;
+ dma_release_channel(&fb_data->pxp_chan->dma_chan);
+ fb_data->pxp_chan = NULL;
+
+ dev_dbg(fb_data->dev, "TX completed\n");
+
+ return 0;
+}
+
+static int __init mxc_epdc_fb_init(void)
+{
+ return platform_driver_register(&mxc_epdc_fb_driver);
+}
+late_initcall(mxc_epdc_fb_init);
+
+
+static void __exit mxc_epdc_fb_exit(void)
+{
+ platform_driver_unregister(&mxc_epdc_fb_driver);
+}
+module_exit(mxc_epdc_fb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC EPDC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxcfb_sii9022.c b/drivers/video/mxc/mxcfb_sii9022.c
new file mode 100644
index 000000000000..1de827304f52
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_sii9022.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb_sii9022.c
+ *
+ * @brief MXC Frame buffer driver for SII9022
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/mxcfb.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+static struct i2c_client *sii9022_client;
+static void sii9022_poweron(void);
+static void sii9022_poweroff(void);
+static void (*sii9022_reset) (void);
+
+static __attribute__ ((unused)) void dump_regs(u8 reg, int len)
+{
+ u8 buf[50];
+ int i;
+
+ i2c_smbus_read_i2c_block_data(sii9022_client, reg, len, buf);
+ for (i = 0; i < len; i++)
+ dev_dbg(&sii9022_client->dev, "reg[0x%02X]: 0x%02X\n",
+ i+reg, buf[i]);
+}
+
+static void sii9022_setup(struct fb_info *fbi)
+{
+ u16 data[4];
+ u32 refresh;
+ u8 *tmp;
+ int i;
+
+ dev_dbg(&sii9022_client->dev, "SII9022: setup..\n");
+
+ /* Power up */
+ i2c_smbus_write_byte_data(sii9022_client, 0x1E, 0x00);
+
+ /* set TPI video mode */
+ data[0] = PICOS2KHZ(fbi->var.pixclock) / 10;
+ data[2] = fbi->var.hsync_len + fbi->var.left_margin +
+ fbi->var.xres + fbi->var.right_margin;
+ data[3] = fbi->var.vsync_len + fbi->var.upper_margin +
+ fbi->var.yres + fbi->var.lower_margin;
+ refresh = data[2] * data[3];
+ refresh = (PICOS2KHZ(fbi->var.pixclock) * 1000) / refresh;
+ data[1] = refresh * 100;
+ tmp = (u8 *)data;
+ for (i = 0; i < 8; i++)
+ i2c_smbus_write_byte_data(sii9022_client, i, tmp[i]);
+
+ /* input bus/pixel: full pixel wide (24bit), rising edge */
+ i2c_smbus_write_byte_data(sii9022_client, 0x08, 0x70);
+ /* Set input format to RGB */
+ i2c_smbus_write_byte_data(sii9022_client, 0x09, 0x00);
+ /* set output format to RGB */
+ i2c_smbus_write_byte_data(sii9022_client, 0x0A, 0x00);
+}
+
+static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+ struct fb_event *event = v;
+ struct fb_info *fbi = event->info;
+
+ /* assume sii9022 on DI0 only */
+ if (strcmp(event->info->fix.id, "DISP3 BG"))
+ return 0;
+
+ switch (val) {
+ case FB_EVENT_MODE_CHANGE:
+ sii9022_setup(fbi);
+ break;
+ case FB_EVENT_BLANK:
+ if (*((int *)event->data) == FB_BLANK_UNBLANK)
+ sii9022_poweron();
+ else
+ sii9022_poweroff();
+ break;
+ }
+ return 0;
+}
+
+static struct notifier_block nb = {
+ .notifier_call = lcd_fb_event,
+};
+
+static int __devinit sii9022_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int i, dat;
+ struct mxc_lcd_platform_data *plat = client->dev.platform_data;
+
+ sii9022_client = client;
+
+ if (plat->reset) {
+ sii9022_reset = plat->reset;
+ sii9022_reset();
+ }
+
+ /* Set 9022 in hardware TPI mode on and jump out of D3 state */
+ i2c_smbus_write_byte_data(sii9022_client, 0xc7, 0x00);
+ msleep(10);
+
+ /* read device ID */
+ for (i = 10; i > 0; i--) {
+ dat = i2c_smbus_read_byte_data(sii9022_client, 0x1B);
+ printk(KERN_DEBUG "Sii9022: read id = 0x%02X", dat);
+ if (dat == 0xb0) {
+ dat = i2c_smbus_read_byte_data(sii9022_client, 0x1C);
+ printk(KERN_DEBUG "-0x%02X", dat);
+ dat = i2c_smbus_read_byte_data(sii9022_client, 0x1D);
+ printk(KERN_DEBUG "-0x%02X", dat);
+ dat = i2c_smbus_read_byte_data(sii9022_client, 0x30);
+ printk(KERN_DEBUG "-0x%02X\n", dat);
+ break;
+ }
+ }
+ if (i == 0) {
+ dev_err(&sii9022_client->dev,
+ "SII9022: cound not find device\n");
+ return -ENODEV;
+ }
+
+ fb_register_client(&nb);
+
+ for (i = 0; i < num_registered_fb; i++) {
+ /* assume sii9022 on DI0 only */
+ if ((strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0)
+ && (i == 0)) {
+ struct fb_info *fbi = registered_fb[i];
+ acquire_console_sem();
+ fb_blank(fbi, FB_BLANK_POWERDOWN);
+ release_console_sem();
+
+ sii9022_setup(fbi);
+
+ acquire_console_sem();
+ fb_blank(fbi, FB_BLANK_UNBLANK);
+ release_console_sem();
+
+ fb_show_logo(fbi, 0);
+ }
+ }
+
+ return 0;
+}
+
+static int __devexit sii9022_remove(struct i2c_client *client)
+{
+ fb_unregister_client(&nb);
+ sii9022_poweroff();
+ return 0;
+}
+
+static int sii9022_suspend(struct i2c_client *client, pm_message_t message)
+{
+ /*TODO*/
+ return 0;
+}
+
+static int sii9022_resume(struct i2c_client *client)
+{
+ /*TODO*/
+ return 0;
+}
+
+static void sii9022_poweron(void)
+{
+ /* Turn on DVI or HDMI */
+ i2c_smbus_write_byte_data(sii9022_client, 0x1A, 0x01);
+ return;
+}
+
+static void sii9022_poweroff(void)
+{
+ /* disable tmds before changing resolution */
+ i2c_smbus_write_byte_data(sii9022_client, 0x1A, 0x11);
+
+ return;
+}
+
+static const struct i2c_device_id sii9022_id[] = {
+ { "sii9022", 0 },
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, sii9022_id);
+
+static struct i2c_driver sii9022_i2c_driver = {
+ .driver = {
+ .name = "sii9022",
+ },
+ .probe = sii9022_probe,
+ .remove = sii9022_remove,
+ .suspend = sii9022_suspend,
+ .resume = sii9022_resume,
+ .id_table = sii9022_id,
+};
+
+static int __init sii9022_init(void)
+{
+ return i2c_add_driver(&sii9022_i2c_driver);
+}
+
+static void __exit sii9022_exit(void)
+{
+ i2c_del_driver(&sii9022_i2c_driver);
+}
+
+module_init(sii9022_init);
+module_exit(sii9022_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("SI9022 DVI/HDMI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxs/regs-tvenc.h b/drivers/video/mxs/regs-tvenc.h
new file mode 100644
index 000000000000..bd2493e2dee5
--- /dev/null
+++ b/drivers/video/mxs/regs-tvenc.h
@@ -0,0 +1,583 @@
+/*
+ * Freescale TVENC Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.00
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___TVENC_H
+#define __ARCH_ARM___TVENC_H
+
+
+#define HW_TVENC_CTRL (0x00000000)
+#define HW_TVENC_CTRL_SET (0x00000004)
+#define HW_TVENC_CTRL_CLR (0x00000008)
+#define HW_TVENC_CTRL_TOG (0x0000000c)
+
+#define BM_TVENC_CTRL_SFTRST 0x80000000
+#define BM_TVENC_CTRL_CLKGATE 0x40000000
+#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT 0x20000000
+#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 0x10000000
+#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT 0x08000000
+#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT 0x04000000
+#define BP_TVENC_CTRL_RSRVD1 6
+#define BM_TVENC_CTRL_RSRVD1 0x03FFFFC0
+#define BF_TVENC_CTRL_RSRVD1(v) \
+ (((v) << 6) & BM_TVENC_CTRL_RSRVD1)
+#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE 0x00000020
+#define BM_TVENC_CTRL_DAC_FIFO_NO_READ 0x00000010
+#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST 0x00000008
+#define BP_TVENC_CTRL_RSRVD2 1
+#define BM_TVENC_CTRL_RSRVD2 0x00000006
+#define BF_TVENC_CTRL_RSRVD2(v) \
+ (((v) << 1) & BM_TVENC_CTRL_RSRVD2)
+#define BM_TVENC_CTRL_DAC_MUX_MODE 0x00000001
+
+#define HW_TVENC_CONFIG (0x00000010)
+#define HW_TVENC_CONFIG_SET (0x00000014)
+#define HW_TVENC_CONFIG_CLR (0x00000018)
+#define HW_TVENC_CONFIG_TOG (0x0000001c)
+
+#define BP_TVENC_CONFIG_RSRVD5 28
+#define BM_TVENC_CONFIG_RSRVD5 0xF0000000
+#define BF_TVENC_CONFIG_RSRVD5(v) \
+ (((v) << 28) & BM_TVENC_CONFIG_RSRVD5)
+#define BM_TVENC_CONFIG_DEFAULT_PICFORM 0x08000000
+#define BP_TVENC_CONFIG_YDEL_ADJ 24
+#define BM_TVENC_CONFIG_YDEL_ADJ 0x07000000
+#define BF_TVENC_CONFIG_YDEL_ADJ(v) \
+ (((v) << 24) & BM_TVENC_CONFIG_YDEL_ADJ)
+#define BM_TVENC_CONFIG_RSRVD4 0x00800000
+#define BM_TVENC_CONFIG_RSRVD3 0x00400000
+#define BM_TVENC_CONFIG_ADD_YPBPR_PED 0x00200000
+#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
+#define BM_TVENC_CONFIG_NO_PED 0x00080000
+#define BM_TVENC_CONFIG_COLOR_BAR_EN 0x00040000
+#define BP_TVENC_CONFIG_YGAIN_SEL 16
+#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
+#define BF_TVENC_CONFIG_YGAIN_SEL(v) \
+ (((v) << 16) & BM_TVENC_CONFIG_YGAIN_SEL)
+#define BP_TVENC_CONFIG_CGAIN 14
+#define BM_TVENC_CONFIG_CGAIN 0x0000C000
+#define BF_TVENC_CONFIG_CGAIN(v) \
+ (((v) << 14) & BM_TVENC_CONFIG_CGAIN)
+#define BP_TVENC_CONFIG_CLK_PHS 12
+#define BM_TVENC_CONFIG_CLK_PHS 0x00003000
+#define BF_TVENC_CONFIG_CLK_PHS(v) \
+ (((v) << 12) & BM_TVENC_CONFIG_CLK_PHS)
+#define BM_TVENC_CONFIG_RSRVD2 0x00000800
+#define BM_TVENC_CONFIG_FSYNC_ENBL 0x00000400
+#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
+#define BM_TVENC_CONFIG_HSYNC_PHS 0x00000100
+#define BM_TVENC_CONFIG_VSYNC_PHS 0x00000080
+#define BP_TVENC_CONFIG_SYNC_MODE 4
+#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
+#define BF_TVENC_CONFIG_SYNC_MODE(v) \
+ (((v) << 4) & BM_TVENC_CONFIG_SYNC_MODE)
+#define BM_TVENC_CONFIG_RSRVD1 0x00000008
+#define BP_TVENC_CONFIG_ENCD_MODE 0
+#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
+#define BF_TVENC_CONFIG_ENCD_MODE(v) \
+ (((v) << 0) & BM_TVENC_CONFIG_ENCD_MODE)
+
+#define HW_TVENC_FILTCTRL (0x00000020)
+#define HW_TVENC_FILTCTRL_SET (0x00000024)
+#define HW_TVENC_FILTCTRL_CLR (0x00000028)
+#define HW_TVENC_FILTCTRL_TOG (0x0000002c)
+
+#define BP_TVENC_FILTCTRL_RSRVD1 20
+#define BM_TVENC_FILTCTRL_RSRVD1 0xFFF00000
+#define BF_TVENC_FILTCTRL_RSRVD1(v) \
+ (((v) << 20) & BM_TVENC_FILTCTRL_RSRVD1)
+#define BM_TVENC_FILTCTRL_YSHARP_BW 0x00080000
+#define BM_TVENC_FILTCTRL_YD_OFFSETSEL 0x00040000
+#define BM_TVENC_FILTCTRL_SEL_YLPF 0x00020000
+#define BM_TVENC_FILTCTRL_SEL_CLPF 0x00010000
+#define BM_TVENC_FILTCTRL_SEL_YSHARP 0x00008000
+#define BM_TVENC_FILTCTRL_YLPF_COEFSEL 0x00004000
+#define BM_TVENC_FILTCTRL_COEFSEL_CLPF 0x00002000
+#define BM_TVENC_FILTCTRL_YS_GAINSGN 0x00001000
+#define BP_TVENC_FILTCTRL_YS_GAINSEL 10
+#define BM_TVENC_FILTCTRL_YS_GAINSEL 0x00000C00
+#define BF_TVENC_FILTCTRL_YS_GAINSEL(v) \
+ (((v) << 10) & BM_TVENC_FILTCTRL_YS_GAINSEL)
+#define BM_TVENC_FILTCTRL_RSRVD2 0x00000200
+#define BM_TVENC_FILTCTRL_RSRVD3 0x00000100
+#define BP_TVENC_FILTCTRL_RSRVD4 0
+#define BM_TVENC_FILTCTRL_RSRVD4 0x000000FF
+#define BF_TVENC_FILTCTRL_RSRVD4(v) \
+ (((v) << 0) & BM_TVENC_FILTCTRL_RSRVD4)
+
+#define HW_TVENC_SYNCOFFSET (0x00000030)
+#define HW_TVENC_SYNCOFFSET_SET (0x00000034)
+#define HW_TVENC_SYNCOFFSET_CLR (0x00000038)
+#define HW_TVENC_SYNCOFFSET_TOG (0x0000003c)
+
+#define BM_TVENC_SYNCOFFSET_RSRVD1 0x80000000
+#define BP_TVENC_SYNCOFFSET_HSO 20
+#define BM_TVENC_SYNCOFFSET_HSO 0x7FF00000
+#define BF_TVENC_SYNCOFFSET_HSO(v) \
+ (((v) << 20) & BM_TVENC_SYNCOFFSET_HSO)
+#define BP_TVENC_SYNCOFFSET_VSO 10
+#define BM_TVENC_SYNCOFFSET_VSO 0x000FFC00
+#define BF_TVENC_SYNCOFFSET_VSO(v) \
+ (((v) << 10) & BM_TVENC_SYNCOFFSET_VSO)
+#define BP_TVENC_SYNCOFFSET_HLC 0
+#define BM_TVENC_SYNCOFFSET_HLC 0x000003FF
+#define BF_TVENC_SYNCOFFSET_HLC(v) \
+ (((v) << 0) & BM_TVENC_SYNCOFFSET_HLC)
+
+#define HW_TVENC_HTIMINGSYNC0 (0x00000040)
+#define HW_TVENC_HTIMINGSYNC0_SET (0x00000044)
+#define HW_TVENC_HTIMINGSYNC0_CLR (0x00000048)
+#define HW_TVENC_HTIMINGSYNC0_TOG (0x0000004c)
+
+#define BP_TVENC_HTIMINGSYNC0_RSRVD2 26
+#define BM_TVENC_HTIMINGSYNC0_RSRVD2 0xFC000000
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) \
+ (((v) << 26) & BM_TVENC_HTIMINGSYNC0_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_END 16
+#define BM_TVENC_HTIMINGSYNC0_SYNC_END 0x03FF0000
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v) \
+ (((v) << 16) & BM_TVENC_HTIMINGSYNC0_SYNC_END)
+#define BP_TVENC_HTIMINGSYNC0_RSRVD1 10
+#define BM_TVENC_HTIMINGSYNC0_RSRVD1 0x0000FC00
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_HTIMINGSYNC0_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT 0
+#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT 0x000003FF
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v) \
+ (((v) << 0) & BM_TVENC_HTIMINGSYNC0_SYNC_STRT)
+
+#define HW_TVENC_HTIMINGSYNC1 (0x00000050)
+#define HW_TVENC_HTIMINGSYNC1_SET (0x00000054)
+#define HW_TVENC_HTIMINGSYNC1_CLR (0x00000058)
+#define HW_TVENC_HTIMINGSYNC1_TOG (0x0000005c)
+
+#define BP_TVENC_HTIMINGSYNC1_RSRVD2 26
+#define BM_TVENC_HTIMINGSYNC1_RSRVD2 0xFC000000
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) \
+ (((v) << 26) & BM_TVENC_HTIMINGSYNC1_RSRVD2)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND 16
+#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND 0x03FF0000
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) \
+ (((v) << 16) & BM_TVENC_HTIMINGSYNC1_SYNC_EQEND)
+#define BP_TVENC_HTIMINGSYNC1_RSRVD1 10
+#define BM_TVENC_HTIMINGSYNC1_RSRVD1 0x0000FC00
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_HTIMINGSYNC1_RSRVD1)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND 0
+#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND 0x000003FF
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) \
+ (((v) << 0) & BM_TVENC_HTIMINGSYNC1_SYNC_SREND)
+
+#define HW_TVENC_HTIMINGACTIVE (0x00000060)
+#define HW_TVENC_HTIMINGACTIVE_SET (0x00000064)
+#define HW_TVENC_HTIMINGACTIVE_CLR (0x00000068)
+#define HW_TVENC_HTIMINGACTIVE_TOG (0x0000006c)
+
+#define BP_TVENC_HTIMINGACTIVE_RSRVD2 26
+#define BM_TVENC_HTIMINGACTIVE_RSRVD2 0xFC000000
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) \
+ (((v) << 26) & BM_TVENC_HTIMINGACTIVE_RSRVD2)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_END 16
+#define BM_TVENC_HTIMINGACTIVE_ACTV_END 0x03FF0000
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v) \
+ (((v) << 16) & BM_TVENC_HTIMINGACTIVE_ACTV_END)
+#define BP_TVENC_HTIMINGACTIVE_RSRVD1 10
+#define BM_TVENC_HTIMINGACTIVE_RSRVD1 0x0000FC00
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_HTIMINGACTIVE_RSRVD1)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT 0
+#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT 0x000003FF
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) \
+ (((v) << 0) & BM_TVENC_HTIMINGACTIVE_ACTV_STRT)
+
+#define HW_TVENC_HTIMINGBURST0 (0x00000070)
+#define HW_TVENC_HTIMINGBURST0_SET (0x00000074)
+#define HW_TVENC_HTIMINGBURST0_CLR (0x00000078)
+#define HW_TVENC_HTIMINGBURST0_TOG (0x0000007c)
+
+#define BP_TVENC_HTIMINGBURST0_RSRVD2 26
+#define BM_TVENC_HTIMINGBURST0_RSRVD2 0xFC000000
+#define BF_TVENC_HTIMINGBURST0_RSRVD2(v) \
+ (((v) << 26) & BM_TVENC_HTIMINGBURST0_RSRVD2)
+#define BP_TVENC_HTIMINGBURST0_WBRST_STRT 16
+#define BM_TVENC_HTIMINGBURST0_WBRST_STRT 0x03FF0000
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v) \
+ (((v) << 16) & BM_TVENC_HTIMINGBURST0_WBRST_STRT)
+#define BP_TVENC_HTIMINGBURST0_RSRVD1 10
+#define BM_TVENC_HTIMINGBURST0_RSRVD1 0x0000FC00
+#define BF_TVENC_HTIMINGBURST0_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_HTIMINGBURST0_RSRVD1)
+#define BP_TVENC_HTIMINGBURST0_NBRST_STRT 0
+#define BM_TVENC_HTIMINGBURST0_NBRST_STRT 0x000003FF
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v) \
+ (((v) << 0) & BM_TVENC_HTIMINGBURST0_NBRST_STRT)
+
+#define HW_TVENC_HTIMINGBURST1 (0x00000080)
+#define HW_TVENC_HTIMINGBURST1_SET (0x00000084)
+#define HW_TVENC_HTIMINGBURST1_CLR (0x00000088)
+#define HW_TVENC_HTIMINGBURST1_TOG (0x0000008c)
+
+#define BP_TVENC_HTIMINGBURST1_RSRVD1 10
+#define BM_TVENC_HTIMINGBURST1_RSRVD1 0xFFFFFC00
+#define BF_TVENC_HTIMINGBURST1_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_HTIMINGBURST1_RSRVD1)
+#define BP_TVENC_HTIMINGBURST1_BRST_END 0
+#define BM_TVENC_HTIMINGBURST1_BRST_END 0x000003FF
+#define BF_TVENC_HTIMINGBURST1_BRST_END(v) \
+ (((v) << 0) & BM_TVENC_HTIMINGBURST1_BRST_END)
+
+#define HW_TVENC_VTIMING0 (0x00000090)
+#define HW_TVENC_VTIMING0_SET (0x00000094)
+#define HW_TVENC_VTIMING0_CLR (0x00000098)
+#define HW_TVENC_VTIMING0_TOG (0x0000009c)
+
+#define BP_TVENC_VTIMING0_RSRVD3 26
+#define BM_TVENC_VTIMING0_RSRVD3 0xFC000000
+#define BF_TVENC_VTIMING0_RSRVD3(v) \
+ (((v) << 26) & BM_TVENC_VTIMING0_RSRVD3)
+#define BP_TVENC_VTIMING0_VSTRT_PREEQ 16
+#define BM_TVENC_VTIMING0_VSTRT_PREEQ 0x03FF0000
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v) \
+ (((v) << 16) & BM_TVENC_VTIMING0_VSTRT_PREEQ)
+#define BP_TVENC_VTIMING0_RSRVD2 14
+#define BM_TVENC_VTIMING0_RSRVD2 0x0000C000
+#define BF_TVENC_VTIMING0_RSRVD2(v) \
+ (((v) << 14) & BM_TVENC_VTIMING0_RSRVD2)
+#define BP_TVENC_VTIMING0_VSTRT_ACTV 8
+#define BM_TVENC_VTIMING0_VSTRT_ACTV 0x00003F00
+#define BF_TVENC_VTIMING0_VSTRT_ACTV(v) \
+ (((v) << 8) & BM_TVENC_VTIMING0_VSTRT_ACTV)
+#define BP_TVENC_VTIMING0_RSRVD1 6
+#define BM_TVENC_VTIMING0_RSRVD1 0x000000C0
+#define BF_TVENC_VTIMING0_RSRVD1(v) \
+ (((v) << 6) & BM_TVENC_VTIMING0_RSRVD1)
+#define BP_TVENC_VTIMING0_VSTRT_SUBPH 0
+#define BM_TVENC_VTIMING0_VSTRT_SUBPH 0x0000003F
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v) \
+ (((v) << 0) & BM_TVENC_VTIMING0_VSTRT_SUBPH)
+
+#define HW_TVENC_VTIMING1 (0x000000a0)
+#define HW_TVENC_VTIMING1_SET (0x000000a4)
+#define HW_TVENC_VTIMING1_CLR (0x000000a8)
+#define HW_TVENC_VTIMING1_TOG (0x000000ac)
+
+#define BP_TVENC_VTIMING1_RSRVD3 30
+#define BM_TVENC_VTIMING1_RSRVD3 0xC0000000
+#define BF_TVENC_VTIMING1_RSRVD3(v) \
+ (((v) << 30) & BM_TVENC_VTIMING1_RSRVD3)
+#define BP_TVENC_VTIMING1_VSTRT_POSTEQ 24
+#define BM_TVENC_VTIMING1_VSTRT_POSTEQ 0x3F000000
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v) \
+ (((v) << 24) & BM_TVENC_VTIMING1_VSTRT_POSTEQ)
+#define BP_TVENC_VTIMING1_RSRVD2 22
+#define BM_TVENC_VTIMING1_RSRVD2 0x00C00000
+#define BF_TVENC_VTIMING1_RSRVD2(v) \
+ (((v) << 22) & BM_TVENC_VTIMING1_RSRVD2)
+#define BP_TVENC_VTIMING1_VSTRT_SERRA 16
+#define BM_TVENC_VTIMING1_VSTRT_SERRA 0x003F0000
+#define BF_TVENC_VTIMING1_VSTRT_SERRA(v) \
+ (((v) << 16) & BM_TVENC_VTIMING1_VSTRT_SERRA)
+#define BP_TVENC_VTIMING1_RSRVD1 10
+#define BM_TVENC_VTIMING1_RSRVD1 0x0000FC00
+#define BF_TVENC_VTIMING1_RSRVD1(v) \
+ (((v) << 10) & BM_TVENC_VTIMING1_RSRVD1)
+#define BP_TVENC_VTIMING1_LAST_FLD_LN 0
+#define BM_TVENC_VTIMING1_LAST_FLD_LN 0x000003FF
+#define BF_TVENC_VTIMING1_LAST_FLD_LN(v) \
+ (((v) << 0) & BM_TVENC_VTIMING1_LAST_FLD_LN)
+
+#define HW_TVENC_MISC (0x000000b0)
+#define HW_TVENC_MISC_SET (0x000000b4)
+#define HW_TVENC_MISC_CLR (0x000000b8)
+#define HW_TVENC_MISC_TOG (0x000000bc)
+
+#define BP_TVENC_MISC_RSRVD3 25
+#define BM_TVENC_MISC_RSRVD3 0xFE000000
+#define BF_TVENC_MISC_RSRVD3(v) \
+ (((v) << 25) & BM_TVENC_MISC_RSRVD3)
+#define BP_TVENC_MISC_LPF_RST_OFF 16
+#define BM_TVENC_MISC_LPF_RST_OFF 0x01FF0000
+#define BF_TVENC_MISC_LPF_RST_OFF(v) \
+ (((v) << 16) & BM_TVENC_MISC_LPF_RST_OFF)
+#define BP_TVENC_MISC_RSRVD2 12
+#define BM_TVENC_MISC_RSRVD2 0x0000F000
+#define BF_TVENC_MISC_RSRVD2(v) \
+ (((v) << 12) & BM_TVENC_MISC_RSRVD2)
+#define BM_TVENC_MISC_NTSC_LN_CNT 0x00000800
+#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT 0x00000400
+#define BP_TVENC_MISC_FSC_PHASE_RST 8
+#define BM_TVENC_MISC_FSC_PHASE_RST 0x00000300
+#define BF_TVENC_MISC_FSC_PHASE_RST(v) \
+ (((v) << 8) & BM_TVENC_MISC_FSC_PHASE_RST)
+#define BP_TVENC_MISC_BRUCHB 6
+#define BM_TVENC_MISC_BRUCHB 0x000000C0
+#define BF_TVENC_MISC_BRUCHB(v) \
+ (((v) << 6) & BM_TVENC_MISC_BRUCHB)
+#define BP_TVENC_MISC_AGC_LVL_CTRL 4
+#define BM_TVENC_MISC_AGC_LVL_CTRL 0x00000030
+#define BF_TVENC_MISC_AGC_LVL_CTRL(v) \
+ (((v) << 4) & BM_TVENC_MISC_AGC_LVL_CTRL)
+#define BM_TVENC_MISC_RSRVD1 0x00000008
+#define BM_TVENC_MISC_CS_INVERT_CTRL 0x00000004
+#define BP_TVENC_MISC_Y_BLANK_CTRL 0
+#define BM_TVENC_MISC_Y_BLANK_CTRL 0x00000003
+#define BF_TVENC_MISC_Y_BLANK_CTRL(v) \
+ (((v) << 0) & BM_TVENC_MISC_Y_BLANK_CTRL)
+
+#define HW_TVENC_COLORSUB0 (0x000000c0)
+#define HW_TVENC_COLORSUB0_SET (0x000000c4)
+#define HW_TVENC_COLORSUB0_CLR (0x000000c8)
+#define HW_TVENC_COLORSUB0_TOG (0x000000cc)
+
+#define BP_TVENC_COLORSUB0_PHASE_INC 0
+#define BM_TVENC_COLORSUB0_PHASE_INC 0xFFFFFFFF
+#define BF_TVENC_COLORSUB0_PHASE_INC(v) (v)
+
+#define HW_TVENC_COLORSUB1 (0x000000d0)
+#define HW_TVENC_COLORSUB1_SET (0x000000d4)
+#define HW_TVENC_COLORSUB1_CLR (0x000000d8)
+#define HW_TVENC_COLORSUB1_TOG (0x000000dc)
+
+#define BP_TVENC_COLORSUB1_PHASE_OFFSET 0
+#define BM_TVENC_COLORSUB1_PHASE_OFFSET 0xFFFFFFFF
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v) (v)
+
+#define HW_TVENC_COPYPROTECT (0x000000e0)
+#define HW_TVENC_COPYPROTECT_SET (0x000000e4)
+#define HW_TVENC_COPYPROTECT_CLR (0x000000e8)
+#define HW_TVENC_COPYPROTECT_TOG (0x000000ec)
+
+#define BP_TVENC_COPYPROTECT_RSRVD1 16
+#define BM_TVENC_COPYPROTECT_RSRVD1 0xFFFF0000
+#define BF_TVENC_COPYPROTECT_RSRVD1(v) \
+ (((v) << 16) & BM_TVENC_COPYPROTECT_RSRVD1)
+#define BM_TVENC_COPYPROTECT_WSS_ENBL 0x00008000
+#define BM_TVENC_COPYPROTECT_CGMS_ENBL 0x00004000
+#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA 0
+#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA 0x00003FFF
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v) \
+ (((v) << 0) & BM_TVENC_COPYPROTECT_WSS_CGMS_DATA)
+
+#define HW_TVENC_CLOSEDCAPTION (0x000000f0)
+#define HW_TVENC_CLOSEDCAPTION_SET (0x000000f4)
+#define HW_TVENC_CLOSEDCAPTION_CLR (0x000000f8)
+#define HW_TVENC_CLOSEDCAPTION_TOG (0x000000fc)
+
+#define BP_TVENC_CLOSEDCAPTION_RSRVD1 20
+#define BM_TVENC_CLOSEDCAPTION_RSRVD1 0xFFF00000
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) \
+ (((v) << 20) & BM_TVENC_CLOSEDCAPTION_RSRVD1)
+#define BP_TVENC_CLOSEDCAPTION_CC_ENBL 18
+#define BM_TVENC_CLOSEDCAPTION_CC_ENBL 0x000C0000
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v) \
+ (((v) << 18) & BM_TVENC_CLOSEDCAPTION_CC_ENBL)
+#define BP_TVENC_CLOSEDCAPTION_CC_FILL 16
+#define BM_TVENC_CLOSEDCAPTION_CC_FILL 0x00030000
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v) \
+ (((v) << 16) & BM_TVENC_CLOSEDCAPTION_CC_FILL)
+#define BP_TVENC_CLOSEDCAPTION_CC_DATA 0
+#define BM_TVENC_CLOSEDCAPTION_CC_DATA 0x0000FFFF
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v) \
+ (((v) << 0) & BM_TVENC_CLOSEDCAPTION_CC_DATA)
+
+#define HW_TVENC_COLORBURST (0x00000140)
+#define HW_TVENC_COLORBURST_SET (0x00000144)
+#define HW_TVENC_COLORBURST_CLR (0x00000148)
+#define HW_TVENC_COLORBURST_TOG (0x0000014c)
+
+#define BP_TVENC_COLORBURST_NBA 24
+#define BM_TVENC_COLORBURST_NBA 0xFF000000
+#define BF_TVENC_COLORBURST_NBA(v) \
+ (((v) << 24) & BM_TVENC_COLORBURST_NBA)
+#define BP_TVENC_COLORBURST_PBA 16
+#define BM_TVENC_COLORBURST_PBA 0x00FF0000
+#define BF_TVENC_COLORBURST_PBA(v) \
+ (((v) << 16) & BM_TVENC_COLORBURST_PBA)
+#define BP_TVENC_COLORBURST_RSRVD1 12
+#define BM_TVENC_COLORBURST_RSRVD1 0x0000F000
+#define BF_TVENC_COLORBURST_RSRVD1(v) \
+ (((v) << 12) & BM_TVENC_COLORBURST_RSRVD1)
+#define BP_TVENC_COLORBURST_RSRVD2 0
+#define BM_TVENC_COLORBURST_RSRVD2 0x00000FFF
+#define BF_TVENC_COLORBURST_RSRVD2(v) \
+ (((v) << 0) & BM_TVENC_COLORBURST_RSRVD2)
+
+#define HW_TVENC_MACROVISION0 (0x00000150)
+#define HW_TVENC_MACROVISION0_SET (0x00000154)
+#define HW_TVENC_MACROVISION0_CLR (0x00000158)
+#define HW_TVENC_MACROVISION0_TOG (0x0000015c)
+
+#define BP_TVENC_MACROVISION0_DATA 0
+#define BM_TVENC_MACROVISION0_DATA 0xFFFFFFFF
+#define BF_TVENC_MACROVISION0_DATA(v) (v)
+
+#define HW_TVENC_MACROVISION1 (0x00000160)
+#define HW_TVENC_MACROVISION1_SET (0x00000164)
+#define HW_TVENC_MACROVISION1_CLR (0x00000168)
+#define HW_TVENC_MACROVISION1_TOG (0x0000016c)
+
+#define BP_TVENC_MACROVISION1_DATA 0
+#define BM_TVENC_MACROVISION1_DATA 0xFFFFFFFF
+#define BF_TVENC_MACROVISION1_DATA(v) (v)
+
+#define HW_TVENC_MACROVISION2 (0x00000170)
+#define HW_TVENC_MACROVISION2_SET (0x00000174)
+#define HW_TVENC_MACROVISION2_CLR (0x00000178)
+#define HW_TVENC_MACROVISION2_TOG (0x0000017c)
+
+#define BP_TVENC_MACROVISION2_DATA 0
+#define BM_TVENC_MACROVISION2_DATA 0xFFFFFFFF
+#define BF_TVENC_MACROVISION2_DATA(v) (v)
+
+#define HW_TVENC_MACROVISION3 (0x00000180)
+#define HW_TVENC_MACROVISION3_SET (0x00000184)
+#define HW_TVENC_MACROVISION3_CLR (0x00000188)
+#define HW_TVENC_MACROVISION3_TOG (0x0000018c)
+
+#define BP_TVENC_MACROVISION3_DATA 0
+#define BM_TVENC_MACROVISION3_DATA 0xFFFFFFFF
+#define BF_TVENC_MACROVISION3_DATA(v) (v)
+
+#define HW_TVENC_MACROVISION4 (0x00000190)
+#define HW_TVENC_MACROVISION4_SET (0x00000194)
+#define HW_TVENC_MACROVISION4_CLR (0x00000198)
+#define HW_TVENC_MACROVISION4_TOG (0x0000019c)
+
+#define BP_TVENC_MACROVISION4_RSRVD2 24
+#define BM_TVENC_MACROVISION4_RSRVD2 0xFF000000
+#define BF_TVENC_MACROVISION4_RSRVD2(v) \
+ (((v) << 24) & BM_TVENC_MACROVISION4_RSRVD2)
+#define BP_TVENC_MACROVISION4_MACV_TST 16
+#define BM_TVENC_MACROVISION4_MACV_TST 0x00FF0000
+#define BF_TVENC_MACROVISION4_MACV_TST(v) \
+ (((v) << 16) & BM_TVENC_MACROVISION4_MACV_TST)
+#define BP_TVENC_MACROVISION4_RSRVD1 11
+#define BM_TVENC_MACROVISION4_RSRVD1 0x0000F800
+#define BF_TVENC_MACROVISION4_RSRVD1(v) \
+ (((v) << 11) & BM_TVENC_MACROVISION4_RSRVD1)
+#define BP_TVENC_MACROVISION4_DATA 0
+#define BM_TVENC_MACROVISION4_DATA 0x000007FF
+#define BF_TVENC_MACROVISION4_DATA(v) \
+ (((v) << 0) & BM_TVENC_MACROVISION4_DATA)
+
+#define HW_TVENC_DACCTRL (0x000001a0)
+#define HW_TVENC_DACCTRL_SET (0x000001a4)
+#define HW_TVENC_DACCTRL_CLR (0x000001a8)
+#define HW_TVENC_DACCTRL_TOG (0x000001ac)
+
+#define BM_TVENC_DACCTRL_TEST3 0x80000000
+#define BM_TVENC_DACCTRL_RSRVD1 0x40000000
+#define BM_TVENC_DACCTRL_RSRVD2 0x20000000
+#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN 0x10000000
+#define BM_TVENC_DACCTRL_TEST2 0x08000000
+#define BM_TVENC_DACCTRL_RSRVD3 0x04000000
+#define BM_TVENC_DACCTRL_RSRVD4 0x02000000
+#define BM_TVENC_DACCTRL_JACK1_DET_EN 0x01000000
+#define BM_TVENC_DACCTRL_TEST1 0x00800000
+#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT 0x00400000
+#define BP_TVENC_DACCTRL_JACK_DIS_ADJ 20
+#define BM_TVENC_DACCTRL_JACK_DIS_ADJ 0x00300000
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v) \
+ (((v) << 20) & BM_TVENC_DACCTRL_JACK_DIS_ADJ)
+#define BM_TVENC_DACCTRL_GAINDN 0x00080000
+#define BM_TVENC_DACCTRL_GAINUP 0x00040000
+#define BM_TVENC_DACCTRL_INVERT_CLK 0x00020000
+#define BM_TVENC_DACCTRL_SELECT_CLK 0x00010000
+#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE 0x00008000
+#define BM_TVENC_DACCTRL_RSRVD5 0x00004000
+#define BM_TVENC_DACCTRL_RSRVD6 0x00002000
+#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
+#define BM_TVENC_DACCTRL_WELL_TOVDD 0x00000800
+#define BM_TVENC_DACCTRL_RSRVD7 0x00000400
+#define BM_TVENC_DACCTRL_RSRVD8 0x00000200
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
+#define BM_TVENC_DACCTRL_LOWER_SIGNAL 0x00000080
+#define BP_TVENC_DACCTRL_RVAL 4
+#define BM_TVENC_DACCTRL_RVAL 0x00000070
+#define BF_TVENC_DACCTRL_RVAL(v) \
+ (((v) << 4) & BM_TVENC_DACCTRL_RVAL)
+#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM 0x00000008
+#define BM_TVENC_DACCTRL_HALF_CURRENT 0x00000004
+#define BP_TVENC_DACCTRL_CASC_ADJ 0
+#define BM_TVENC_DACCTRL_CASC_ADJ 0x00000003
+#define BF_TVENC_DACCTRL_CASC_ADJ(v) \
+ (((v) << 0) & BM_TVENC_DACCTRL_CASC_ADJ)
+
+#define HW_TVENC_DACSTATUS (0x000001b0)
+#define HW_TVENC_DACSTATUS_SET (0x000001b4)
+#define HW_TVENC_DACSTATUS_CLR (0x000001b8)
+#define HW_TVENC_DACSTATUS_TOG (0x000001bc)
+
+#define BP_TVENC_DACSTATUS_RSRVD1 13
+#define BM_TVENC_DACSTATUS_RSRVD1 0xFFFFE000
+#define BF_TVENC_DACSTATUS_RSRVD1(v) \
+ (((v) << 13) & BM_TVENC_DACSTATUS_RSRVD1)
+#define BM_TVENC_DACSTATUS_RSRVD2 0x00001000
+#define BM_TVENC_DACSTATUS_RSRVD3 0x00000800
+#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS 0x00000400
+#define BM_TVENC_DACSTATUS_RSRVD4 0x00000200
+#define BM_TVENC_DACSTATUS_RSRVD5 0x00000100
+#define BM_TVENC_DACSTATUS_JACK1_GROUNDED 0x00000080
+#define BM_TVENC_DACSTATUS_RSRVD6 0x00000040
+#define BM_TVENC_DACSTATUS_RSRVD7 0x00000020
+#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 0x00000010
+#define BM_TVENC_DACSTATUS_RSRVD8 0x00000008
+#define BM_TVENC_DACSTATUS_RSRVD9 0x00000004
+#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ 0x00000002
+#define BM_TVENC_DACSTATUS_ENIRQ_JACK 0x00000001
+
+#define HW_TVENC_VDACTEST (0x000001c0)
+#define HW_TVENC_VDACTEST_SET (0x000001c4)
+#define HW_TVENC_VDACTEST_CLR (0x000001c8)
+#define HW_TVENC_VDACTEST_TOG (0x000001cc)
+
+#define BP_TVENC_VDACTEST_RSRVD1 14
+#define BM_TVENC_VDACTEST_RSRVD1 0xFFFFC000
+#define BF_TVENC_VDACTEST_RSRVD1(v) \
+ (((v) << 14) & BM_TVENC_VDACTEST_RSRVD1)
+#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 0x00002000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT 0x00001000
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 0x00000800
+#define BM_TVENC_VDACTEST_TEST_FIFO_FULL 0x00000400
+#define BP_TVENC_VDACTEST_DATA 0
+#define BM_TVENC_VDACTEST_DATA 0x000003FF
+#define BF_TVENC_VDACTEST_DATA(v) \
+ (((v) << 0) & BM_TVENC_VDACTEST_DATA)
+
+#define HW_TVENC_VERSION (0x000001d0)
+
+#define BP_TVENC_VERSION_MAJOR 24
+#define BM_TVENC_VERSION_MAJOR 0xFF000000
+#define BF_TVENC_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_TVENC_VERSION_MAJOR)
+#define BP_TVENC_VERSION_MINOR 16
+#define BM_TVENC_VERSION_MINOR 0x00FF0000
+#define BF_TVENC_VERSION_MINOR(v) \
+ (((v) << 16) & BM_TVENC_VERSION_MINOR)
+#define BP_TVENC_VERSION_STEP 0
+#define BM_TVENC_VERSION_STEP 0x0000FFFF
+#define BF_TVENC_VERSION_STEP(v) \
+ (((v) << 0) & BM_TVENC_VERSION_STEP)
+#endif /* __ARCH_ARM___TVENC_H */
diff --git a/drivers/video/mxs/tvenc.c b/drivers/video/mxs/tvenc.c
new file mode 100644
index 000000000000..7aaa1fd013b0
--- /dev/null
+++ b/drivers/video/mxs/tvenc.c
@@ -0,0 +1,279 @@
+/*
+ * Freescale STMP378X dvi panel initialization
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <mach/regs-lcdif.h>
+#include <mach/regs-lradc.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-apbh.h>
+#include <mach/gpio.h>
+#include <mach/lcdif.h>
+#include "regs-tvenc.h"
+
+enum {
+ TVENC_MODE_OFF = 0,
+ TVENC_MODE_NTSC,
+ TVENC_MODE_PAL,
+};
+
+#define REGS_TVENC_BASE (IO_ADDRESS(TVENC_PHYS_ADDR))
+
+/* NTSC 720x480 mode */
+#define NTSC_X_RES 720
+#define NTSC_Y_RES 480
+#define NTSC_H_BLANKING 262
+#define NTSC_V_LINES 525
+
+/* PAL 720x576 mode */
+#define PAL_X_RES 720
+#define PAL_Y_RES 576
+#define PAL_H_BLANKING 274
+#define PAL_V_LINES 625
+
+/* frame size */
+#define DVI_H_BLANKING(m) (m == TVENC_MODE_NTSC ? \
+ NTSC_H_BLANKING : PAL_H_BLANKING)
+#define DVI_V_LINES(m) (m == TVENC_MODE_NTSC ? \
+ NTSC_V_LINES : PAL_V_LINES)
+#define DVI_H_ACTIVE(m) (m == TVENC_MODE_NTSC ? NTSC_X_RES : PAL_X_RES)
+#define DVI_V_ACTIVE(m) (m == TVENC_MODE_NTSC ? NTSC_Y_RES : PAL_Y_RES)
+/* fileds range */
+#define DVI_F1_START(m) 1
+#define DVI_F1_END(m) (DVI_V_LINES(m) / 2)
+#define DVI_F2_START(m) (DVI_F1_END(m) + 1)
+#define DVI_F2_END(m) DVI_V_LINES(m)
+/* blanking range */
+#define DVI_V1_BLANK_START(m) DVI_F1_END(m)
+#define DVI_V1_BLANK_END(m) (DVI_V1_BLANK_START(m) + \
+ (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2)
+#define DVI_V2_BLANK_START(m) DVI_F2_END(m)
+#define DVI_V2_BLANK_END(m) ((DVI_V2_BLANK_START(m) + \
+ (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2 - 1) % \
+ DVI_V_LINES(m))
+
+static struct clk *lcd_clk;
+static struct clk *clk_tv108M_ng;
+static struct clk *clk_tv27M;
+
+static int tvenc_mode;
+
+static void init_tvenc_hw(int mode)
+{
+ /* Reset module */
+ __raw_writel(BM_TVENC_CTRL_SFTRST, REGS_TVENC_BASE + HW_TVENC_CTRL_SET);
+ udelay(10);
+
+ /* Take module out of reset */
+ __raw_writel(BM_TVENC_CTRL_SFTRST | BM_TVENC_CTRL_CLKGATE,
+ REGS_TVENC_BASE + HW_TVENC_CTRL_CLR);
+
+ if (mode == TVENC_MODE_NTSC) {
+ /* Config NTSC-M mode, 8-bit Y/C in, SYNC out */
+ __raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+ BM_TVENC_CONFIG_PAL_SHAPE |
+ BM_TVENC_CONFIG_YGAIN_SEL |
+ BM_TVENC_CONFIG_CGAIN,
+ REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+ __raw_writel(BM_TVENC_CONFIG_FSYNC_PHS |
+ BF_TVENC_CONFIG_SYNC_MODE(0x4),
+ REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+ /* 859 pixels/line for NTSC */
+ __raw_writel(857, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+ __raw_writel(0x21F07C1F, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+ __raw_writel(BM_TVENC_COLORBURST_NBA |
+ BM_TVENC_COLORBURST_PBA,
+ REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+ __raw_writel(BF_TVENC_COLORBURST_NBA(0xc8) |
+ BF_TVENC_COLORBURST_PBA(0x0),
+ REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+ } else if (mode == TVENC_MODE_PAL) {
+ /* Config PAL-B mode, 8-bit Y/C in, SYNC out */
+ __raw_writel(BM_TVENC_CONFIG_SYNC_MODE |
+ BM_TVENC_CONFIG_ENCD_MODE |
+ BM_TVENC_CONFIG_YGAIN_SEL |
+ BM_TVENC_CONFIG_CGAIN |
+ BM_TVENC_CONFIG_FSYNC_PHS,
+ REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR);
+ __raw_writel(BM_TVENC_CONFIG_PAL_SHAPE |
+ BF_TVENC_CONFIG_YGAIN_SEL(0x1)
+ | BF_TVENC_CONFIG_CGAIN(0x1)
+ | BF_TVENC_CONFIG_ENCD_MODE(0x1)
+ | BF_TVENC_CONFIG_SYNC_MODE(0x4),
+ REGS_TVENC_BASE + HW_TVENC_CONFIG_SET);
+
+ /* 863 pixels/line for PAL */
+ __raw_writel(863, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET);
+
+ __raw_writel(0x2A098ACB, REGS_TVENC_BASE + HW_TVENC_COLORSUB0);
+ __raw_writel(BM_TVENC_COLORBURST_NBA |
+ BM_TVENC_COLORBURST_PBA,
+ REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR);
+ __raw_writel(BF_TVENC_COLORBURST_NBA(0xd6) |
+ BF_TVENC_COLORBURST_PBA(0x2a),
+ REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET);
+ }
+
+ /* Power up DAC */
+ __raw_writel(BM_TVENC_DACCTRL_GAINDN |
+ BM_TVENC_DACCTRL_GAINUP |
+ BM_TVENC_DACCTRL_PWRUP1 |
+ BM_TVENC_DACCTRL_DUMP_TOVDD1 |
+ BF_TVENC_DACCTRL_RVAL(0x3),
+ REGS_TVENC_BASE + HW_TVENC_DACCTRL);
+
+ /* set all to zero is a requirement for NTSC */
+ __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION0);
+ __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION1);
+ __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION2);
+ __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION3);
+ __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION4);
+}
+
+static int init_panel(struct device *dev, dma_addr_t phys, int memsize,
+ struct mxs_platform_fb_entry *pentry)
+{
+ int ret = 0;
+
+ lcd_clk = clk_get(dev, "lcdif");
+ clk_enable(lcd_clk);
+ clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns);/* kHz */
+
+ clk_tv108M_ng = clk_get(NULL, "tv108M_ng");
+ clk_tv27M = clk_get(NULL, "tv27M");
+ clk_enable(clk_tv108M_ng);
+ clk_enable(clk_tv27M);
+
+ tvenc_mode = pentry->x_res == NTSC_Y_RES ? TVENC_MODE_NTSC :
+ TVENC_MODE_PAL;
+
+ init_tvenc_hw(tvenc_mode);
+
+ setup_dvi_panel(DVI_H_ACTIVE(tvenc_mode), DVI_V_ACTIVE(tvenc_mode),
+ DVI_H_BLANKING(tvenc_mode), DVI_V_LINES(tvenc_mode),
+ DVI_V1_BLANK_START(tvenc_mode),
+ DVI_V1_BLANK_END(tvenc_mode),
+ DVI_V2_BLANK_START(tvenc_mode),
+ DVI_V2_BLANK_END(tvenc_mode),
+ DVI_F1_START(tvenc_mode), DVI_F1_END(tvenc_mode),
+ DVI_F2_START(tvenc_mode), DVI_F2_END(tvenc_mode));
+
+ ret = mxs_lcdif_dma_init(dev, phys, memsize);
+ mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry);
+
+ return ret;
+}
+
+static void release_panel(struct device *dev,
+ struct mxs_platform_fb_entry *pentry)
+{
+ mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry);
+ release_dvi_panel();
+
+ mxs_lcdif_dma_release();
+
+ clk_disable(clk_tv108M_ng);
+ clk_disable(clk_tv27M);
+ clk_disable(lcd_clk);
+ clk_put(clk_tv108M_ng);
+ clk_put(clk_tv27M);
+ clk_put(lcd_clk);
+}
+
+static int blank_panel(int blank)
+{
+ int ret = 0, count;
+
+ switch (blank) {
+ case FB_BLANK_NORMAL:
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ case FB_BLANK_POWERDOWN:
+ __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+ /* Wait until current transfer is complete, max 30ms */
+ for (count = 30000; count > 0; count--) {
+ if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
+ BM_LCDIF_STAT_TXFIFO_EMPTY)
+ break;
+ udelay(1);
+ }
+ break;
+
+ case FB_BLANK_UNBLANK:
+ __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+ break;
+
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static struct mxs_platform_fb_entry ntsc_fb_entry = {
+ .name = "tvenc_ntsc",
+ /* x/y swapped */
+ .x_res = NTSC_Y_RES,
+ .y_res = NTSC_X_RES,
+ .bpp = 32,
+ /* the pix_clk should be near 27Mhz for proper syncronization */
+ .cycle_time_ns = 37,
+ .lcd_type = MXS_LCD_PANEL_DVI,
+ .init_panel = init_panel,
+ .release_panel = release_panel,
+ .blank_panel = blank_panel,
+ .run_panel = mxs_lcdif_run,
+ .pan_display = mxs_lcdif_pan_display,
+};
+
+static struct mxs_platform_fb_entry pal_fb_entry = {
+ .name = "tvenc_pal",
+ /* x/y swapped */
+ .x_res = PAL_Y_RES,
+ .y_res = PAL_X_RES,
+ .bpp = 32,
+ /* the pix_clk should be near 27Mhz for proper syncronization */
+ .cycle_time_ns = 37,
+ .lcd_type = MXS_LCD_PANEL_DVI,
+ .init_panel = init_panel,
+ .release_panel = release_panel,
+ .blank_panel = blank_panel,
+ .run_panel = mxs_lcdif_run,
+ .pan_display = mxs_lcdif_pan_display,
+};
+
+static int __init register_devices(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-fb", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return -ENODEV;
+
+ mxs_lcd_register_entry(&ntsc_fb_entry, pdev->dev.platform_data);
+ mxs_lcd_register_entry(&pal_fb_entry, pdev->dev.platform_data);
+ return 0;
+}
+
+subsys_initcall(register_devices);
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-16 14:21:33 +0000