diff options
Diffstat (limited to 'include/asm-arm/plat-s3c24xx/regs-spi.h')
| -rw-r--r-- | include/asm-arm/plat-s3c24xx/regs-spi.h | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h index 2b35479ee35c..9fcb1f245097 100644 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h +++ b/include/asm-arm/plat-s3c24xx/regs-spi.h @@ -78,5 +78,101 @@ #define S3C2412_RXFIFO (0x18) #define S3C2412_SPFIC (0x24) +/* + * High Speed SPI registers and control bits + * Coming from the SMDK (Luis Galdos) + */ +#define S3C2443_SPI0_CH_CFG (0x00) /* Configuration */ +#define S3C2443_SPI0_CLK_CFG (0x04) /* Clock configuration */ +#define S3C2443_SPI0_MODE_CFG (0x08) /* FIFO control */ +#define S3C2443_SPI0_SLAVE_SEL (0x0C) /* Slave selection */ +#define S3C2443_SPI0_INT_EN (0x10) /* interrupt enable */ +#define S3C2443_SPI0_STATUS (0x14) /* status */ +#define S3C2443_SPI0_TX_DATA (0x18) /* TX data */ +#define S3C2443_SPI0_RX_DATA (0x1C) /* RX data */ +#define S3C2443_SPI0_PACKET_CNT (0x20) /* Count how many data master gets */ +#define S3C2443_SPI0_PENDING_CLR (0x24) /* Pending clear */ + +#define S3C2443_SPI0_TX_DATA_PA (0x52000018) +#define S3C2443_SPI0_RX_DATA_PA (0x5200001C) + +#define S3C2443_SPI0_CH_SW_RST (1<<5) +#define S3C2443_SPI0_CH_MASTER (0<<4) +#define S3C2443_SPI0_CH_SLAVE (1<<4) +#define S3C2443_SPI0_CH_RISING (0<<3) +#define S3C2443_SPI0_CH_FALLING (1<<3) +#define S3C2443_SPI0_CH_FORMAT_A (0<<2) +#define S3C2443_SPI0_CH_FORMAT_B (1<<2) +#define S3C2443_SPI0_CH_RXCH_OFF (0<<1) +#define S3C2443_SPI0_CH_RXCH_ON (1<<1) +#define S3C2443_SPI0_CH_TXCH_OFF (0<<0) +#define S3C2443_SPI0_CH_TXCH_ON (1<<0) + +#define S3C2443_SPI0_CLKSEL_PCLK (0<<9) +#define S3C2443_SPI0_CLKSEL_HCLK (1<<9) +#define S3C2443_SPI0_CLKSEL_ECLK (2<<9) +#define S3C2443_SPI0_CLKSEL_EPLL (3<<9) +#define S3C2443_SPI0_ENCLK_DISABLE (0<<8) +#define S3C2443_SPI0_ENCLK_ENABLE (1<<8) +#define S3C2443_SPI0_CLK_PRE_MASK (0xff) + +#define S3C2443_SPI0_MODE_CH_TSZ_BYTE (0<<18) +#define S3C2443_SPI0_MODE_CH_TSZ_WORD (1<<18) +#define S3C2443_SPI0_FEED_BACK_DELAY (1<<17) +#define S3C2443_SPI0_MODE_RXDMA_OFF (0<<2) +#define S3C2443_SPI0_MODE_RXDMA_ON (1<<2) +#define S3C2443_SPI0_MODE_TXDMA_OFF (0<<1) +#define S3C2443_SPI0_MODE_TXDMA_ON (1<<1) +#define S3C2443_SPI0_MODE_SINGLE (0<<0) +#define S3C2443_SPI0_MODE_4BURST (1<<0) + +#define S3C2443_SPI0_STUS_TX_DONE (1<<21) +#define S3C2443_SPI0_STUS_TRAILCNT_ZERO (1<<20) + +#define S3C2443_SPI0_STUS_TX_LEVEL(x) ((x >> 6) & 0x7F) +#define S3C2443_SPI0_STUS_RX_LEVEL(x) ((x >> 13) & 0x7F) + +#define S3C2443_SPI0_STUS_RX_OVERRUN_ERR (1<<5) +#define S3C2443_SPI0_STUS_RX_UNDERRUN_ERR (1<<4) +#define S3C2443_SPI0_STUS_TX_OVERRUN_ERR (1<<3) +#define S3C2443_SPI0_STUS_TX_UNDERRUN_ERR (1<<2) +#define S3C2443_SPI0_STUS_RX_FIFORDY (1<<1) +#define S3C2443_SPI0_STUS_TX_FIFORDY (1<<0) + +#define S3C2443_SPI0_SLAVE_SIG_ACT (0<<0) +#define S3C2443_SPI0_SLAVE_SIG_INACT (1<<0) + +#define S3C2443_SPI0_STUS_TX_DONE (1<<21) +#define S3C2443_SPI0_STUS_TRAILCNT_ZERO (1<<20) +#define S3C2443_SPI0_STUS_RX_OVERRUN (1<<5) +#define S3C2443_SPI0_STUS_RX_UNDERRUN (1<<4) +#define S3C2443_SPI0_STUS_TX_OVERRUN (1<<3) +#define S3C2443_SPI0_STUS_TX_UNDERRUN (1<<2) +#define S3C2443_SPI0_STUS_RX_FIFORDY (1<<1) +#define S3C2443_SPI0_STUS_TX_FIFORDY (1<<0) + +#define S3C2443_SPI0_INT_TRAILING_DIS (0<<6) +#define S3C2443_SPI0_INT_TRAILING_EN (1<<6) +#define S3C2443_SPI0_INT_RX_OVERRUN_DIS (0<<5) +#define S3C2443_SPI0_INT_RX_OVERRUN_EN (1<<5) +#define S3C2443_SPI0_INT_RX_UNDERRUN_DIS (0<<4) +#define S3C2443_SPI0_INT_RX_UNDERRUN_EN (1<<4) +#define S3C2443_SPI0_INT_TX_OVERRUN_DIS (0<<3) +#define S3C2443_SPI0_INT_TX_OVERRUN_EN (1<<3) +#define S3C2443_SPI0_INT_TX_UNDERRUN_DIS (0<<2) +#define S3C2443_SPI0_INT_TX_UNDERRUN_EN (1<<2) +#define S3C2443_SPI0_INT_RX_FIFORDY_DIS (0<<1) +#define S3C2443_SPI0_INT_RX_FIFORDY_EN (1<<1) +#define S3C2443_SPI0_INT_TX_FIFORDY_DIS (0<<0) +#define S3C2443_SPI0_INT_TX_FIFORDY_EN (1<<0) + +#define S3C2443_SPI0_PACKET_CNT_DIS (0<<16) +#define S3C2443_SPI0_PACKET_CNT_EN (1<<16) + +#define S3C2443_SPI0_PND_TX_UNDERRUN_CLR (1<<4) +#define S3C2443_SPI0_PND_TX_OVERRUN_CLR (1<<3) +#define S3C2443_SPI0_PND_RX_UNDERRUN_CLR (1<<2) +#define S3C2443_SPI0_PND_RX_OVERRUN_CLR (1<<1) +#define S3C2443_SPI0_PND_TRAILING_CLR (1<<0) #endif /* __ASM_ARCH_REGS_SPI_H */ |