diff options
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/mach-atlas/mc146818rtc.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mips-boards/atlasint.h | 124 |
2 files changed, 87 insertions, 39 deletions
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h index fc09928571d6..a73a5698420c 100644 --- a/include/asm-mips/mach-atlas/mc146818rtc.h +++ b/include/asm-mips/mach-atlas/mc146818rtc.h @@ -33,7 +33,7 @@ #define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8) #define RTC_IO_EXTENT 0x100 #define RTC_IOMAPPED 0 -#define RTC_IRQ ATLASINT_RTC +#define RTC_IRQ ATLAS_INT_RTC static inline unsigned char CMOS_READ(unsigned long addr) { diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h index fd7ebc54fa90..b15e4ea0b091 100644 --- a/include/asm-mips/mips-boards/atlasint.h +++ b/include/asm-mips/mips-boards/atlasint.h @@ -1,6 +1,7 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> * * ######################################################################## * @@ -25,41 +26,88 @@ #ifndef _MIPS_ATLASINT_H #define _MIPS_ATLASINT_H -#define ATLASINT_BASE 1 -#define ATLASINT_UART (ATLASINT_BASE+0) -#define ATLASINT_TIM0 (ATLASINT_BASE+1) -#define ATLASINT_RES2 (ATLASINT_BASE+2) -#define ATLASINT_RES3 (ATLASINT_BASE+3) -#define ATLASINT_RTC (ATLASINT_BASE+4) -#define ATLASINT_COREHI (ATLASINT_BASE+5) -#define ATLASINT_CORELO (ATLASINT_BASE+6) -#define ATLASINT_RES7 (ATLASINT_BASE+7) -#define ATLASINT_PCIA (ATLASINT_BASE+8) -#define ATLASINT_PCIB (ATLASINT_BASE+9) -#define ATLASINT_PCIC (ATLASINT_BASE+10) -#define ATLASINT_PCID (ATLASINT_BASE+11) -#define ATLASINT_ENUM (ATLASINT_BASE+12) -#define ATLASINT_DEG (ATLASINT_BASE+13) -#define ATLASINT_ATXFAIL (ATLASINT_BASE+14) -#define ATLASINT_INTA (ATLASINT_BASE+15) -#define ATLASINT_INTB (ATLASINT_BASE+16) -#define ATLASINT_ETH ATLASINT_INTB -#define ATLASINT_INTC (ATLASINT_BASE+17) -#define ATLASINT_SCSI ATLASINT_INTC -#define ATLASINT_INTD (ATLASINT_BASE+18) -#define ATLASINT_SERR (ATLASINT_BASE+19) -#define ATLASINT_RES20 (ATLASINT_BASE+20) -#define ATLASINT_RES21 (ATLASINT_BASE+21) -#define ATLASINT_RES22 (ATLASINT_BASE+22) -#define ATLASINT_RES23 (ATLASINT_BASE+23) -#define ATLASINT_RES24 (ATLASINT_BASE+24) -#define ATLASINT_RES25 (ATLASINT_BASE+25) -#define ATLASINT_RES26 (ATLASINT_BASE+26) -#define ATLASINT_RES27 (ATLASINT_BASE+27) -#define ATLASINT_RES28 (ATLASINT_BASE+28) -#define ATLASINT_RES29 (ATLASINT_BASE+29) -#define ATLASINT_RES30 (ATLASINT_BASE+30) -#define ATLASINT_RES31 (ATLASINT_BASE+31) -#define ATLASINT_END (ATLASINT_BASE+31) +/* + * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) + */ +#define MIPSCPU_INT_BASE 0 + +/* CPU interrupt offsets */ +#define MIPSCPU_INT_SW0 0 +#define MIPSCPU_INT_SW1 1 +#define MIPSCPU_INT_MB0 2 +#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0 +#define MIPSCPU_INT_MB1 3 +#define MIPSCPU_INT_MB2 4 +#define MIPSCPU_INT_MB3 5 +#define MIPSCPU_INT_MB4 6 +#define MIPSCPU_INT_CPUCTR 7 + +/* + * Interrupts 8..39 are used for Atlas interrupt controller interrupts + */ +#define ATLAS_INT_BASE 8 +#define ATLAS_INT_UART (ATLAS_INT_BASE + 0) +#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1) +#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2) +#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3) +#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4) +#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5) +#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6) +#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7) +#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8) +#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9) +#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10) +#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11) +#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12) +#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13) +#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14) +#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15) +#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16) +#define ATLAS_INT_ETH ATLAS_INT_INTB +#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17) +#define ATLAS_INT_SCSI ATLAS_INT_INTC +#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18) +#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19) +#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20) +#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21) +#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22) +#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23) +#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24) +#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25) +#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26) +#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27) +#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28) +#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29) +#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30) +#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31) +#define ATLAS_INT_END (ATLAS_INT_BASE + 31) + +/* + * Interrupts 64..127 are used for Soc-it Classic interrupts + */ +#define MSC01C_INT_BASE 64 + +/* SOC-it Classic interrupt offsets */ +#define MSC01C_INT_TMR 0 +#define MSC01C_INT_PCI 1 + +/* + * Interrupts 64..127 are used for Soc-it EIC interrupts + */ +#define MSC01E_INT_BASE 64 + +/* SOC-it EIC interrupt offsets */ +#define MSC01E_INT_SW0 1 +#define MSC01E_INT_SW1 2 +#define MSC01E_INT_MB0 3 +#define MSC01E_INT_ATLAS MSC01E_INT_MB0 +#define MSC01E_INT_MB1 4 +#define MSC01E_INT_MB2 5 +#define MSC01E_INT_MB3 6 +#define MSC01E_INT_MB4 7 +#define MSC01E_INT_TMR 8 +#define MSC01E_INT_PCI 9 +#define MSC01E_INT_PERFCTR 10 +#define MSC01E_INT_CPUCTR 11 #endif /* !(_MIPS_ATLASINT_H) */ |