diff options
Diffstat (limited to 'include/asm-ppc64')
| -rw-r--r-- | include/asm-ppc64/a.out.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc64/bug.h | 7 | ||||
| -rw-r--r-- | include/asm-ppc64/elf.h | 8 | ||||
| -rw-r--r-- | include/asm-ppc64/imalloc.h | 24 | ||||
| -rw-r--r-- | include/asm-ppc64/mmu.h | 193 | ||||
| -rw-r--r-- | include/asm-ppc64/mmu_context.h | 82 | ||||
| -rw-r--r-- | include/asm-ppc64/page.h | 30 | ||||
| -rw-r--r-- | include/asm-ppc64/pgalloc.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc64/pgtable.h | 156 | ||||
| -rw-r--r-- | include/asm-ppc64/signal.h | 33 | ||||
| -rw-r--r-- | include/asm-ppc64/spinlock.h | 8 | ||||
| -rw-r--r-- | include/asm-ppc64/xics.h | 3 |
12 files changed, 256 insertions, 292 deletions
diff --git a/include/asm-ppc64/a.out.h b/include/asm-ppc64/a.out.h index 802338efcb19..3871e252a6f1 100644 --- a/include/asm-ppc64/a.out.h +++ b/include/asm-ppc64/a.out.h @@ -1,8 +1,6 @@ #ifndef __PPC64_A_OUT_H__ #define __PPC64_A_OUT_H__ -#include <asm/ppcdebug.h> - /* * c 2001 PPC 64 Team, IBM Corp * diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h index db31dd22233c..169868fa307d 100644 --- a/include/asm-ppc64/bug.h +++ b/include/asm-ppc64/bug.h @@ -26,6 +26,8 @@ struct bug_entry *find_bug(unsigned long bugaddr); */ #define BUG_WARNING_TRAP 0x1000000 +#ifdef CONFIG_BUG + #define BUG() do { \ __asm__ __volatile__( \ "1: twi 31,0,0\n" \ @@ -55,11 +57,12 @@ struct bug_entry *find_bug(unsigned long bugaddr); "i" (__FILE__), "i" (__FUNCTION__)); \ } while (0) -#endif - #define HAVE_ARCH_BUG #define HAVE_ARCH_BUG_ON #define HAVE_ARCH_WARN_ON +#endif +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h index 8457d90244fb..6c42d61bedd1 100644 --- a/include/asm-ppc64/elf.h +++ b/include/asm-ppc64/elf.h @@ -229,9 +229,13 @@ do { \ /* * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. + * have the READ_IMPLIES_EXEC personality flag set automatically. This + * is only required to work around bugs in old 32bit toolchains. Since + * the 64bit ABI has never had these issues dont enable the workaround + * even if we have an executable stack. */ -#define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) +#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ + (exec_stk != EXSTACK_DISABLE_X) : 0) #endif diff --git a/include/asm-ppc64/imalloc.h b/include/asm-ppc64/imalloc.h new file mode 100644 index 000000000000..3a45e918bf16 --- /dev/null +++ b/include/asm-ppc64/imalloc.h @@ -0,0 +1,24 @@ +#ifndef _PPC64_IMALLOC_H +#define _PPC64_IMALLOC_H + +/* + * Define the address range of the imalloc VM area. + */ +#define PHBS_IO_BASE IOREGIONBASE +#define IMALLOC_BASE (IOREGIONBASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */ +#define IMALLOC_END (IOREGIONBASE + EADDR_MASK) + + +/* imalloc region types */ +#define IM_REGION_UNUSED 0x1 +#define IM_REGION_SUBSET 0x2 +#define IM_REGION_EXISTS 0x4 +#define IM_REGION_OVERLAP 0x8 +#define IM_REGION_SUPERSET 0x10 + +extern struct vm_struct * im_get_free_area(unsigned long size); +extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size, + int region_type); +unsigned long im_free(void *addr); + +#endif /* _PPC64_IMALLOC_H */ diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h index 188987e9d9d4..c78282a67d8e 100644 --- a/include/asm-ppc64/mmu.h +++ b/include/asm-ppc64/mmu.h @@ -15,19 +15,10 @@ #include <linux/config.h> #include <asm/page.h> -#include <linux/stringify.h> -#ifndef __ASSEMBLY__ - -/* Time to allow for more things here */ -typedef unsigned long mm_context_id_t; -typedef struct { - mm_context_id_t id; -#ifdef CONFIG_HUGETLB_PAGE - pgd_t *huge_pgdir; - u16 htlb_segs; /* bitmask */ -#endif -} mm_context_t; +/* + * Segment table + */ #define STE_ESID_V 0x80 #define STE_ESID_KS 0x20 @@ -36,15 +27,48 @@ typedef struct { #define STE_VSID_SHIFT 12 -struct stab_entry { - unsigned long esid_data; - unsigned long vsid_data; -}; +/* Location of cpu0's segment table */ +#define STAB0_PAGE 0x9 +#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) +#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR) + +/* + * SLB + */ -/* Hardware Page Table Entry */ +#define SLB_NUM_BOLTED 3 +#define SLB_CACHE_ENTRIES 8 + +/* Bits in the SLB ESID word */ +#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ + +/* Bits in the SLB VSID word */ +#define SLB_VSID_SHIFT 12 +#define SLB_VSID_KS ASM_CONST(0x0000000000000800) +#define SLB_VSID_KP ASM_CONST(0x0000000000000400) +#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ +#define SLB_VSID_L ASM_CONST(0x0000000000000100) /* largepage 16M */ +#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ + +#define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C) +#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS) + +/* + * Hash table + */ #define HPTES_PER_GROUP 8 +/* Values for PP (assumes Ks=0, Kp=1) */ +/* pp0 will always be 0 for linux */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +#ifndef __ASSEMBLY__ + +/* Hardware Page Table Entry */ typedef struct { unsigned long avpn:57; /* vsid | api == avpn */ unsigned long : 2; /* Software use */ @@ -90,14 +114,6 @@ typedef struct { } dw1; } HPTE; -/* Values for PP (assumes Ks=0, Kp=1) */ -/* pp0 will always be 0 for linux */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - - extern HPTE * htab_address; extern unsigned long htab_hash_mask; @@ -174,31 +190,70 @@ extern int __hash_page(unsigned long ea, unsigned long access, extern void htab_finish_init(void); +extern void hpte_init_native(void); +extern void hpte_init_lpar(void); +extern void hpte_init_iSeries(void); + +extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, + unsigned long va, unsigned long prpn, + int secondary, unsigned long hpteflags, + int bolted, int large); +extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, + unsigned long prpn, int secondary, + unsigned long hpteflags, int bolted, int large); + #endif /* __ASSEMBLY__ */ /* - * Location of cpu0's segment table + * VSID allocation + * + * We first generate a 36-bit "proto-VSID". For kernel addresses this + * is equal to the ESID, for user addresses it is: + * (context << 15) | (esid & 0x7fff) + * + * The two forms are distinguishable because the top bit is 0 for user + * addresses, whereas the top two bits are 1 for kernel addresses. + * Proto-VSIDs with the top two bits equal to 0b10 are reserved for + * now. + * + * The proto-VSIDs are then scrambled into real VSIDs with the + * multiplicative hash: + * + * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS + * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 + * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF + * + * This scramble is only well defined for proto-VSIDs below + * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are + * reserved. VSID_MULTIPLIER is prime, so in particular it is + * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. + * Because the modulus is 2^n-1 we can compute it efficiently without + * a divide or extra multiply (see below). + * + * This scheme has several advantages over older methods: + * + * - We have VSIDs allocated for every kernel address + * (i.e. everything above 0xC000000000000000), except the very top + * segment, which simplifies several things. + * + * - We allow for 15 significant bits of ESID and 20 bits of + * context for user addresses. i.e. 8T (43 bits) of address space for + * up to 1M contexts (although the page table structure and context + * allocation will need changes to take advantage of this). + * + * - The scramble function gives robust scattering in the hash + * table (at least based on some initial results). The previous + * method was more susceptible to pathological cases giving excessive + * hash collisions. + */ +/* + * WARNING - If you change these you must make sure the asm + * implementations in slb_allocate (slb_low.S), do_stab_bolted + * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly. + * + * You'll also need to change the precomputed VSID values in head.S + * which are used by the iSeries firmware. */ -#define STAB0_PAGE 0x9 -#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) -#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR) - -#define SLB_NUM_BOLTED 3 -#define SLB_CACHE_ENTRIES 8 - -/* Bits in the SLB ESID word */ -#define SLB_ESID_V 0x0000000008000000 /* entry is valid */ - -/* Bits in the SLB VSID word */ -#define SLB_VSID_SHIFT 12 -#define SLB_VSID_KS 0x0000000000000800 -#define SLB_VSID_KP 0x0000000000000400 -#define SLB_VSID_N 0x0000000000000200 /* no-execute */ -#define SLB_VSID_L 0x0000000000000100 /* largepage (4M) */ -#define SLB_VSID_C 0x0000000000000080 /* class */ - -#define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C) -#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS) #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */ #define VSID_BITS 36 @@ -239,4 +294,50 @@ extern void htab_finish_init(void); srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \ add rt,rt,rx + +#ifndef __ASSEMBLY__ + +typedef unsigned long mm_context_id_t; + +typedef struct { + mm_context_id_t id; +#ifdef CONFIG_HUGETLB_PAGE + pgd_t *huge_pgdir; + u16 htlb_segs; /* bitmask */ +#endif +} mm_context_t; + + +static inline unsigned long vsid_scramble(unsigned long protovsid) +{ +#if 0 + /* The code below is equivalent to this function for arguments + * < 2^VSID_BITS, which is all this should ever be called + * with. However gcc is not clever enough to compute the + * modulus (2^n-1) without a second multiply. */ + return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); +#else /* 1 */ + unsigned long x; + + x = protovsid * VSID_MULTIPLIER; + x = (x >> VSID_BITS) + (x & VSID_MODULUS); + return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; +#endif /* 1 */ +} + +/* This is only valid for addresses >= KERNELBASE */ +static inline unsigned long get_kernel_vsid(unsigned long ea) +{ + return vsid_scramble(ea >> SID_SHIFT); +} + +/* This is only valid for user addresses (which are below 2^41) */ +static inline unsigned long get_vsid(unsigned long context, unsigned long ea) +{ + return vsid_scramble((context << USER_ESID_BITS) + | (ea >> SID_SHIFT)); +} + +#endif /* __ASSEMBLY */ + #endif /* _PPC64_MMU_H_ */ diff --git a/include/asm-ppc64/mmu_context.h b/include/asm-ppc64/mmu_context.h index c2e8e0466383..77a743402db4 100644 --- a/include/asm-ppc64/mmu_context.h +++ b/include/asm-ppc64/mmu_context.h @@ -84,86 +84,4 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) local_irq_restore(flags); } -/* VSID allocation - * =============== - * - * We first generate a 36-bit "proto-VSID". For kernel addresses this - * is equal to the ESID, for user addresses it is: - * (context << 15) | (esid & 0x7fff) - * - * The two forms are distinguishable because the top bit is 0 for user - * addresses, whereas the top two bits are 1 for kernel addresses. - * Proto-VSIDs with the top two bits equal to 0b10 are reserved for - * now. - * - * The proto-VSIDs are then scrambled into real VSIDs with the - * multiplicative hash: - * - * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS - * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 - * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF - * - * This scramble is only well defined for proto-VSIDs below - * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are - * reserved. VSID_MULTIPLIER is prime, so in particular it is - * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. - * Because the modulus is 2^n-1 we can compute it efficiently without - * a divide or extra multiply (see below). - * - * This scheme has several advantages over older methods: - * - * - We have VSIDs allocated for every kernel address - * (i.e. everything above 0xC000000000000000), except the very top - * segment, which simplifies several things. - * - * - We allow for 15 significant bits of ESID and 20 bits of - * context for user addresses. i.e. 8T (43 bits) of address space for - * up to 1M contexts (although the page table structure and context - * allocation will need changes to take advantage of this). - * - * - The scramble function gives robust scattering in the hash - * table (at least based on some initial results). The previous - * method was more susceptible to pathological cases giving excessive - * hash collisions. - */ - -/* - * WARNING - If you change these you must make sure the asm - * implementations in slb_allocate(), do_stab_bolted and mmu.h - * (ASM_VSID_SCRAMBLE macro) are changed accordingly. - * - * You'll also need to change the precomputed VSID values in head.S - * which are used by the iSeries firmware. - */ - -static inline unsigned long vsid_scramble(unsigned long protovsid) -{ -#if 0 - /* The code below is equivalent to this function for arguments - * < 2^VSID_BITS, which is all this should ever be called - * with. However gcc is not clever enough to compute the - * modulus (2^n-1) without a second multiply. */ - return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); -#else /* 1 */ - unsigned long x; - - x = protovsid * VSID_MULTIPLIER; - x = (x >> VSID_BITS) + (x & VSID_MODULUS); - return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; -#endif /* 1 */ -} - -/* This is only valid for addresses >= KERNELBASE */ -static inline unsigned long get_kernel_vsid(unsigned long ea) -{ - return vsid_scramble(ea >> SID_SHIFT); -} - -/* This is only valid for user addresses (which are below 2^41) */ -static inline unsigned long get_vsid(unsigned long context, unsigned long ea) -{ - return vsid_scramble((context << USER_ESID_BITS) - | (ea >> SID_SHIFT)); -} - #endif /* __PPC64_MMU_CONTEXT_H */ diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h index 20e0f19324e8..bcd21789d3b7 100644 --- a/include/asm-ppc64/page.h +++ b/include/asm-ppc64/page.h @@ -23,7 +23,6 @@ #define PAGE_SHIFT 12 #define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -#define PAGE_OFFSET_MASK (PAGE_SIZE-1) #define SID_SHIFT 28 #define SID_MASK 0xfffffffffUL @@ -85,9 +84,6 @@ /* align addr on a size boundary - adjust address up if needed */ #define _ALIGN(addr,size) _ALIGN_UP(addr,size) -/* to align the pointer to the (next) double word boundary */ -#define DOUBLEWORD_ALIGN(addr) _ALIGN(addr,sizeof(unsigned long)) - /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE) @@ -100,7 +96,6 @@ #define REGION_SIZE 4UL #define REGION_SHIFT 60UL #define REGION_MASK (((1UL<<REGION_SIZE)-1UL)<<REGION_SHIFT) -#define REGION_STRIDE (1UL << REGION_SHIFT) static __inline__ void clear_page(void *addr) { @@ -209,13 +204,13 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ #define VMALLOCBASE ASM_CONST(0xD000000000000000) #define IOREGIONBASE ASM_CONST(0xE000000000000000) -#define IO_REGION_ID (IOREGIONBASE>>REGION_SHIFT) -#define VMALLOC_REGION_ID (VMALLOCBASE>>REGION_SHIFT) -#define KERNEL_REGION_ID (KERNELBASE>>REGION_SHIFT) +#define IO_REGION_ID (IOREGIONBASE >> REGION_SHIFT) +#define VMALLOC_REGION_ID (VMALLOCBASE >> REGION_SHIFT) +#define KERNEL_REGION_ID (KERNELBASE >> REGION_SHIFT) #define USER_REGION_ID (0UL) -#define REGION_ID(X) (((unsigned long)(X))>>REGION_SHIFT) +#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) -#define __bpn_to_ba(x) ((((unsigned long)(x))<<PAGE_SHIFT) + KERNELBASE) +#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE) #define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT) #define __va(x) ((void *)((unsigned long)(x) + KERNELBASE)) @@ -252,10 +247,19 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ /* * This is the default if a program doesn't have a PT_GNU_STACK - * program header entry. + * program header entry. The PPC64 ELF ABI has a non executable stack + * stack by default, so in the absense of a PT_GNU_STACK program header + * we turn execute permission off. */ -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#define VM_STACK_DEFAULT_FLAGS \ + (test_thread_flag(TIF_32BIT) ? \ + VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) #endif /* __KERNEL__ */ #endif /* _PPC64_PAGE_H */ diff --git a/include/asm-ppc64/pgalloc.h b/include/asm-ppc64/pgalloc.h index 16232d740173..4fc4b739b380 100644 --- a/include/asm-ppc64/pgalloc.h +++ b/include/asm-ppc64/pgalloc.h @@ -27,7 +27,7 @@ pgd_free(pgd_t *pgd) kmem_cache_free(zero_cache, pgd); } -#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD) +#define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD) static inline pmd_t * pmd_alloc_one(struct mm_struct *mm, unsigned long addr) diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index a26120517c54..264c4f7993be 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -1,8 +1,6 @@ #ifndef _PPC64_PGTABLE_H #define _PPC64_PGTABLE_H -#include <asm-generic/4level-fixup.h> - /* * This file contains the functions and defines necessary to modify and use * the ppc64 hashed page table. @@ -17,15 +15,7 @@ #include <asm/tlbflush.h> #endif /* __ASSEMBLY__ */ -/* PMD_SHIFT determines what a second-level page table entry can map */ -#define PMD_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3) + (PAGE_SHIFT - 2)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) +#include <asm-generic/pgtable-nopud.h> /* * Entries per page directory level. The PTE level must use a 64b record @@ -40,40 +30,30 @@ #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) -#define USER_PTRS_PER_PGD (1024) -#define FIRST_USER_ADDRESS 0 +/* PMD_SHIFT determines what a second-level page table entry can map */ +#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) -#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ - PGD_INDEX_SIZE + PAGE_SHIFT) +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +#define FIRST_USER_ADDRESS 0 /* * Size of EA range mapped by our pagetables. */ -#define PGTABLE_EA_BITS 41 -#define PGTABLE_EA_MASK ((1UL<<PGTABLE_EA_BITS)-1) +#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ + PGD_INDEX_SIZE + PAGE_SHIFT) +#define EADDR_MASK ((1UL << EADDR_SIZE) - 1) /* * Define the address range of the vmalloc VM area. */ #define VMALLOC_START (0xD000000000000000ul) -#define VMALLOC_END (VMALLOC_START + PGTABLE_EA_MASK) - -/* - * Define the address range of the imalloc VM area. - * (used for ioremap) - */ -#define IMALLOC_START (ioremap_bot) -#define IMALLOC_VMADDR(x) ((unsigned long)(x)) -#define PHBS_IO_BASE (0xE000000000000000ul) /* Reserve 2 gigs for PHBs */ -#define IMALLOC_BASE (0xE000000080000000ul) -#define IMALLOC_END (IMALLOC_BASE + PGTABLE_EA_MASK) - -/* - * Define the user address range - */ -#define USER_START (0UL) -#define USER_END (USER_START + PGTABLE_EA_MASK) - +#define VMALLOC_END (VMALLOC_START + EADDR_MASK) /* * Bits in a linux-style PTE. These match the bits in the @@ -168,10 +148,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; /* shift to put page number into pte */ #define PTE_SHIFT (17) -/* We allow 2^41 bytes of real memory, so we need 29 bits in the PMD - * to give the PTE page number. The bottom two bits are for flags. */ -#define PMD_TO_PTEPAGE_SHIFT (2) - #ifdef CONFIG_HUGETLB_PAGE #ifndef __ASSEMBLY__ @@ -200,13 +176,14 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#define pfn_pte(pfn,pgprot) \ -({ \ - pte_t pte; \ - pte_val(pte) = ((unsigned long)(pfn) << PTE_SHIFT) | \ - pgprot_val(pgprot); \ - pte; \ -}) +static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) +{ + pte_t pte; + + + pte_val(pte) = (pfn << PTE_SHIFT) | pgprot_val(pgprot); + return pte; +} #define pte_modify(_pte, newprot) \ (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))) @@ -220,20 +197,20 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pmd_set(pmdp, ptep) \ - (pmd_val(*(pmdp)) = (__ba_to_bpn(ptep) << PMD_TO_PTEPAGE_SHIFT)) + (pmd_val(*(pmdp)) = __ba_to_bpn(ptep)) #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_bad(pmd) (pmd_val(pmd) == 0) #define pmd_present(pmd) (pmd_val(pmd) != 0) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) -#define pmd_page_kernel(pmd) \ - (__bpn_to_ba(pmd_val(pmd) >> PMD_TO_PTEPAGE_SHIFT)) +#define pmd_page_kernel(pmd) (__bpn_to_ba(pmd_val(pmd))) #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd)) -#define pgd_set(pgdp, pmdp) (pgd_val(*(pgdp)) = (__ba_to_bpn(pmdp))) -#define pgd_none(pgd) (!pgd_val(pgd)) -#define pgd_bad(pgd) ((pgd_val(pgd)) == 0) -#define pgd_present(pgd) (pgd_val(pgd) != 0UL) -#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) -#define pgd_page(pgd) (__bpn_to_ba(pgd_val(pgd))) + +#define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (__ba_to_bpn(pmdp))) +#define pud_none(pud) (!pud_val(pud)) +#define pud_bad(pud) ((pud_val(pud)) == 0UL) +#define pud_present(pud) (pud_val(pud) != 0UL) +#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) +#define pud_page(pud) (__bpn_to_ba(pud_val(pud))) /* * Find an entry in a page-table-directory. We combine the address region @@ -245,12 +222,13 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) /* Find an entry in the second-level page table.. */ -#define pmd_offset(dir,addr) \ - ((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) +#define pmd_offset(pudp,addr) \ + ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) /* Find an entry in the third-level page table.. */ #define pte_offset_kernel(dir,addr) \ - ((pte_t *) pmd_page_kernel(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) + ((pte_t *) pmd_page_kernel(*(dir)) \ + + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) @@ -264,8 +242,6 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); /* to find an entry in the ioremap page-table-directory */ #define pgd_offset_i(address) (ioremap_pgd + pgd_index(address)) -#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) - /* * The following only work if pte_present() is true. * Undefined behaviour if not.. @@ -440,7 +416,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_clear(mm, addr, ptep); flush_tlb_pending(); } - *ptep = __pte(pte_val(pte)) & ~_PAGE_HPTEFLAGS; + *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); } /* Set the dirty and/or accessed bits atomically in a linux PTE, this @@ -485,18 +461,13 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, extern unsigned long ioremap_bot, ioremap_base; -#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) -#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e)) -extern pgd_t swapper_pg_dir[1024]; -extern pgd_t ioremap_dir[1024]; +extern pgd_t swapper_pg_dir[]; +extern pgd_t ioremap_dir[]; extern void paging_init(void); @@ -538,43 +509,11 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); */ #define kern_addr_valid(addr) (1) -#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ - remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) - #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ remap_pfn_range(vma, vaddr, pfn, size, prot) -#define MK_IOSPACE_PFN(space, pfn) (pfn) -#define GET_IOSPACE(pfn) 0 -#define GET_PFN(pfn) (pfn) - void pgtable_cache_init(void); -extern void hpte_init_native(void); -extern void hpte_init_lpar(void); -extern void hpte_init_iSeries(void); - -/* imalloc region types */ -#define IM_REGION_UNUSED 0x1 -#define IM_REGION_SUBSET 0x2 -#define IM_REGION_EXISTS 0x4 -#define IM_REGION_OVERLAP 0x8 -#define IM_REGION_SUPERSET 0x10 - -extern struct vm_struct * im_get_free_area(unsigned long size); -extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size, - int region_type); -unsigned long im_free(void *addr); - -extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, - unsigned long va, unsigned long prpn, - int secondary, unsigned long hpteflags, - int bolted, int large); - -extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, - unsigned long prpn, int secondary, - unsigned long hpteflags, int bolted, int large); - /* * find_linux_pte returns the address of a linux pte for a given * effective address and directory. If not found, it returns zero. @@ -582,19 +521,22 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) { pgd_t *pg; + pud_t *pu; pmd_t *pm; pte_t *pt = NULL; pte_t pte; pg = pgdir + pgd_index(ea); if (!pgd_none(*pg)) { - - pm = pmd_offset(pg, ea); - if (pmd_present(*pm)) { - pt = pte_offset_kernel(pm, ea); - pte = *pt; - if (!pte_present(pte)) - pt = NULL; + pu = pud_offset(pg, ea); + if (!pud_none(*pu)) { + pm = pmd_offset(pu, ea); + if (pmd_present(*pm)) { + pt = pte_offset_kernel(pm, ea); + pte = *pt; + if (!pte_present(pte)) + pt = NULL; + } } } diff --git a/include/asm-ppc64/signal.h b/include/asm-ppc64/signal.h index fe5401adb41b..432df7dd355d 100644 --- a/include/asm-ppc64/signal.h +++ b/include/asm-ppc64/signal.h @@ -96,47 +96,20 @@ typedef struct { #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __sigfunction(int); -typedef __sigfunction __user * __sighandler_t; - -/* Type of the restorer function */ -typedef void __sigrestorer(void); -typedef __sigrestorer __user * __sigrestorer_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; unsigned long sa_flags; - __sigrestorer_t sa_restorer; + __sigrestore_t sa_restorer; }; struct sigaction { __sighandler_t sa_handler; unsigned long sa_flags; - __sigrestorer_t sa_restorer; + __sigrestore_t sa_restorer; sigset_t sa_mask; /* mask last for extensibility */ }; diff --git a/include/asm-ppc64/spinlock.h b/include/asm-ppc64/spinlock.h index a9b2a1162cf7..acd11564dd75 100644 --- a/include/asm-ppc64/spinlock.h +++ b/include/asm-ppc64/spinlock.h @@ -110,7 +110,7 @@ static void __inline__ _raw_spin_lock(spinlock_t *lock) HMT_low(); if (SHARED_PROCESSOR) __spin_yield(lock); - } while (likely(lock->lock != 0)); + } while (unlikely(lock->lock != 0)); HMT_medium(); } } @@ -128,7 +128,7 @@ static void __inline__ _raw_spin_lock_flags(spinlock_t *lock, unsigned long flag HMT_low(); if (SHARED_PROCESSOR) __spin_yield(lock); - } while (likely(lock->lock != 0)); + } while (unlikely(lock->lock != 0)); HMT_medium(); local_irq_restore(flags_dis); } @@ -194,7 +194,7 @@ static void __inline__ _raw_read_lock(rwlock_t *rw) HMT_low(); if (SHARED_PROCESSOR) __rw_yield(rw); - } while (likely(rw->lock < 0)); + } while (unlikely(rw->lock < 0)); HMT_medium(); } } @@ -251,7 +251,7 @@ static void __inline__ _raw_write_lock(rwlock_t *rw) HMT_low(); if (SHARED_PROCESSOR) __rw_yield(rw); - } while (likely(rw->lock != 0)); + } while (unlikely(rw->lock != 0)); HMT_medium(); } } diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h index 0027da4364ac..fdec5e7a7af6 100644 --- a/include/asm-ppc64/xics.h +++ b/include/asm-ppc64/xics.h @@ -30,7 +30,4 @@ struct xics_ipi_struct { extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; -extern unsigned int default_distrib_server; -extern unsigned int interrupt_server_size; - #endif /* _PPC64_KERNEL_XICS_H */ |