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-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h26
-rw-r--r--include/asm-sh/cpu-sh4/cache.h35
-rw-r--r--include/asm-sh/cpu-sh4/cacheflush.h64
-rw-r--r--include/asm-sh/cpu-sh4/dma.h17
-rw-r--r--include/asm-sh/cpu-sh4/freq.h22
-rw-r--r--include/asm-sh/cpu-sh4/mmu_context.h39
-rw-r--r--include/asm-sh/cpu-sh4/rtc.h25
-rw-r--r--include/asm-sh/cpu-sh4/shmparam.h19
-rw-r--r--include/asm-sh/cpu-sh4/sigcontext.h24
-rw-r--r--include/asm-sh/cpu-sh4/sq.h48
-rw-r--r--include/asm-sh/cpu-sh4/timer.h51
-rw-r--r--include/asm-sh/cpu-sh4/ubc.h27
-rw-r--r--include/asm-sh/cpu-sh4/watchdog.h25
13 files changed, 422 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
new file mode 100644
index 000000000000..727634d886ce
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima
+ *
+ * Defitions for the address spaces of the SH-4 CPUs.
+ */
+#ifndef __ASM_CPU_SH4_ADDRSPACE_H
+#define __ASM_CPU_SH4_ADDRSPACE_H
+
+/* Detailed P4SEG */
+#define P4SEG_STORE_QUE (P4SEG)
+#define P4SEG_IC_ADDR 0xf0000000
+#define P4SEG_IC_DATA 0xf1000000
+#define P4SEG_ITLB_ADDR 0xf2000000
+#define P4SEG_ITLB_DATA 0xf3000000
+#define P4SEG_OC_ADDR 0xf4000000
+#define P4SEG_OC_DATA 0xf5000000
+#define P4SEG_TLB_ADDR 0xf6000000
+#define P4SEG_TLB_DATA 0xf7000000
+#define P4SEG_REG_BASE 0xff000000
+
+#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
+
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
new file mode 100644
index 000000000000..1fe20359312c
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -0,0 +1,35 @@
+/*
+ * include/asm-sh/cpu-sh4/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHE_H
+#define __ASM_CPU_SH4_CACHE_H
+
+#define L1_CACHE_SHIFT 5
+
+#define CCR 0xff00001c /* Address of Cache Control Register */
+#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
+#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
+#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
+#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
+#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
+#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
+#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
+#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
+#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
+#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
+
+/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
+#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
+
+#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
+
+#endif /* __ASM_CPU_SH4_CACHE_H */
+
diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h
new file mode 100644
index 000000000000..f323567e085f
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cacheflush.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-sh/cpu-sh4/cacheflush.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
+#define __ASM_CPU_SH4_CACHEFLUSH_H
+
+/*
+ * Caches are broken on SH-4 (unless we use write-through
+ * caching; in which case they're only semi-broken),
+ * so we need them.
+ */
+
+/* Page is 4K, OC size is 16K, there are four lines. */
+#define CACHE_ALIAS 0x00003000
+
+struct page;
+struct mm_struct;
+struct vm_area_struct;
+
+extern void flush_cache_all(void);
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+extern void flush_dcache_page(struct page *pg);
+
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_cache_sigtramp(unsigned long addr);
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+ struct page *page, unsigned long addr,
+ int len);
+
+#define flush_icache_page(vma,pg) do { } while (0)
+
+/* Initialization of P3 area for copy_user_page */
+extern void p3_cache_init(void);
+
+#define PG_mapped PG_arch_1
+
+/* We provide our own get_unmapped_area to avoid cache alias issue */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+#ifdef CONFIG_MMU
+extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
+ unsigned long size, unsigned long flags);
+#else /* CONFIG_MMU */
+static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
+ unsigned long size, unsigned long flags)
+{
+ return 0;
+}
+#endif /* CONFIG_MMU */
+#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
+
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
new file mode 100644
index 000000000000..e2b91adf821a
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_CPU_SH4_DMA_H
+#define __ASM_CPU_SH4_DMA_H
+
+#define SH_DMAC_BASE 0xffa00000
+
+#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
+ SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30})
+#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
+ SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34})
+#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
+ SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38})
+#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
+ SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
+#define DMAOR (SH_DMAC_BASE + 0x40)
+
+#endif /* __ASM_CPU_SH4_DMA_H */
+
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
new file mode 100644
index 000000000000..201d94fd214f
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-sh/cpu-sh4/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_FREQ_H
+#define __ASM_CPU_SH4_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH73180)
+#define FRQCR 0xa4150000
+#else
+#define FRQCR 0xffc00000
+#endif
+#define MIN_DIVISOR_NR 0
+#define MAX_DIVISOR_NR 3
+
+#endif /* __ASM_CPU_SH4_FREQ_H */
+
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
new file mode 100644
index 000000000000..5b64d041f0b9
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-sh/cpu-sh4/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
+#define __ASM_CPU_SH4_MMU_CONTEXT_H
+
+#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
+#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
+#define MMU_TTB 0xFF000008 /* Translation table base register */
+#define MMU_TEA 0xFF00000C /* TLB Exception Address */
+#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
+
+#define MMUCR 0xFF000010 /* MMU Control Register */
+
+#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
+#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
+#define MMU_PAGE_ASSOC_BIT 0x80
+
+#define MMU_NTLB_ENTRIES 64 /* for 7750 */
+#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
+
+#define MMU_ITLB_DATA_ARRAY 0xF3000000
+#define MMU_UTLB_DATA_ARRAY 0xF7000000
+
+#define MMU_UTLB_ENTRIES 64
+#define MMU_U_ENTRY_SHIFT 8
+#define MMU_UTLB_VALID 0x100
+#define MMU_ITLB_ENTRIES 4
+#define MMU_I_ENTRY_SHIFT 8
+#define MMU_ITLB_VALID 0x100
+
+#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
+
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
new file mode 100644
index 000000000000..e091e32a67b7
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/rtc.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_CPU_SH4_RTC_H
+#define __ASM_CPU_SH4_RTC_H
+
+/* SH-4 RTC */
+#define R64CNT 0xffc80000
+#define RSECCNT 0xffc80004
+#define RMINCNT 0xffc80008
+#define RHRCNT 0xffc8000c
+#define RWKCNT 0xffc80010
+#define RDAYCNT 0xffc80014
+#define RMONCNT 0xffc80018
+#define RYRCNT 0xffc8001c /* 16bit */
+#define RSECAR 0xffc80020
+#define RMINAR 0xffc80024
+#define RHRAR 0xffc80028
+#define RWKAR 0xffc8002c
+#define RDAYAR 0xffc80030
+#define RMONAR 0xffc80034
+#define RCR1 0xffc80038
+#define RCR2 0xffc8003c
+
+#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
+
+#endif /* __ASM_CPU_SH4_RTC_H */
+
diff --git a/include/asm-sh/cpu-sh4/shmparam.h b/include/asm-sh/cpu-sh4/shmparam.h
new file mode 100644
index 000000000000..a5a0aa9425fe
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/shmparam.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm-sh/cpu-sh4/shmparam.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_SHMPARAM_H
+#define __ASM_CPU_SH4_SHMPARAM_H
+
+/*
+ * SH-4 has D-cache alias issue
+ */
+#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */
+
+#endif /* __ASM_CPU_SH4_SHMPARAM_H */
+
diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h
new file mode 100644
index 000000000000..ab392f120e06
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sigcontext.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
+#define __ASM_CPU_SH4_SIGCONTEXT_H
+
+struct sigcontext {
+ unsigned long oldmask;
+
+ /* CPU registers */
+ unsigned long sc_regs[16];
+ unsigned long sc_pc;
+ unsigned long sc_pr;
+ unsigned long sc_sr;
+ unsigned long sc_gbr;
+ unsigned long sc_mach;
+ unsigned long sc_macl;
+
+ /* FPU registers */
+ unsigned long sc_fpregs[16];
+ unsigned long sc_xfpregs[16];
+ unsigned int sc_fpscr;
+ unsigned int sc_fpul;
+ unsigned int sc_ownedfp;
+};
+
+#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h
new file mode 100644
index 000000000000..366b09166d3b
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sq.h
@@ -0,0 +1,48 @@
+/*
+ * include/asm-sh/cpu-sh4/sq.h
+ *
+ * Copyright (C) 2001, 2002, 2003 Paul Mundt
+ * Copyright (C) 2001, 2002 M. R. Brown
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_SQ_H
+#define __ASM_CPU_SH4_SQ_H
+
+#include <asm/addrspace.h>
+
+/*
+ * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
+ * mapped to any physical address space. Since data is written (and aligned)
+ * to 32-byte boundaries, we need to be sure that all allocations are aligned.
+ */
+#define SQ_SIZE 32
+#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
+#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
+
+#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
+#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
+#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
+
+struct sq_mapping {
+ const char *name;
+
+ unsigned long sq_addr;
+ unsigned long addr;
+ unsigned int size;
+
+ struct list_head list;
+};
+
+/* arch/sh/kernel/cpu/sh4/sq.c */
+extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name);
+extern void sq_unmap(struct sq_mapping *map);
+
+extern void sq_clear(unsigned long addr, unsigned int len);
+extern void sq_flush(void *addr);
+extern void sq_flush_range(unsigned long start, unsigned int len);
+
+#endif /* __ASM_CPU_SH4_SQ_H */
+
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
new file mode 100644
index 000000000000..8a4af126c890
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -0,0 +1,51 @@
+/*
+ * include/asm-sh/cpu-sh4/timer.h
+ *
+ * Copyright (C) 2004 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_TIMER_H
+#define __ASM_CPU_SH4_TIMER_H
+
+/*
+ * ---------------------------------------------------------------------------
+ * TMU Common definitions for SH4 processors
+ * SH7750S/SH7750R
+ * SH7751/SH7751R
+ * SH7760
+ * ---------------------------------------------------------------------------
+ */
+
+#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
+#define TMU_TOCR 0xffd80000 /* Byte access */
+#endif
+#define TMU_TSTR 0xffd80004 /* Byte access */
+
+#define TMU0_TCOR 0xffd80008 /* Long access */
+#define TMU0_TCNT 0xffd8000c /* Long access */
+#define TMU0_TCR 0xffd80010 /* Word access */
+
+#define TMU1_TCOR 0xffd80014 /* Long access */
+#define TMU1_TCNT 0xffd80018 /* Long access */
+#define TMU1_TCR 0xffd8001c /* Word access */
+
+#define TMU2_TCOR 0xffd80020 /* Long access */
+#define TMU2_TCNT 0xffd80024 /* Long access */
+#define TMU2_TCR 0xffd80028 /* Word access */
+#define TMU2_TCPR 0xffd8002c /* Long access */
+
+#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
+#define TMU3_TCOR 0xfe100008 /* Long access */
+#define TMU3_TCNT 0xfe10000c /* Long access */
+#define TMU3_TCR 0xfe100010 /* Word access */
+
+#define TMU4_TCOR 0xfe100014 /* Long access */
+#define TMU4_TCNT 0xfe100018 /* Long access */
+#define TMU4_TCR 0xfe10001c /* Word access */
+#endif
+
+#endif /* __ASM_CPU_SH4_TIMER_H */
+
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
new file mode 100644
index 000000000000..3d0943167659
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/ubc.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-sh/cpu-sh4/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_UBC_H
+#define __ASM_CPU_SH4_UBC_H
+
+#define UBC_BARA 0xff200000
+#define UBC_BAMRA 0xff200004
+#define UBC_BBRA 0xff200008
+#define UBC_BASRA 0xff000014
+#define UBC_BARB 0xff20000c
+#define UBC_BAMRB 0xff200010
+#define UBC_BBRB 0xff200014
+#define UBC_BASRB 0xff000018
+#define UBC_BDRB 0xff200018
+#define UBC_BDMRB 0xff20001c
+#define UBC_BRCR 0xff200020
+
+#endif /* __ASM_CPU_SH4_UBC_H */
+
diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h
new file mode 100644
index 000000000000..259f6a0ce23d
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/watchdog.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/cpu-sh4/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_WATCHDOG_H
+#define __ASM_CPU_SH4_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT 0xffc00008
+#define WTCSR 0xffc0000c
+
+/* Bit definitions */
+#define WTCSR_TME 0x80
+#define WTCSR_WT 0x40
+#define WTCSR_RSTS 0x20
+#define WTCSR_WOVF 0x10
+#define WTCSR_IOVF 0x08
+
+#endif /* __ASM_CPU_SH4_WATCHDOG_H */
+