diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/pinctrl/s32v234-pinctrl.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/s32v234-pinctrl.h b/include/dt-bindings/pinctrl/s32v234-pinctrl.h index 5f050cb4b432..0c3ae517590f 100644 --- a/include/dt-bindings/pinctrl/s32v234-pinctrl.h +++ b/include/dt-bindings/pinctrl/s32v234-pinctrl.h @@ -292,6 +292,62 @@ #define S32V234_IMCR_Ethernet_TIMER1 983 #define S32V234_IMCR_Ethernet_TIMER2 984 +/* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the IMCR_IDX + * instead of MSCR_IDX, add 512 to it as the Reference Manual states. + */ + +/* UART configuration */ +#define S32V234_PAD_PA12__UART0_TXD S32V234_MSCR_PA12 PAD_CTL_UART_TX +#define S32V234_PAD_PA11__UART0_RXD_OUT S32V234_MSCR_PA11 PAD_CTL_UART_RX_MSCR +#define S32V234_PAD_PA11__UART0_RXD_IN S32V234_IMCR_UART0_RXD \ + PAD_CTL_UART_RX_IMCR + +#define S32V234_PAD_PA14__UART1_TXD S32V234_MSCR_PA14 PAD_CTL_UART_TX +#define S32V234_PAD_PA13__UART1_RXD_OUT S32V234_MSCR_PA13 PAD_CTL_UART_RX_MSCR +#define S32V234_PAD_PA13__UART1_RXD_IN S32V234_IMCR_UART1_RXD \ + PAD_CTL_UART_RX_IMCR + +/* uSDHC configuration */ +#define S32V234_PAD_PK6__USDHC_CLK_OUT S32V234_MSCR_PK6 PAD_CTL_USDHC_CLK +#define S32V234_PAD_PK6__USDHC_CLK_IN S32V234_IMCR_USDHC_CLK \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK7__USDHC_CMD_OUT S32V234_MSCR_PK7 PAD_CTL_USDHC_CMD +#define S32V234_PAD_PK7__USDHC_CMD_IN S32V234_IMCR_USDHC_CMD \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK8__USDHC_DAT0_OUT S32V234_MSCR_PK8 PAD_CTL_USDHC_DAT0_3 +#define S32V234_PAD_PK8__USDHC_DAT0_IN S32V234_IMCR_USDHC_DAT0 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK9__USDHC_DAT1_OUT S32V234_MSCR_PK9 PAD_CTL_USDHC_DAT0_3 +#define S32V234_PAD_PK9__USDHC_DAT1_IN S32V234_IMCR_USDHC_DAT1 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK10__USDHC_DAT2_OUT S32V234_MSCR_PK10 PAD_CTL_USDHC_DAT0_3 +#define S32V234_PAD_PK10__USDHC_DAT2_IN S32V234_IMCR_USDHC_DAT2 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK11__USDHC_DAT3_OUT S32V234_MSCR_PK11 PAD_CTL_USDHC_DAT0_3 +#define S32V234_PAD_PK11__USDHC_DAT3_IN S32V234_IMCR_USDHC_DAT3 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PK15__USDHC_DAT4_OUT S32V234_MSCR_PK15 PAD_CTL_USDHC_DAT4_7 +#define S32V234_PAD_PK15__USDHC_DAT4_IN S32V234_IMCR_USDHC_DAT4 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PL0__USDHC_DAT5_OUT S32V234_MSCR_PL0 PAD_CTL_USDHC_DAT4_7 +#define S32V234_PAD_PL0__USDHC_DAT5_IN S32V234_IMCR_USDHC_DAT5 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PL1__USDHC_DAT6_OUT S32V234_MSCR_PL1 PAD_CTL_USDHC_DAT4_7 +#define S32V234_PAD_PL1__USDHC_DAT6_IN S32V234_IMCR_USDHC_DAT6 \ + PAD_CTL_MUX_MODE_ALT3 + +#define S32V234_PAD_PL2__USDHC_DAT7_OUT S32V234_MSCR_PL2 PAD_CTL_USDHC_DAT4_7 +#define S32V234_PAD_PL2__USDHC_DAT7_IN S32V234_IMCR_USDHC_DAT7 \ + PAD_CTL_MUX_MODE_ALT3 + /* ENET configuration */ #define S32V234_PAD_PC13__MDC S32V234_MSCR_PC13 PAD_CTL_ENET_CFG2 |