diff options
Diffstat (limited to 'include/linux')
90 files changed, 5319 insertions, 609 deletions
diff --git a/include/linux/bio.h b/include/linux/bio.h index 97cb48f03dc7..87ce64dafb93 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -83,17 +83,6 @@ static inline bool bio_no_advance_iter(struct bio *bio) bio_op(bio) == REQ_OP_WRITE_SAME; } -static inline bool bio_is_rw(struct bio *bio) -{ - if (!bio_has_data(bio)) - return false; - - if (bio_no_advance_iter(bio)) - return false; - - return true; -} - static inline bool bio_mergeable(struct bio *bio) { if (bio->bi_opf & REQ_NOMERGE_FLAGS) diff --git a/include/linux/blk-cgroup.h b/include/linux/blk-cgroup.h index 3bf5d33800ab..ddaf28d0988f 100644 --- a/include/linux/blk-cgroup.h +++ b/include/linux/blk-cgroup.h @@ -581,15 +581,14 @@ static inline void blkg_rwstat_exit(struct blkg_rwstat *rwstat) /** * blkg_rwstat_add - add a value to a blkg_rwstat * @rwstat: target blkg_rwstat - * @op: REQ_OP - * @op_flags: rq_flag_bits + * @op: REQ_OP and flags * @val: value to add * * Add @val to @rwstat. The counters are chosen according to @rw. The * caller is responsible for synchronizing calls to this function. */ static inline void blkg_rwstat_add(struct blkg_rwstat *rwstat, - int op, int op_flags, uint64_t val) + unsigned int op, uint64_t val) { struct percpu_counter *cnt; @@ -600,7 +599,7 @@ static inline void blkg_rwstat_add(struct blkg_rwstat *rwstat, __percpu_counter_add(cnt, val, BLKG_STAT_CPU_BATCH); - if (op_flags & REQ_SYNC) + if (op & REQ_SYNC) cnt = &rwstat->cpu_cnt[BLKG_RWSTAT_SYNC]; else cnt = &rwstat->cpu_cnt[BLKG_RWSTAT_ASYNC]; @@ -705,9 +704,9 @@ static inline bool blkcg_bio_issue_check(struct request_queue *q, if (!throtl) { blkg = blkg ?: q->root_blkg; - blkg_rwstat_add(&blkg->stat_bytes, bio_op(bio), bio->bi_opf, + blkg_rwstat_add(&blkg->stat_bytes, bio->bi_opf, bio->bi_iter.bi_size); - blkg_rwstat_add(&blkg->stat_ios, bio_op(bio), bio->bi_opf, 1); + blkg_rwstat_add(&blkg->stat_ios, bio->bi_opf, 1); } rcu_read_unlock(); diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index cd395ecec99d..3fa62cabe8d2 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -88,24 +88,6 @@ struct bio { struct bio_vec bi_inline_vecs[0]; }; -#define BIO_OP_SHIFT (8 * FIELD_SIZEOF(struct bio, bi_opf) - REQ_OP_BITS) -#define bio_flags(bio) ((bio)->bi_opf & ((1 << BIO_OP_SHIFT) - 1)) -#define bio_op(bio) ((bio)->bi_opf >> BIO_OP_SHIFT) - -#define bio_set_op_attrs(bio, op, op_flags) do { \ - if (__builtin_constant_p(op)) \ - BUILD_BUG_ON((op) + 0U >= (1U << REQ_OP_BITS)); \ - else \ - WARN_ON_ONCE((op) + 0U >= (1U << REQ_OP_BITS)); \ - if (__builtin_constant_p(op_flags)) \ - BUILD_BUG_ON((op_flags) + 0U >= (1U << BIO_OP_SHIFT)); \ - else \ - WARN_ON_ONCE((op_flags) + 0U >= (1U << BIO_OP_SHIFT)); \ - (bio)->bi_opf = bio_flags(bio); \ - (bio)->bi_opf |= (((op) + 0U) << BIO_OP_SHIFT); \ - (bio)->bi_opf |= (op_flags); \ -} while (0) - #define BIO_RESET_BYTES offsetof(struct bio, bi_max_vecs) /* @@ -119,6 +101,8 @@ struct bio { #define BIO_QUIET 6 /* Make BIO Quiet */ #define BIO_CHAIN 7 /* chained bio, ->bi_remaining in effect */ #define BIO_REFFED 8 /* bio has elevated ->bi_cnt */ +#define BIO_THROTTLED 9 /* This bio has already been subjected to + * throttling rules. Don't do it again. */ /* * Flags starting here get preserved by bio_reset() - this includes @@ -145,50 +129,57 @@ struct bio { #endif /* CONFIG_BLOCK */ /* - * Request flags. For use in the cmd_flags field of struct request, and in - * bi_opf of struct bio. Note that some flags are only valid in either one. + * Operations and flags common to the bio and request structures. + * We use 8 bits for encoding the operation, and the remaining 24 for flags. + * + * The least significant bit of the operation number indicates the data + * transfer direction: + * + * - if the least significant bit is set transfers are TO the device + * - if the least significant bit is not set transfers are FROM the device + * + * If a operation does not transfer data the least significant bit has no + * meaning. */ -enum rq_flag_bits { - /* common flags */ - __REQ_FAILFAST_DEV, /* no driver retries of device errors */ +#define REQ_OP_BITS 8 +#define REQ_OP_MASK ((1 << REQ_OP_BITS) - 1) +#define REQ_FLAG_BITS 24 + +enum req_opf { + /* read sectors from the device */ + REQ_OP_READ = 0, + /* write sectors to the device */ + REQ_OP_WRITE = 1, + /* flush the volatile write cache */ + REQ_OP_FLUSH = 2, + /* discard sectors */ + REQ_OP_DISCARD = 3, + /* get zone information */ + REQ_OP_ZONE_REPORT = 4, + /* securely erase sectors */ + REQ_OP_SECURE_ERASE = 5, + /* seset a zone write pointer */ + REQ_OP_ZONE_RESET = 6, + /* write the same sector many times */ + REQ_OP_WRITE_SAME = 7, + + REQ_OP_LAST, +}; + +enum req_flag_bits { + __REQ_FAILFAST_DEV = /* no driver retries of device errors */ + REQ_OP_BITS, __REQ_FAILFAST_TRANSPORT, /* no driver retries of transport errors */ __REQ_FAILFAST_DRIVER, /* no driver retries of driver errors */ - __REQ_SYNC, /* request is sync (sync write or read) */ __REQ_META, /* metadata io request */ __REQ_PRIO, /* boost priority in cfq */ - + __REQ_NOMERGE, /* don't touch this for merging */ __REQ_NOIDLE, /* don't anticipate more IO after this one */ __REQ_INTEGRITY, /* I/O includes block integrity payload */ __REQ_FUA, /* forced unit access */ __REQ_PREFLUSH, /* request for cache flush */ - - /* bio only flags */ __REQ_RAHEAD, /* read ahead, can fail anytime */ - __REQ_THROTTLED, /* This bio has already been subjected to - * throttling rules. Don't do it again. */ - - /* request only flags */ - __REQ_SORTED, /* elevator knows about this request */ - __REQ_SOFTBARRIER, /* may not be passed by ioscheduler */ - __REQ_NOMERGE, /* don't touch this for merging */ - __REQ_STARTED, /* drive already may have started this one */ - __REQ_DONTPREP, /* don't call prep for this one */ - __REQ_QUEUED, /* uses queueing */ - __REQ_ELVPRIV, /* elevator private data attached */ - __REQ_FAILED, /* set if the request failed */ - __REQ_QUIET, /* don't worry about errors */ - __REQ_PREEMPT, /* set for "ide_preempt" requests and also - for requests for which the SCSI "quiesce" - state must be ignored. */ - __REQ_ALLOCED, /* request came from our alloc pool */ - __REQ_COPY_USER, /* contains copies of user pages */ - __REQ_FLUSH_SEQ, /* request for flush sequence */ - __REQ_IO_STAT, /* account I/O stat */ - __REQ_MIXED_MERGE, /* merge of different types, fail separately */ - __REQ_PM, /* runtime pm request */ - __REQ_HASHED, /* on IO scheduler merge hash */ - __REQ_MQ_INFLIGHT, /* track inflight for MQ */ __REQ_NR_BITS, /* stops here */ }; @@ -198,54 +189,37 @@ enum rq_flag_bits { #define REQ_SYNC (1ULL << __REQ_SYNC) #define REQ_META (1ULL << __REQ_META) #define REQ_PRIO (1ULL << __REQ_PRIO) +#define REQ_NOMERGE (1ULL << __REQ_NOMERGE) #define REQ_NOIDLE (1ULL << __REQ_NOIDLE) #define REQ_INTEGRITY (1ULL << __REQ_INTEGRITY) +#define REQ_FUA (1ULL << __REQ_FUA) +#define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH) +#define REQ_RAHEAD (1ULL << __REQ_RAHEAD) #define REQ_FAILFAST_MASK \ (REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER) -#define REQ_COMMON_MASK \ - (REQ_FAILFAST_MASK | REQ_SYNC | REQ_META | REQ_PRIO | REQ_NOIDLE | \ - REQ_PREFLUSH | REQ_FUA | REQ_INTEGRITY | REQ_NOMERGE) -#define REQ_CLONE_MASK REQ_COMMON_MASK -/* This mask is used for both bio and request merge checking */ #define REQ_NOMERGE_FLAGS \ - (REQ_NOMERGE | REQ_STARTED | REQ_SOFTBARRIER | REQ_PREFLUSH | REQ_FUA | REQ_FLUSH_SEQ) + (REQ_NOMERGE | REQ_PREFLUSH | REQ_FUA) -#define REQ_RAHEAD (1ULL << __REQ_RAHEAD) -#define REQ_THROTTLED (1ULL << __REQ_THROTTLED) +#define bio_op(bio) \ + ((bio)->bi_opf & REQ_OP_MASK) +#define req_op(req) \ + ((req)->cmd_flags & REQ_OP_MASK) -#define REQ_SORTED (1ULL << __REQ_SORTED) -#define REQ_SOFTBARRIER (1ULL << __REQ_SOFTBARRIER) -#define REQ_FUA (1ULL << __REQ_FUA) -#define REQ_NOMERGE (1ULL << __REQ_NOMERGE) -#define REQ_STARTED (1ULL << __REQ_STARTED) -#define REQ_DONTPREP (1ULL << __REQ_DONTPREP) -#define REQ_QUEUED (1ULL << __REQ_QUEUED) -#define REQ_ELVPRIV (1ULL << __REQ_ELVPRIV) -#define REQ_FAILED (1ULL << __REQ_FAILED) -#define REQ_QUIET (1ULL << __REQ_QUIET) -#define REQ_PREEMPT (1ULL << __REQ_PREEMPT) -#define REQ_ALLOCED (1ULL << __REQ_ALLOCED) -#define REQ_COPY_USER (1ULL << __REQ_COPY_USER) -#define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH) -#define REQ_FLUSH_SEQ (1ULL << __REQ_FLUSH_SEQ) -#define REQ_IO_STAT (1ULL << __REQ_IO_STAT) -#define REQ_MIXED_MERGE (1ULL << __REQ_MIXED_MERGE) -#define REQ_PM (1ULL << __REQ_PM) -#define REQ_HASHED (1ULL << __REQ_HASHED) -#define REQ_MQ_INFLIGHT (1ULL << __REQ_MQ_INFLIGHT) - -enum req_op { - REQ_OP_READ, - REQ_OP_WRITE, - REQ_OP_DISCARD, /* request to discard sectors */ - REQ_OP_SECURE_ERASE, /* request to securely erase sectors */ - REQ_OP_WRITE_SAME, /* write same block many times */ - REQ_OP_FLUSH, /* request for cache flush */ -}; +/* obsolete, don't use in new code */ +#define bio_set_op_attrs(bio, op, op_flags) \ + ((bio)->bi_opf |= (op | op_flags)) + +static inline bool op_is_write(unsigned int op) +{ + return (op & 1); +} -#define REQ_OP_BITS 3 +static inline bool op_is_sync(unsigned int op) +{ + return (op & REQ_OP_MASK) == REQ_OP_READ || (op & REQ_SYNC); +} typedef unsigned int blk_qc_t; #define BLK_QC_T_NONE -1U diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index bd738aafd432..6b5481d88923 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -77,6 +77,50 @@ enum rq_cmd_type_bits { REQ_TYPE_DRV_PRIV, /* driver defined types from here */ }; +/* + * request flags */ +typedef __u32 __bitwise req_flags_t; + +/* elevator knows about this request */ +#define RQF_SORTED ((__force req_flags_t)(1 << 0)) +/* drive already may have started this one */ +#define RQF_STARTED ((__force req_flags_t)(1 << 1)) +/* uses tagged queueing */ +#define RQF_QUEUED ((__force req_flags_t)(1 << 2)) +/* may not be passed by ioscheduler */ +#define RQF_SOFTBARRIER ((__force req_flags_t)(1 << 3)) +/* request for flush sequence */ +#define RQF_FLUSH_SEQ ((__force req_flags_t)(1 << 4)) +/* merge of different types, fail separately */ +#define RQF_MIXED_MERGE ((__force req_flags_t)(1 << 5)) +/* track inflight for MQ */ +#define RQF_MQ_INFLIGHT ((__force req_flags_t)(1 << 6)) +/* don't call prep for this one */ +#define RQF_DONTPREP ((__force req_flags_t)(1 << 7)) +/* set for "ide_preempt" requests and also for requests for which the SCSI + "quiesce" state must be ignored. */ +#define RQF_PREEMPT ((__force req_flags_t)(1 << 8)) +/* contains copies of user pages */ +#define RQF_COPY_USER ((__force req_flags_t)(1 << 9)) +/* vaguely specified driver internal error. Ignored by the block layer */ +#define RQF_FAILED ((__force req_flags_t)(1 << 10)) +/* don't warn about errors */ +#define RQF_QUIET ((__force req_flags_t)(1 << 11)) +/* elevator private data attached */ +#define RQF_ELVPRIV ((__force req_flags_t)(1 << 12)) +/* account I/O stat */ +#define RQF_IO_STAT ((__force req_flags_t)(1 << 13)) +/* request came from our alloc pool */ +#define RQF_ALLOCED ((__force req_flags_t)(1 << 14)) +/* runtime pm request */ +#define RQF_PM ((__force req_flags_t)(1 << 15)) +/* on IO scheduler merge hash */ +#define RQF_HASHED ((__force req_flags_t)(1 << 16)) + +/* flags that prevent us from merging requests: */ +#define RQF_NOMERGE_FLAGS \ + (RQF_STARTED | RQF_SOFTBARRIER | RQF_FLUSH_SEQ) + #define BLK_MAX_CDB 16 /* @@ -97,7 +141,8 @@ struct request { int cpu; unsigned cmd_type; - u64 cmd_flags; + unsigned int cmd_flags; /* op and common flags */ + req_flags_t rq_flags; unsigned long atomic_flags; /* the following two fields are internal, NEVER access directly */ @@ -198,20 +243,6 @@ struct request { struct request *next_rq; }; -#define REQ_OP_SHIFT (8 * sizeof(u64) - REQ_OP_BITS) -#define req_op(req) ((req)->cmd_flags >> REQ_OP_SHIFT) - -#define req_set_op(req, op) do { \ - WARN_ON(op >= (1 << REQ_OP_BITS)); \ - (req)->cmd_flags &= ((1ULL << REQ_OP_SHIFT) - 1); \ - (req)->cmd_flags |= ((u64) (op) << REQ_OP_SHIFT); \ -} while (0) - -#define req_set_op_attrs(req, op, flags) do { \ - req_set_op(req, op); \ - (req)->cmd_flags |= flags; \ -} while (0) - static inline unsigned short req_get_ioprio(struct request *req) { return req->ioprio; @@ -231,6 +262,8 @@ typedef void (softirq_done_fn)(struct request *); typedef int (dma_drain_needed_fn)(struct request *); typedef int (lld_busy_fn) (struct request_queue *q); typedef int (bsg_job_fn) (struct bsg_job *); +typedef int (init_rq_fn)(struct request_queue *, struct request *, gfp_t); +typedef void (exit_rq_fn)(struct request_queue *, struct request *); enum blk_eh_timer_return { BLK_EH_NOT_HANDLED, @@ -318,6 +351,8 @@ struct request_queue { rq_timed_out_fn *rq_timed_out_fn; dma_drain_needed_fn *dma_drain_needed; lld_busy_fn *lld_busy_fn; + init_rq_fn *init_rq_fn; + exit_rq_fn *exit_rq_fn; struct blk_mq_ops *mq_ops; @@ -476,6 +511,9 @@ struct request_queue { struct bio_set *bio_split; bool mq_sysfs_init_done; + + size_t cmd_size; + void *rq_alloc_data; }; #define QUEUE_FLAG_QUEUED 1 /* uses generic tag queueing */ @@ -601,7 +639,7 @@ static inline void queue_flag_clear(unsigned int flag, struct request_queue *q) REQ_FAILFAST_DRIVER)) #define blk_account_rq(rq) \ - (((rq)->cmd_flags & REQ_STARTED) && \ + (((rq)->rq_flags & RQF_STARTED) && \ ((rq)->cmd_type == REQ_TYPE_FS)) #define blk_rq_cpu_valid(rq) ((rq)->cpu != -1) @@ -627,17 +665,9 @@ static inline unsigned int blk_queue_cluster(struct request_queue *q) return q->limits.cluster; } -/* - * We regard a request as sync, if either a read or a sync write - */ -static inline bool rw_is_sync(int op, unsigned int rw_flags) -{ - return op == REQ_OP_READ || (rw_flags & REQ_SYNC); -} - static inline bool rq_is_sync(struct request *rq) { - return rw_is_sync(req_op(rq), rq->cmd_flags); + return op_is_sync(rq->cmd_flags); } static inline bool blk_rl_full(struct request_list *rl, bool sync) @@ -671,6 +701,8 @@ static inline bool rq_mergeable(struct request *rq) if (rq->cmd_flags & REQ_NOMERGE_FLAGS) return false; + if (rq->rq_flags & RQF_NOMERGE_FLAGS) + return false; return true; } @@ -978,8 +1010,7 @@ extern void blk_unprep_request(struct request *); extern struct request_queue *blk_init_queue_node(request_fn_proc *rfn, spinlock_t *lock, int node_id); extern struct request_queue *blk_init_queue(request_fn_proc *, spinlock_t *); -extern struct request_queue *blk_init_allocated_queue(struct request_queue *, - request_fn_proc *, spinlock_t *); +extern int blk_init_allocated_queue(struct request_queue *); extern void blk_cleanup_queue(struct request_queue *); extern void blk_queue_make_request(struct request_queue *, make_request_fn *); extern void blk_queue_bounce_limit(struct request_queue *, u64); diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h index cceb72f9e29f..e417f080219a 100644 --- a/include/linux/blktrace_api.h +++ b/include/linux/blktrace_api.h @@ -118,7 +118,7 @@ static inline int blk_cmd_buf_len(struct request *rq) } extern void blk_dump_cmd(char *buf, struct request *rq); -extern void blk_fill_rwbs(char *rwbs, int op, u32 rw, int bytes); +extern void blk_fill_rwbs(char *rwbs, unsigned int op, int bytes); #endif /* CONFIG_EVENT_TRACING && CONFIG_BLOCK */ diff --git a/include/linux/busfreq-imx.h b/include/linux/busfreq-imx.h new file mode 100644 index 000000000000..17b8991d69bd --- /dev/null +++ b/include/linux/busfreq-imx.h @@ -0,0 +1,77 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BUSFREQ_H__ +#define __ASM_ARCH_MXC_BUSFREQ_H__ + +#include <linux/notifier.h> +#include <linux/regulator/consumer.h> + +/* + * This enumerates busfreq low power mode entry and exit. + */ +enum busfreq_event { + LOW_BUSFREQ_ENTER, + LOW_BUSFREQ_EXIT, +}; + +/* + * This enumerates the system bus and ddr frequencies in various modes. + * BUS_FREQ_HIGH - DDR @ 528MHz, AHB @ 132MHz. + * BUS_FREQ_MED - DDR @ 400MHz, AHB @ 132MHz + * BUS_FREQ_AUDIO - DDR @ 50MHz/100MHz, AHB @ 24MHz. + * BUS_FREQ_LOW - DDR @ 24MHz, AHB @ 24MHz. + * BUS_FREQ_ULTRA_LOW - DDR @ 1MHz, AHB - 3MHz. + * + * Drivers need to request/release the bus/ddr frequencies based on + * their performance requirements. Drivers cannot request/release + * BUS_FREQ_ULTRA_LOW mode as this mode is automatically entered from + * either BUS_FREQ_AUDIO or BUS_FREQ_LOW + * modes. + */ +enum bus_freq_mode { + BUS_FREQ_HIGH, + BUS_FREQ_MED, + BUS_FREQ_AUDIO, + BUS_FREQ_LOW, + BUS_FREQ_ULTRA_LOW, +}; + +#if defined(CONFIG_CPU_FREQ) && !defined(CONFIG_ARM64) +extern struct regulator *arm_reg; +extern struct regulator *soc_reg; +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int register_busfreq_notifier(struct notifier_block *nb); +int unregister_busfreq_notifier(struct notifier_block *nb); +int get_bus_freq_mode(void); +#elif defined(CONFIG_ARCH_FSL_IMX8MQ) +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int get_bus_freq_mode(void); +#else +static inline void request_bus_freq(enum bus_freq_mode mode) +{ +} +static inline void release_bus_freq(enum bus_freq_mode mode) +{ +} +static inline int register_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int get_bus_freq_mode(void) +{ + return BUS_FREQ_HIGH; +} +#endif +#endif diff --git a/include/linux/can/platform/flexcan.h b/include/linux/can/platform/flexcan.h new file mode 100644 index 000000000000..fdfe76f16ea7 --- /dev/null +++ b/include/linux/can/platform/flexcan.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This file is released under the GPLv2 + * + */ + +#ifndef __CAN_PLATFORM_FLEXCAN_H +#define __CAN_PLATFORM_FLEXCAN_H + +/** + * struct flexcan_platform_data - flex CAN controller platform data + * @transceiver_enable: - called to power on/off the transceiver + * + */ +struct flexcan_platform_data { + void (*transceiver_switch)(int enable); +}; + +#endif /* __CAN_PLATFORM_FLEXCAN_H */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index a428aec36ace..6dc1aeda6ca5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -35,6 +35,7 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) +#define CLK_SET_PARENT_NOCACHE BIT(13) /* do not use the cached clk parent */ struct clk; struct clk_hw; @@ -357,6 +358,7 @@ struct clk_div_table { * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements @@ -385,6 +387,12 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_ZERO_GATE - For dividers when the value read from the register + * is zero, it means the divisor is gated. For this case, the cached_val + * will be used to store the intermediate div for the normal rate + * operation, like set_rate/get_rate/recalc_rate. When the divider is + * ungated, the driver will actually program the hardware to have the + * requested divider value. */ struct clk_divider { struct clk_hw hw; @@ -393,6 +401,7 @@ struct clk_divider { u8 width; u8 flags; const struct clk_div_table *table; + u32 cached_val; spinlock_t *lock; }; @@ -405,6 +414,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_ZERO_GATE BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; @@ -553,6 +563,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -569,6 +585,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, diff --git a/include/linux/cpu.h b/include/linux/cpu.h index ae5ac89324df..fdf5be472eff 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -276,4 +276,11 @@ static inline void cpu_smt_check_topology_early(void) { } static inline void cpu_smt_check_topology(void) { } #endif +#define IDLE_START 1 +#define IDLE_END 2 + +void idle_notifier_register(struct notifier_block *n); +void idle_notifier_unregister(struct notifier_block *n); +void idle_notifier_call_chain(unsigned long val); + #endif /* _LINUX_CPU_H_ */ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 32dc0cbd51ca..7643354f0b86 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -539,6 +539,18 @@ struct gov_attr_set { int usage_count; }; +#define gov_attr_ro(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0444, show_##_name, NULL) + +#define gov_attr_wo(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0200, NULL, store_##_name) + +#define gov_attr_rw(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + /* sysfs ops for cpufreq governors */ extern const struct sysfs_ops governor_sysfs_ops; diff --git a/include/linux/device.h b/include/linux/device.h index 8d732965fab7..12cfe907a8ff 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -710,6 +710,81 @@ struct device_dma_parameters { }; /** + * enum device_link_state - Device link states. + * @DL_STATE_NONE: The presence of the drivers is not being tracked. + * @DL_STATE_DORMANT: None of the supplier/consumer drivers is present. + * @DL_STATE_AVAILABLE: The supplier driver is present, but the consumer is not. + * @DL_STATE_CONSUMER_PROBE: The consumer is probing (supplier driver present). + * @DL_STATE_ACTIVE: Both the supplier and consumer drivers are present. + * @DL_STATE_SUPPLIER_UNBIND: The supplier driver is unbinding. + */ +enum device_link_state { + DL_STATE_NONE = -1, + DL_STATE_DORMANT = 0, + DL_STATE_AVAILABLE, + DL_STATE_CONSUMER_PROBE, + DL_STATE_ACTIVE, + DL_STATE_SUPPLIER_UNBIND, +}; + +/* + * Device link flags. + * + * STATELESS: The core won't track the presence of supplier/consumer drivers. + * AUTOREMOVE: Remove this link automatically on consumer driver unbind. + */ +#define DL_FLAG_STATELESS BIT(0) +#define DL_FLAG_AUTOREMOVE BIT(1) + +/** + * struct device_link - Device link representation. + * @supplier: The device on the supplier end of the link. + * @s_node: Hook to the supplier device's list of links to consumers. + * @consumer: The device on the consumer end of the link. + * @c_node: Hook to the consumer device's list of links to suppliers. + * @status: The state of the link (with respect to the presence of drivers). + * @flags: Link flags. + * @rcu_head: An RCU head to use for deferred execution of SRCU callbacks. + */ +struct device_link { + struct device *supplier; + struct list_head s_node; + struct device *consumer; + struct list_head c_node; + enum device_link_state status; + u32 flags; +#ifdef CONFIG_SRCU + struct rcu_head rcu_head; +#endif +}; + +/** + * enum dl_dev_state - Device driver presence tracking information. + * @DL_DEV_NO_DRIVER: There is no driver attached to the device. + * @DL_DEV_PROBING: A driver is probing. + * @DL_DEV_DRIVER_BOUND: The driver has been bound to the device. + * @DL_DEV_UNBINDING: The driver is unbinding from the device. + */ +enum dl_dev_state { + DL_DEV_NO_DRIVER = 0, + DL_DEV_PROBING, + DL_DEV_DRIVER_BOUND, + DL_DEV_UNBINDING, +}; + +/** + * struct dev_links_info - Device data related to device links. + * @suppliers: List of links to supplier devices. + * @consumers: List of links to consumer devices. + * @status: Driver status information. + */ +struct dev_links_info { + struct list_head suppliers; + struct list_head consumers; + enum dl_dev_state status; +}; + +/** * struct device - The basic device structure * @parent: The device's "parent" device, the device to which it is attached. * In most cases, a parent device is some sort of bus or host @@ -801,6 +876,7 @@ struct device { core doesn't touch it */ void *driver_data; /* Driver data, set and get with dev_set/get_drvdata */ + struct dev_links_info links; struct dev_pm_info power; struct dev_pm_domain *pm_domain; @@ -1118,6 +1194,10 @@ extern void device_shutdown(void); /* debugging and troubleshooting/diagnostic helpers. */ extern const char *dev_driver_string(const struct device *dev); +/* Device links interface. */ +struct device_link *device_link_add(struct device *consumer, + struct device *supplier, u32 flags); +void device_link_del(struct device_link *link); #ifdef CONFIG_PRINTK diff --git a/include/linux/device_cooling.h b/include/linux/device_cooling.h new file mode 100644 index 000000000000..18d9e3b90ed9 --- /dev/null +++ b/include/linux/device_cooling.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DEVICE_THERMAL_H__ +#define __DEVICE_THERMAL_H__ + +#include <linux/thermal.h> + +#ifdef CONFIG_DEVICE_THERMAL +int register_devfreq_cooling_notifier(struct notifier_block *nb); +int unregister_devfreq_cooling_notifier(struct notifier_block *nb); +struct thermal_cooling_device *devfreq_cooling_register(void); +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev); +#else +static inline +int register_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +int unregister_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +struct thermal_cooling_device *devfreq_cooling_register(void) +{ + return NULL; +} + +static inline +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev) +{ + return; +} +#endif +#endif /* __DEVICE_THERMAL_H__ */ diff --git a/include/linux/dm-io.h b/include/linux/dm-io.h index b91b023deffb..a52c6580cc9a 100644 --- a/include/linux/dm-io.h +++ b/include/linux/dm-io.h @@ -58,7 +58,7 @@ struct dm_io_notify { struct dm_io_client; struct dm_io_request { int bi_op; /* REQ_OP */ - int bi_op_flags; /* rq_flag_bits */ + int bi_op_flags; /* req_flag_bits */ struct dm_io_memory mem; /* Memory to use for io */ struct dm_io_notify notify; /* Synchronous if notify.fn is NULL */ struct dm_io_client *client; /* Client memory handler */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index cc535a478bae..eaf8e1dfc582 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -336,6 +336,8 @@ enum dma_slave_buswidth { * may or may not be applicable on memory sources. * @dst_maxburst: same as src_maxburst but for destination target * mutatis mutandis. + * @src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset; + * @dst_fifo_num: same as src_fifo_num * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill * with 'true' if peripheral should be flow controller. Direction will be * selected at Runtime. @@ -363,6 +365,8 @@ struct dma_slave_config { enum dma_slave_buswidth dst_addr_width; u32 src_maxburst; u32 dst_maxburst; + u32 src_fifo_num; + u32 dst_fifo_num; bool device_fc; unsigned int slave_id; }; diff --git a/include/linux/elevator.h b/include/linux/elevator.h index eaa58c0f894b..6af1654e319d 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -30,7 +30,7 @@ typedef int (elevator_dispatch_fn) (struct request_queue *, int); typedef void (elevator_add_req_fn) (struct request_queue *, struct request *); typedef struct request *(elevator_request_list_fn) (struct request_queue *, struct request *); typedef void (elevator_completed_req_fn) (struct request_queue *, struct request *); -typedef int (elevator_may_queue_fn) (struct request_queue *, int, int); +typedef int (elevator_may_queue_fn) (struct request_queue *, unsigned int); typedef void (elevator_init_icq_fn) (struct io_cq *); typedef void (elevator_exit_icq_fn) (struct io_cq *); @@ -139,7 +139,7 @@ extern struct request *elv_former_request(struct request_queue *, struct request extern struct request *elv_latter_request(struct request_queue *, struct request *); extern int elv_register_queue(struct request_queue *q); extern void elv_unregister_queue(struct request_queue *q); -extern int elv_may_queue(struct request_queue *, int, int); +extern int elv_may_queue(struct request_queue *, unsigned int); extern void elv_completed_request(struct request_queue *, struct request *); extern int elv_set_request(struct request_queue *q, struct request *rq, struct bio *bio, gfp_t gfp_mask); diff --git a/include/linux/fs.h b/include/linux/fs.h index bcad2b963296..6527e4e5729b 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2508,11 +2508,6 @@ extern void make_bad_inode(struct inode *); extern bool is_bad_inode(struct inode *); #ifdef CONFIG_BLOCK -static inline bool op_is_write(unsigned int op) -{ - return op == REQ_OP_READ ? false : true; -} - /* * return data direction, READ or WRITE */ diff --git a/include/linux/hantrodec.h b/include/linux/hantrodec.h new file mode 100755 index 000000000000..f423ea82a04e --- /dev/null +++ b/include/linux/hantrodec.h @@ -0,0 +1,29 @@ +/***************************************************************************** +* +* The GPL License (GPL) +* +* Copyright (c) 2015-2017, VeriSilicon Inc. +* Copyright (c) 2011-2014, Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software Foundation, +* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +* +*****************************************************************************/ + +#ifndef _HANTRODEC_H_ +#define _HANTRODEC_H_ + +#include <uapi/linux/hantrodec.h> + +#endif /* !_HANTRODEC_H_ */ diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index e9744202fa29..e367de96076b 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -32,9 +32,11 @@ enum hdmi_infoframe_type { HDMI_INFOFRAME_TYPE_AVI = 0x82, HDMI_INFOFRAME_TYPE_SPD = 0x83, HDMI_INFOFRAME_TYPE_AUDIO = 0x84, + HDMI_INFOFRAME_TYPE_DRM = 0x87, }; #define HDMI_IEEE_OUI 0x000c03 +#define HDMI_FORUM_IEEE_OUI 0xc45dd8 #define HDMI_INFOFRAME_HEADER_SIZE 4 #define HDMI_AVI_INFOFRAME_SIZE 13 #define HDMI_SPD_INFOFRAME_SIZE 25 @@ -78,6 +80,8 @@ enum hdmi_picture_aspect { HDMI_PICTURE_ASPECT_NONE, HDMI_PICTURE_ASPECT_4_3, HDMI_PICTURE_ASPECT_16_9, + HDMI_PICTURE_ASPECT_64_27, + HDMI_PICTURE_ASPECT_256_135, HDMI_PICTURE_ASPECT_RESERVED, }; @@ -157,10 +161,28 @@ struct hdmi_avi_infoframe { unsigned short right_bar; }; +struct hdmi_drm_infoframe { + enum hdmi_infoframe_type type; + unsigned char version; + unsigned char length; + uint8_t eotf; + uint8_t metadata_type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; +}; + int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame); ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, size_t size); +int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame); + enum hdmi_spd_sdi { HDMI_SPD_SDI_UNKNOWN, HDMI_SPD_SDI_DSTB, @@ -325,6 +347,7 @@ union hdmi_infoframe { struct hdmi_spd_infoframe spd; union hdmi_vendor_any_infoframe vendor; struct hdmi_audio_infoframe audio; + struct hdmi_drm_infoframe drm; }; ssize_t diff --git a/include/linux/hx280enc.h b/include/linux/hx280enc.h new file mode 100755 index 000000000000..186a00e3446f --- /dev/null +++ b/include/linux/hx280enc.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * Encoder device driver (kernel module header) + * + * Copyright (C) 2012 Google Finland Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * +-------------------------------------------------------------------------------- +-- +-- Abstract : 6280/7280/8270/8290/H1 Encoder device driver (kernel module) +-- +*****************************************************************************/ + +#ifndef _HX280ENC_H_ +#define _HX280ENC_H_ + +#include <uapi/linux/hx280enc.h> + +#endif /* !_HX280ENC_H_ */ diff --git a/include/linux/imx_gpc.h b/include/linux/imx_gpc.h new file mode 100644 index 000000000000..46a1f08472bb --- /dev/null +++ b/include/linux/imx_gpc.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_gpc.h + * + * @brief Global header file for imx GPC + * + * @ingroup GPC + */ +#ifndef __LINUX_IMX_GPC_H__ +#define __LINUX_IMX_GPC_H__ + +#ifdef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on); +#else +static int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) +{ + return 0; +} +#endif + +#endif /* __LINUX_IMX_GPC_H__ */ diff --git a/include/linux/imx_rpmsg.h b/include/linux/imx_rpmsg.h new file mode 100644 index 000000000000..cabb6d6e03ce --- /dev/null +++ b/include/linux/imx_rpmsg.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_rpmsg.h + * + * @brief Global header file for imx RPMSG + * + * @ingroup RPMSG + */ +#ifndef __LINUX_IMX_RPMSG_H__ +#define __LINUX_IMX_RPMSG_H__ + +/* Category define */ +#define IMX_RMPSG_LIFECYCLE 1 +#define IMX_RPMSG_PMIC 2 +#define IMX_RPMSG_AUDIO 3 +#define IMX_RPMSG_KEY 4 +#define IMX_RPMSG_GPIO 5 +#define IMX_RPMSG_RTC 6 +#define IMX_RPMSG_SENSOR 7 +/* rpmsg version */ +#define IMX_RMPSG_MAJOR 1 +#define IMX_RMPSG_MINOR 0 + +struct imx_rpmsg_head { + u8 cate; + u8 major; + u8 minor; + u8 type; + u8 cmd; + u8 reserved[5]; +} __attribute__ ((packed)); + +#endif /* __LINUX_IMX_RPMSG_H__ */ diff --git a/include/linux/imx_sema4.h b/include/linux/imx_sema4.h new file mode 100644 index 000000000000..19850ae7742b --- /dev/null +++ b/include/linux/imx_sema4.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX_SEMA4_H__ +#define __LINUX_IMX_SEMA4_H__ + +#define SEMA4_NUM_DEVICES 1 +#define SEMA4_NUM_GATES 16 + +#define SEMA4_UNLOCK 0x00 +#define SEMA4_A9_LOCK 0x01 +#define SEMA4_GATE_MASK 0x03 + +#define CORE_MUTEX_VALID (('c'<<24)|('m'<<24)|('t'<<24)|'x') + +/* + * The enumerates + */ +enum { + /* sema4 registers offset */ + SEMA4_CP0INE = 0x40, + SEMA4_CP1INE = 0x48, + SEMA4_CP0NTF = 0x80, + SEMA4_CP1NTF = 0x88, +}; + +static const unsigned int idx_sema4[SEMA4_NUM_GATES] = { + 1 << 7, 1 << 6, 1 << 5, 1 << 4, + 1 << 3, 1 << 2, 1 << 1, 1 << 0, + 1 << 15, 1 << 14, 1 << 13, 1 << 12, + 1 << 11, 1 << 10, 1 << 9, 1 << 8, +}; + +struct imx_sema4_mutex { + u32 valid; + u32 gate_num; + unsigned char gate_val; + wait_queue_head_t wait_q; +}; + +struct imx_sema4_mutex_device { + struct device *dev; + u16 cpntf_val; + u16 cpine_val; + void __iomem *ioaddr; /* Mapped address */ + spinlock_t lock; /* Mutex */ + int irq; + + u16 alloced; + struct imx_sema4_mutex *mutex_ptr[SEMA4_NUM_GATES]; +}; + +struct imx_sema4_mutex * + imx_sema4_mutex_create(u32 dev_num, u32 mutex_num); +#ifdef CONFIG_IMX_SEMA4 +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr); +#else +static inline int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +#endif +#endif /* __LINUX_IMX_SEMA4_H__ */ diff --git a/include/linux/ipu-v3-pre.h b/include/linux/ipu-v3-pre.h new file mode 100644 index 000000000000..f5a26e5eadbf --- /dev/null +++ b/include/linux/ipu-v3-pre.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRE_H_ +#define __LINUX_IPU_V3_PRE_H_ + +#define IPU_PRE_MAX_WIDTH 1920 +#define IPU_PRE_MAX_BPP 4 +#define IPU_PRE_SMALL_LINE 9 /* to workaround errata ERR009624*/ + +struct ipu_rect { + int left; + int top; + int width; + int height; +}; + +struct ipu_pre_context { + bool repeat; + bool vflip; + bool handshake_en; + bool hsk_abort_en; + unsigned int hsk_line_num; + bool sdw_update; + unsigned int block_size; + unsigned int interlaced; + unsigned int prefetch_mode; + + unsigned long cur_buf; + unsigned long next_buf; + + unsigned int tile_fmt; + + unsigned int read_burst; + unsigned int prefetch_input_bpp; + unsigned int prefetch_input_pixel_fmt; + unsigned int prefetch_shift_offset; + unsigned int prefetch_shift_width; + bool shift_bypass; + bool field_inverse; + bool tpr_coor_offset_en; + /* the output of prefetch is + * also the input of store + */ + struct ipu_rect prefetch_output_size; + unsigned int prefetch_input_active_width; + unsigned int prefetch_input_width; + unsigned int prefetch_input_height; + unsigned int store_pitch; + int interlace_offset; + + bool store_en; + unsigned int write_burst; + unsigned int store_output_bpp; + + unsigned int sec_buf_off; + unsigned int trd_buf_off; + + /* return for IPU fb caller */ + unsigned long store_addr; +}; + +/* + * In order to workaround the PRE SoC bug recorded by errata ERR009624, + * the software cannot write the PRE_CTRL register when the PRE writes + * the PRE_CTRL register automatically to set the ENABLE bit(bit0) to 1 + * in the PRE repeat mode. + * The software mechanism to set the PRE_CTRL register is different for + * PRE Y resolution higher than 9 lines and lower or equal to 9 lines. + * Use this helper to check the Y resolution. + */ +static inline bool ipu_pre_yres_is_small(unsigned int yres) +{ + return yres <= IPU_PRE_SMALL_LINE; +} + +#ifdef CONFIG_MXC_IPU_V3_PRE +int ipu_pre_alloc(int ipu_id, ipu_channel_t ipu_ch); +void ipu_pre_free(unsigned int *id); +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size); +void ipu_pre_free_double_buffer(unsigned int id); +int ipu_pre_config(int id, struct ipu_pre_context *config); +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config); +int ipu_pre_enable(int id); +void ipu_pre_disable(int id); +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off); +int ipu_pre_sdw_update(int id); +#else +int ipu_pre_alloc(int ipu_id, ipu_channel_t channel) +{ + return -ENODEV; +} + +void ipu_pre_free(unsigned int *id) +{ +} + +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size) +{ + return -ENODEV; +} + +void ipu_pre_free_double_buffer(unsigned int id) +{ +} + +int ipu_pre_config(int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_enable(int id) +{ + return -ENODEV; +} + +void ipu_pre_disable(int id) +{ + return; +} + +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off) +{ + return -ENODEV; +} +int ipu_pre_sdw_update(int id) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRE_H_ */ diff --git a/include/linux/ipu-v3-prg.h b/include/linux/ipu-v3-prg.h new file mode 100644 index 000000000000..2ab803a6699f --- /dev/null +++ b/include/linux/ipu-v3-prg.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRG_H_ +#define __LINUX_IPU_V3_PRG_H_ + +#include <linux/ipu-v3.h> + +#define PRG_SO_INTERLACE 1 +#define PRG_SO_PROGRESSIVE 0 +#define PRG_BLOCK_MODE 1 +#define PRG_SCAN_MODE 0 + +struct ipu_prg_config { + unsigned int id; + unsigned int pre_num; + ipu_channel_t ipu_ch; + unsigned int stride; + unsigned int height; + unsigned int ipu_height; + unsigned int crop_line; + unsigned int so; + unsigned int ilo; + unsigned int block_mode; + bool vflip; + u32 baddr; + u32 offset; +}; + +#ifdef CONFIG_MXC_IPU_V3_PRG +int ipu_prg_config(struct ipu_prg_config *config); +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num); +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height); +#else +int ipu_prg_config(struct ipu_prg_config *config) +{ + return -ENODEV; +} + +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num) +{ + return -ENODEV; +} + +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRG_H_ */ diff --git a/include/linux/ipu-v3.h b/include/linux/ipu-v3.h new file mode 100644 index 000000000000..ae09614a2257 --- /dev/null +++ b/include/linux/ipu-v3.h @@ -0,0 +1,770 @@ +/* + * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __LINUX_IPU_V3_H_ +#define __LINUX_IPU_V3_H_ + +#include <linux/ipu.h> + +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/ + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + /* for vdi mem->vdi->mem */ + MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5), + + /* fake channel for vdoa to link with IPU */ + MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/* + * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished. + */ +#define IPU_IRQF_NONE 0x00000000 +#define IPU_IRQF_ONESHOT 0x00000001 + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDIC_OUT_EOF = 5, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_BG_SYNC_NFACK = 64 + 23, + IPU_IRQ_FG_SYNC_NFACK = 64 + 27, + IPU_IRQ_DC_SYNC_NFACK = 64 + 28, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4 = 0, + IPU_CSI_DATA_WIDTH_8 = 1, + IPU_CSI_DATA_WIDTH_10 = 3, + IPU_CSI_DATA_WIDTH_16 = 9, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +struct ipu_soc; +/* Common IPU API */ +struct ipu_soc *ipu_get_soc(int id); +int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); +void ipu_disable_hsp_clk(struct ipu_soc *ipu); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + dma_addr_t phyaddr_2, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_get_channel_offset(uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset, + uint32_t *u_offset, uint32_t *v_offset); + +int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); + +int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); +uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel); + +int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); +int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); +int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); +bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); +void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); +int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t band_height); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); + +/* SDC API */ +int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); + +int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_reset_disp_panel(struct ipu_soc *ipu); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); + +int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, + bool flag, bool wait) +{ + return ipu_csi_enable_mclk(ipu, csi, flag, wait); +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); + +uint32_t bytes_per_pixel(uint32_t fmt); + +bool ipu_ch_param_bad_alpha_pos(uint32_t fmt); +int ipu_ch_param_get_axi_id(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +ipu_color_space_t format_to_colorspace(uint32_t fmt); +bool ipu_pixel_format_is_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_split_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_pre_yuv(uint32_t fmt); +bool ipu_pixel_format_is_multiplanar_yuv(uint32_t fmt); + +struct ipuv3_fb_platform_data { + char disp_dev[32]; + u32 interface_pix_fmt; + char *mode_str; + int default_bpp; + bool int_clk; + + /* reserved mem */ + resource_size_t res_base[2]; + resource_size_t res_size[2]; + + /* + * Late init to avoid display channel being + * re-initialized as we've probably setup the + * channel in bootloader. + */ + bool late_init; + + /* Enable prefetch engine or not? */ + bool prefetch; + + /* Enable the PRE resolve engine or not? */ + bool resolve; +}; + +#endif /* __LINUX_IPU_V3_H_ */ diff --git a/include/linux/ipu.h b/include/linux/ipu.h new file mode 100644 index 000000000000..1090ac65f24b --- /dev/null +++ b/include/linux/ipu.h @@ -0,0 +1,38 @@ +/* + * Copyright 2005-2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file linux/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __LINUX_IPU_H__ +#define __LINUX_IPU_H__ + +#include <linux/interrupt.h> +#include <uapi/linux/ipu.h> + +unsigned int fmt_to_bpp(unsigned int pixelformat); +cs_t colorspaceofpixel(int fmt); +int need_csc(int ifmt, int ofmt); + +int ipu_queue_task(struct ipu_task *task); +int ipu_check_task(struct ipu_task *task); + +#endif diff --git a/include/linux/isl29023.h b/include/linux/isl29023.h new file mode 100644 index 000000000000..5c84566b7b21 --- /dev/null +++ b/include/linux/isl29023.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ISL29023_H__ +#define __ISL29023_H__ + +#include <linux/types.h> + +#define ISL29023_PD_MODE 0x0 +#define ISL29023_ALS_ONCE_MODE 0x1 +#define ISL29023_IR_ONCE_MODE 0x2 +#define ISL29023_ALS_CONT_MODE 0x5 +#define ISL29023_IR_CONT_MODE 0x6 + +#define ISL29023_INT_PERSISTS_1 0x0 +#define ISL29023_INT_PERSISTS_4 0x1 +#define ISL29023_INT_PERSISTS_8 0x2 +#define ISL29023_INT_PERSISTS_16 0x3 + +#define ISL29023_RES_16 0x0 +#define ISL29023_RES_12 0x1 +#define ISL29023_RES_8 0x2 +#define ISL29023_RES_4 0x3 + +#define ISL29023_RANGE_1K 0x0 +#define ISL29023_RANGE_4K 0x1 +#define ISL29023_RANGE_16K 0x2 +#define ISL29023_RANGE_64K 0x3 + +#endif diff --git a/include/linux/mfd/bd71837.h b/include/linux/mfd/bd71837.h new file mode 100644 index 000000000000..3cd51f314b20 --- /dev/null +++ b/include/linux/mfd/bd71837.h @@ -0,0 +1,413 @@ +/** + * @file bd71837.h ROHM BD71837MWV header file + * + * Copyright 2017 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * @author cpham2403@gmail.com + */ + +#ifndef __LINUX_MFD_BD71837_H +#define __LINUX_MFD_BD71837_H + +#include <linux/regmap.h> + +enum { + BD71837_BUCK1 = 0, + BD71837_BUCK2, + BD71837_BUCK3, + BD71837_BUCK4, + BD71837_BUCK5, + BD71837_BUCK6, + BD71837_BUCK7, + BD71837_BUCK8, + // General Purpose + BD71837_LDO1, + BD71837_LDO2, + BD71837_LDO3, + BD71837_LDO4, + BD71837_LDO5, + BD71837_LDO6, + BD71837_LDO7, + BD71837_REGULATOR_CNT, +}; + +#define BD71837_SUPPLY_STATE_ENABLED 0x1 + +#define BD71837_BUCK1_VOLTAGE_NUM 0x40 +#define BD71837_BUCK2_VOLTAGE_NUM 0x40 +#define BD71837_BUCK3_VOLTAGE_NUM 0x40 +#define BD71837_BUCK4_VOLTAGE_NUM 0x40 + +#define BD71837_BUCK5_VOLTAGE_NUM 0x08 +#define BD71837_BUCK6_VOLTAGE_NUM 0x04 +#define BD71837_BUCK7_VOLTAGE_NUM 0x08 +#define BD71837_BUCK8_VOLTAGE_NUM 0x40 + +#define BD71837_LDO1_VOLTAGE_NUM 0x04 +#define BD71837_LDO2_VOLTAGE_NUM 0x02 +#define BD71837_LDO3_VOLTAGE_NUM 0x10 +#define BD71837_LDO4_VOLTAGE_NUM 0x10 +#define BD71837_LDO5_VOLTAGE_NUM 0x10 +#define BD71837_LDO6_VOLTAGE_NUM 0x10 +#define BD71837_LDO7_VOLTAGE_NUM 0x10 + +enum { + BD71837_REG_REV = 0x00, + BD71837_REG_SWRESET = 0x01, + BD71837_REG_I2C_DEV = 0x02, + BD71837_REG_PWRCTRL0 = 0x03, + BD71837_REG_PWRCTRL1 = 0x04, + BD71837_REG_BUCK1_CTRL = 0x05, + BD71837_REG_BUCK2_CTRL = 0x06, + BD71837_REG_BUCK3_CTRL = 0x07, + BD71837_REG_BUCK4_CTRL = 0x08, + BD71837_REG_BUCK5_CTRL = 0x09, + BD71837_REG_BUCK6_CTRL = 0x0A, + BD71837_REG_BUCK7_CTRL = 0x0B, + BD71837_REG_BUCK8_CTRL = 0x0C, + BD71837_REG_BUCK1_VOLT_RUN = 0x0D, + BD71837_REG_BUCK1_VOLT_IDLE = 0x0E, + BD71837_REG_BUCK1_VOLT_SUSP = 0x0F, + BD71837_REG_BUCK2_VOLT_RUN = 0x10, + BD71837_REG_BUCK2_VOLT_IDLE = 0x11, + BD71837_REG_BUCK3_VOLT_RUN = 0x12, + BD71837_REG_BUCK4_VOLT_RUN = 0x13, + BD71837_REG_BUCK5_VOLT = 0x14, + BD71837_REG_BUCK6_VOLT = 0x15, + BD71837_REG_BUCK7_VOLT = 0x16, + BD71837_REG_BUCK8_VOLT = 0x17, + BD71837_REG_LDO1_VOLT = 0x18, + BD71837_REG_LDO2_VOLT = 0x19, + BD71837_REG_LDO3_VOLT = 0x1A, + BD71837_REG_LDO4_VOLT = 0x1B, + BD71837_REG_LDO5_VOLT = 0x1C, + BD71837_REG_LDO6_VOLT = 0x1D, + BD71837_REG_LDO7_VOLT = 0x1E, + BD71837_REG_TRANS_COND0 = 0x1F, + BD71837_REG_TRANS_COND1 = 0x20, + BD71837_REG_VRFAULTEN = 0x21, + BD71837_REG_MVRFLTMASK0 = 0x22, + BD71837_REG_MVRFLTMASK1 = 0x23, + BD71837_REG_MVRFLTMASK2 = 0x24, + BD71837_REG_RCVCFG = 0x25, + BD71837_REG_RCVNUM = 0x26, + BD71837_REG_PWRONCONFIG0 = 0x27, + BD71837_REG_PWRONCONFIG1 = 0x28, + BD71837_REG_RESETSRC = 0x29, + BD71837_REG_MIRQ = 0x2A, + BD71837_REG_IRQ = 0x2B, + BD71837_REG_IN_MON = 0x2C, + BD71837_REG_POW_STATE = 0x2D, + BD71837_REG_OUT32K = 0x2E, + BD71837_REG_REGLOCK = 0x2F, + BD71837_REG_OTPVER = 0xFF, + BD71837_MAX_REGISTER = 0x100, +}; + +/* BD71837_REG_BUCK1_CTRL bits */ +#define BUCK1_RAMPRATE_MASK 0xC0 +#define BUCK1_RAMPRATE_10P00MV 0x0 +#define BUCK1_RAMPRATE_5P00MV 0x1 +#define BUCK1_RAMPRATE_2P50MV 0x2 +#define BUCK1_RAMPRATE_1P25MV 0x3 +#define BUCK1_SEL 0x02 +#define BUCK1_EN 0x01 + +/* BD71837_REG_BUCK2_CTRL bits */ +#define BUCK2_RAMPRATE_MASK 0xC0 +#define BUCK2_RAMPRATE_10P00MV 0x0 +#define BUCK2_RAMPRATE_5P00MV 0x1 +#define BUCK2_RAMPRATE_2P50MV 0x2 +#define BUCK2_RAMPRATE_1P25MV 0x3 +#define BUCK2_SEL 0x02 +#define BUCK2_EN 0x01 + +/* BD71837_REG_BUCK3_CTRL bits */ +#define BUCK3_RAMPRATE_MASK 0xC0 +#define BUCK3_RAMPRATE_10P00MV 0x0 +#define BUCK3_RAMPRATE_5P00MV 0x1 +#define BUCK3_RAMPRATE_2P50MV 0x2 +#define BUCK3_RAMPRATE_1P25MV 0x3 +#define BUCK3_SEL 0x02 +#define BUCK3_EN 0x01 + +/* BD71837_REG_BUCK4_CTRL bits */ +#define BUCK4_RAMPRATE_MASK 0xC0 +#define BUCK4_RAMPRATE_10P00MV 0x0 +#define BUCK4_RAMPRATE_5P00MV 0x1 +#define BUCK4_RAMPRATE_2P50MV 0x2 +#define BUCK4_RAMPRATE_1P25MV 0x3 +#define BUCK4_SEL 0x02 +#define BUCK4_EN 0x01 + +/* BD71837_REG_BUCK5_CTRL bits */ +#define BUCK5_SEL 0x02 +#define BUCK5_EN 0x01 + +/* BD71837_REG_BUCK6_CTRL bits */ +#define BUCK6_SEL 0x02 +#define BUCK6_EN 0x01 + +/* BD71837_REG_BUCK7_CTRL bits */ +#define BUCK7_SEL 0x02 +#define BUCK7_EN 0x01 + +/* BD71837_REG_BUCK8_CTRL bits */ +#define BUCK8_SEL 0x02 +#define BUCK8_EN 0x01 + +/* BD71837_REG_BUCK1_VOLT_RUN bits */ +#define BUCK1_RUN_MASK 0x3F +#define BUCK1_RUN_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_SUSP bits */ +#define BUCK1_SUSP_MASK 0x3F +#define BUCK1_SUSP_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_IDLE bits */ +#define BUCK1_IDLE_MASK 0x3F +#define BUCK1_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK2_VOLT_RUN bits */ +#define BUCK2_RUN_MASK 0x3F +#define BUCK2_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK2_VOLT_IDLE bits */ +#define BUCK2_IDLE_MASK 0x3F +#define BUCK2_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK3_VOLT_RUN bits */ +#define BUCK3_RUN_MASK 0x3F +#define BUCK3_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK4_VOLT_RUN bits */ +#define BUCK4_RUN_MASK 0x3F +#define BUCK4_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK5_VOLT bits */ +#define BUCK5_MASK 0x07 +#define BUCK5_DEFAULT 0x02 + +/* BD71837_REG_BUCK6_VOLT bits */ +#define BUCK6_MASK 0x03 +#define BUCK6_DEFAULT 0x03 + +/* BD71837_REG_BUCK7_VOLT bits */ +#define BUCK7_MASK 0x07 +#define BUCK7_DEFAULT 0x03 + +/* BD71837_REG_BUCK8_VOLT bits */ +#define BUCK8_MASK 0x3F +#define BUCK8_DEFAULT 0x1E + +/* BD71837_REG_IRQ bits */ +#define IRQ_SWRST 0x40 +#define IRQ_PWRON_S 0x20 +#define IRQ_PWRON_L 0x10 +#define IRQ_PWRON 0x08 +#define IRQ_WDOG 0x04 +#define IRQ_ON_REQ 0x02 +#define IRQ_STBY_REQ 0x01 + +/* BD71837_REG_OUT32K bits */ +#define OUT32K_EN 0x01 + +/* BD71837 interrupt masks */ +enum { + BD71837_INT_MASK = 0x7F, +}; +/* BD71837 interrupt irqs */ +enum { + BD71837_IRQ = 0x0, +}; + +/* BD71837_REG_LDO1_VOLT bits */ +#define LDO1_SEL 0x80 +#define LDO1_EN 0x40 +#define LDO1_MASK 0x03 + +/* BD71837_REG_LDO2_VOLT bits */ +#define LDO2_SEL 0x80 +#define LDO2_EN 0x40 + +/* BD71837_REG_LDO3_VOLT bits */ +#define LDO3_SEL 0x80 +#define LDO3_EN 0x40 +#define LDO3_MASK 0x0F + +/* BD71837_REG_LDO4_VOLT bits */ +#define LDO4_SEL 0x80 +#define LDO4_EN 0x40 +#define LDO4_MASK 0x0F + +/* BD71837_REG_LDO5_VOLT bits */ +#define LDO5_EN 0x40 +#define LDO5_MASK 0x0F + +/* BD71837_REG_LDO6_VOLT bits */ +#define LDO6_EN 0x40 +#define LDO6_MASK 0x0F + +/* BD71837_REG_LDO7_VOLT bits */ +#define LDO7_EN 0x40 +#define LDO7_MASK 0x0F + +/** @brief charge state enumuration */ +enum CHG_STATE { + CHG_STATE_SUSPEND = 0x0, /**< suspend state */ + CHG_STATE_TRICKLE_CHARGE, /**< trickle charge state */ + CHG_STATE_PRE_CHARGE, /**< precharge state */ + CHG_STATE_FAST_CHARGE, /**< fast charge state */ + CHG_STATE_TOP_OFF, /**< top off state */ + CHG_STATE_DONE, /**< charge complete */ +}; + +struct bd71837; + +/** + * @brief Board platform data may be used to initialize regulators. + */ + +struct bd71837_board { + struct regulator_init_data *init_data[BD71837_REGULATOR_CNT]; + /**< regulator initialize data */ + int gpio_intr; /**< gpio connected to bd71837 INTB */ + int irq_base; /**< bd71837 sub irqs base # */ +}; + +/** + * @brief bd71837 sub-driver chip access routines + */ + +struct bd71837 { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + struct mutex io_mutex; + unsigned int id; + + /* IRQ Handling */ + int chip_irq; /**< bd71837 irq to host cpu */ + struct regmap_irq_chip_data *irq_data; + + /* Client devices */ + struct bd71837_pmic *pmic; /**< client device regulator */ + struct bd71837_power *power; /**< client device battery */ + + struct bd71837_board *of_plat_data; + /**< Device node parsed board data */ +}; + +static inline int bd71837_chip_id(struct bd71837 *bd71837) +{ + return bd71837->id; +} + + +/** + * @brief bd71837_reg_read + * read single register's value of bd71837 + * @param bd71837 device to read + * @param reg register address + * @return register value if success + * error number if fail + */ +static inline int bd71837_reg_read(struct bd71837 *bd71837, u8 reg) +{ + int r, val; + + r = regmap_read(bd71837->regmap, reg, &val); + if (r < 0) { + return r; + } + return val; +} + +/** + * @brief bd71837_reg_write + * write single register of bd71837 + * @param bd71837 device to write + * @param reg register address + * @param val value to write + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_reg_write(struct bd71837 *bd71837, u8 reg, + unsigned int val) +{ + return regmap_write(bd71837->regmap, reg, val); +} + +/** + * @brief bd71837_set_bits + * set bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ +static inline int bd71837_set_bits(struct bd71837 *bd71837, u8 reg, u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, mask); +} + +/** + * @brief bd71837_clear_bits + * clear bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_clear_bits(struct bd71837 *bd71837, u8 reg, + u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, 0); +} + +/** + * @brief bd71837_update_bits + * update bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @param val value to update + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_update_bits(struct bd71837 *bd71837, u8 reg, + u8 mask, u8 val) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, val); +} + +/** + * @brief bd71837 platform data type + */ +struct bd71837_gpo_plat_data { + u32 drv; ///< gpo output drv + int gpio_base; ///< base gpio number in system +}; + +u8 ext_bd71837_reg_read8(u8 reg); +int ext_bd71837_reg_write8(int reg, u8 val); + +#define BD71837_DBG0 0x0001 +#define BD71837_DBG1 0x0002 +#define BD71837_DBG2 0x0004 +#define BD71837_DBG3 0x0008 + +extern unsigned int bd71837_debug_mask; +#define bd71837_debug(debug, fmt, arg...) do { if (debug & bd71837_debug_mask) printk("BD71837:" fmt, ##arg); } while (0) + +#endif /* __LINUX_MFD_BD71837_H */ diff --git a/include/linux/mfd/max17135.h b/include/linux/mfd/max17135.h new file mode 100644 index 000000000000..e3b8777c8630 --- /dev/null +++ b/include/linux/mfd/max17135.h @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __LINUX_REGULATOR_MAX17135_H_ +#define __LINUX_REGULATOR_MAX17135_H_ + +/* + * PMIC Register Addresses + */ +enum { + REG_MAX17135_EXT_TEMP = 0x0, + REG_MAX17135_CONFIG, + REG_MAX17135_INT_TEMP = 0x4, + REG_MAX17135_STATUS, + REG_MAX17135_PRODUCT_REV, + REG_MAX17135_PRODUCT_ID, + REG_MAX17135_DVR, + REG_MAX17135_ENABLE, + REG_MAX17135_FAULT, /*0x0A*/ + REG_MAX17135_HVINP, + REG_MAX17135_PRGM_CTRL, + REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */ + REG_MAX17135_TIMING2, + REG_MAX17135_TIMING3, + REG_MAX17135_TIMING4, + REG_MAX17135_TIMING5, + REG_MAX17135_TIMING6, + REG_MAX17135_TIMING7, + REG_MAX17135_TIMING8, +}; +#define MAX17135_REG_NUM 21 +#define MAX17135_MAX_REGISTER 0xFF + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Shift and width values for each register bitfield + */ +#define EXT_TEMP_LSH 7 +#define EXT_TEMP_WID 9 + +#define THERMAL_SHUTDOWN_LSH 0 +#define THERMAL_SHUTDOWN_WID 1 + +#define INT_TEMP_LSH 7 +#define INT_TEMP_WID 9 + +#define STAT_BUSY_LSH 0 +#define STAT_BUSY_WID 1 +#define STAT_OPEN_LSH 1 +#define STAT_OPEN_WID 1 +#define STAT_SHRT_LSH 2 +#define STAT_SHRT_WID 1 + +#define PROD_REV_LSH 0 +#define PROD_REV_WID 8 + +#define PROD_ID_LSH 0 +#define PROD_ID_WID 8 + +#define DVR_LSH 0 +#define DVR_WID 8 + +#define ENABLE_LSH 0 +#define ENABLE_WID 1 +#define VCOM_ENABLE_LSH 1 +#define VCOM_ENABLE_WID 1 + +#define FAULT_FBPG_LSH 0 +#define FAULT_FBPG_WID 1 +#define FAULT_HVINP_LSH 1 +#define FAULT_HVINP_WID 1 +#define FAULT_HVINN_LSH 2 +#define FAULT_HVINN_WID 1 +#define FAULT_FBNG_LSH 3 +#define FAULT_FBNG_WID 1 +#define FAULT_HVINPSC_LSH 4 +#define FAULT_HVINPSC_WID 1 +#define FAULT_HVINNSC_LSH 5 +#define FAULT_HVINNSC_WID 1 +#define FAULT_OT_LSH 6 +#define FAULT_OT_WID 1 +#define FAULT_POK_LSH 7 +#define FAULT_POK_WID 1 + +#define HVINP_LSH 0 +#define HVINP_WID 4 + +#define CTRL_DVR_LSH 0 +#define CTRL_DVR_WID 1 +#define CTRL_TIMING_LSH 1 +#define CTRL_TIMING_WID 1 + +#define TIMING1_LSH 0 +#define TIMING1_WID 8 +#define TIMING2_LSH 0 +#define TIMING2_WID 8 +#define TIMING3_LSH 0 +#define TIMING3_WID 8 +#define TIMING4_LSH 0 +#define TIMING4_WID 8 +#define TIMING5_LSH 0 +#define TIMING5_WID 8 +#define TIMING6_LSH 0 +#define TIMING6_WID 8 +#define TIMING7_LSH 0 +#define TIMING7_WID 8 +#define TIMING8_LSH 0 +#define TIMING8_WID 8 + +struct max17135 { + /* chip revision */ + int rev; + + struct device *dev; + struct max17135_platform_data *pdata; + + /* Platform connection */ + struct i2c_client *i2c_client; + + /* Timings */ + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + + /* GPIOs */ + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + + /* MAX17135 part variables */ + int pass_num; + int vcom_uV; + + /* One-time VCOM setup marker */ + bool vcom_setup; + + /* powerup/powerdown wait time */ + int max_wait; +}; + +enum { + /* In alphabetical order */ + MAX17135_DISPLAY, /* virtual master enable */ + MAX17135_GVDD, + MAX17135_GVEE, + MAX17135_HVINN, + MAX17135_HVINP, + MAX17135_VCOM, + MAX17135_VNEG, + MAX17135_VPOS, + MAX17135_V3P3, + MAX17135_NUM_REGULATORS, +}; + +/* + * Declarations + */ +struct regulator_init_data; +struct max17135_regulator_data; + +struct max17135_platform_data { + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + int pass_num; + int vcom_uV; + + /* PMIC */ + struct max17135_regulator_data *regulators; + int num_regulators; +}; + +struct max17135_regulator_data { + int id; + struct regulator_init_data *initdata; + struct device_node *reg_node; +}; + +int max17135_reg_read(int reg_num, unsigned int *reg_val); +int max17135_reg_write(int reg_num, const unsigned int reg_val); + +#endif diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h new file mode 100644 index 000000000000..b2696b951f43 --- /dev/null +++ b/include/linux/mfd/mxc-hdmi-core.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_MXC_HDMI_CORE_H_ +#define __LINUX_MXC_HDMI_CORE_H_ + +#include <video/mxc_edid.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#define IRQ_DISABLE_SUCCEED 0 +#define IRQ_DISABLE_FAIL 1 + +bool hdmi_check_overflow(void); + +u8 hdmi_readb(unsigned int reg); +void hdmi_writeb(u8 value, unsigned int reg); +void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask); +unsigned int hdmi_read4(unsigned int reg); +void hdmi_write4(unsigned int value, unsigned int reg); + +void hdmi_irq_init(void); +void hdmi_irq_enable(int irq); +unsigned int hdmi_irq_disable(int irq); + +void hdmi_set_sample_rate(unsigned int rate); +void hdmi_set_dma_mode(unsigned int dma_running); +void hdmi_init_clk_regenerator(void); +void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock); + +void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg); +void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg); + +extern int mxc_hdmi_ipu_id; +extern int mxc_hdmi_disp_id; + +void hdmi_set_registered(int registered); +int hdmi_get_registered(void); +int mxc_hdmi_abort_stream(void); +int mxc_hdmi_register_audio(struct snd_pcm_substream *substream); +void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream); +unsigned int hdmi_set_cable_state(unsigned int state); +unsigned int hdmi_set_blank_state(unsigned int state); +int check_hdmi_state(void); + +#endif diff --git a/include/linux/mfd/pf1550.h b/include/linux/mfd/pf1550.h new file mode 100644 index 000000000000..7d0a13e1144a --- /dev/null +++ b/include/linux/mfd/pf1550.h @@ -0,0 +1,250 @@ +/* + * pf1550.h - mfd head file for PF1550 + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Robin Gong <yibin.gong@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_MFD_PF1550_H +#define __LINUX_MFD_PF1550_H + +#include <linux/i2c.h> + +enum chips { PF1550 = 1, }; + +enum pf1550_pmic_reg { + /* PMIC regulator part */ + PF1550_PMIC_REG_DEVICE_ID = 0x00, + PF1550_PMIC_REG_OTP_FLAVOR = 0x01, + PF1550_PMIC_REG_SILICON_REV = 0x02, + + PF1550_PMIC_REG_INT_CATEGORY = 0x06, + PF1550_PMIC_REG_SW_INT_STAT0 = 0x08, + PF1550_PMIC_REG_SW_INT_MASK0 = 0x09, + PF1550_PMIC_REG_SW_INT_SENSE0 = 0x0A, + PF1550_PMIC_REG_SW_INT_STAT1 = 0x0B, + PF1550_PMIC_REG_SW_INT_MASK1 = 0x0C, + PF1550_PMIC_REG_SW_INT_SENSE1 = 0x0D, + PF1550_PMIC_REG_SW_INT_STAT2 = 0x0E, + PF1550_PMIC_REG_SW_INT_MASK2 = 0x0F, + PF1550_PMIC_REG_SW_INT_SENSE2 = 0x10, + PF1550_PMIC_REG_LDO_INT_STAT0 = 0x18, + PF1550_PMIC_REG_LDO_INT_MASK0 = 0x19, + PF1550_PMIC_REG_LDO_INT_SENSE0 = 0x1A, + PF1550_PMIC_REG_TEMP_INT_STAT0 = 0x20, + PF1550_PMIC_REG_TEMP_INT_MASK0 = 0x21, + PF1550_PMIC_REG_TEMP_INT_SENSE0 = 0x22, + PF1550_PMIC_REG_ONKEY_INT_STAT0 = 0x24, + PF1550_PMIC_REG_ONKEY_INT_MASK0 = 0x25, + PF1550_PMIC_REG_ONKEY_INT_SENSE0 = 0x26, + PF1550_PMIC_REG_MISC_INT_STAT0 = 0x28, + PF1550_PMIC_REG_MISC_INT_MASK0 = 0x29, + PF1550_PMIC_REG_MISC_INT_SENSE0 = 0x2A, + + PF1550_PMIC_REG_COINCELL_CONTROL = 0x30, + + PF1550_PMIC_REG_SW1_VOLT = 0x32, + PF1550_PMIC_REG_SW1_STBY_VOLT = 0x33, + PF1550_PMIC_REG_SW1_SLP_VOLT = 0x34, + PF1550_PMIC_REG_SW1_CTRL = 0x35, + PF1550_PMIC_REG_SW1_CTRL1 = 0x36, + PF1550_PMIC_REG_SW2_VOLT = 0x38, + PF1550_PMIC_REG_SW2_STBY_VOLT = 0x39, + PF1550_PMIC_REG_SW2_SLP_VOLT = 0x3A, + PF1550_PMIC_REG_SW2_CTRL = 0x3B, + PF1550_PMIC_REG_SW2_CTRL1 = 0x3C, + PF1550_PMIC_REG_SW3_VOLT = 0x3E, + PF1550_PMIC_REG_SW3_STBY_VOLT = 0x3F, + PF1550_PMIC_REG_SW3_SLP_VOLT = 0x40, + PF1550_PMIC_REG_SW3_CTRL = 0x41, + PF1550_PMIC_REG_SW3_CTRL1 = 0x42, + PF1550_PMIC_REG_VSNVS_CTRL = 0x48, + PF1550_PMIC_REG_VREFDDR_CTRL = 0x4A, + PF1550_PMIC_REG_LDO1_VOLT = 0x4C, + PF1550_PMIC_REG_LDO1_CTRL = 0x4D, + PF1550_PMIC_REG_LDO2_VOLT = 0x4F, + PF1550_PMIC_REG_LDO2_CTRL = 0x50, + PF1550_PMIC_REG_LDO3_VOLT = 0x52, + PF1550_PMIC_REG_LDO3_CTRL = 0x53, + PF1550_PMIC_REG_PWRCTRL0 = 0x58, + PF1550_PMIC_REG_PWRCTRL1 = 0x59, + PF1550_PMIC_REG_PWRCTRL2 = 0x5A, + PF1550_PMIC_REG_PWRCTRL3 = 0x5B, + PF1550_PMIC_REG_SW1_PWRDN_SEQ = 0x5F, + PF1550_PMIC_REG_SW2_PWRDN_SEQ = 0x60, + PF1550_PMIC_REG_SW3_PWRDN_SEQ = 0x61, + PF1550_PMIC_REG_LDO1_PWRDN_SEQ = 0x62, + PF1550_PMIC_REG_LDO2_PWRDN_SEQ = 0x63, + PF1550_PMIC_REG_LDO3_PWRDN_SEQ = 0x64, + PF1550_PMIC_REG_VREFDDR_PWRDN_SEQ = 0x65, + + PF1550_PMIC_REG_STATE_INFO = 0x67, + PF1550_PMIC_REG_I2C_ADDR = 0x68, + PF1550_PMIC_REG_IO_DRV0 = 0x69, + PF1550_PMIC_REG_IO_DRV1 = 0x6A, + PF1550_PMIC_REG_RC_16MHZ = 0x6B, + PF1550_PMIC_REG_KEY = 0x6F, + + /* charger part */ + PF1550_CHARG_REG_CHG_INT = 0x80, + PF1550_CHARG_REG_CHG_INT_MASK = 0x82, + PF1550_CHARG_REG_CHG_INT_OK = 0x84, + PF1550_CHARG_REG_VBUS_SNS = 0x86, + PF1550_CHARG_REG_CHG_SNS = 0x87, + PF1550_CHARG_REG_BATT_SNS = 0x88, + PF1550_CHARG_REG_CHG_OPER = 0x89, + PF1550_CHARG_REG_CHG_TMR = 0x8A, + PF1550_CHARG_REG_CHG_EOC_CNFG = 0x8D, + PF1550_CHARG_REG_CHG_CURR_CNFG = 0x8E, + PF1550_CHARG_REG_BATT_REG = 0x8F, + PF1550_CHARG_REG_BATFET_CNFG = 0x91, + PF1550_CHARG_REG_THM_REG_CNFG = 0x92, + PF1550_CHARG_REG_VBUS_INLIM_CNFG = 0x94, + PF1550_CHARG_REG_VBUS_LIN_DPM = 0x95, + PF1550_CHARG_REG_USB_PHY_LDO_CNFG = 0x96, + PF1550_CHARG_REG_DBNC_DELAY_TIME = 0x98, + PF1550_CHARG_REG_CHG_INT_CNFG = 0x99, + PF1550_CHARG_REG_THM_ADJ_SETTING = 0x9A, + PF1550_CHARG_REG_VBUS2SYS_CNFG = 0x9B, + PF1550_CHARG_REG_LED_PWM = 0x9C, + PF1550_CHARG_REG_FAULT_BATFET_CNFG = 0x9D, + PF1550_CHARG_REG_LED_CNFG = 0x9E, + PF1550_CHARG_REG_CHGR_KEY2 = 0x9F, + + PF1550_TEST_REG_FMRADDR = 0xC4, + PF1550_TEST_REG_FMRDATA = 0xC5, + PF1550_TEST_REG_KEY3 = 0xDF, + + PF1550_PMIC_REG_END = 0xff, +}; + +#define PF1550_CHG_PRECHARGE 0 +#define PF1550_CHG_CONSTANT_CURRENT 1 +#define PF1550_CHG_CONSTANT_VOL 2 +#define PF1550_CHG_EOC 3 +#define PF1550_CHG_DONE 4 +#define PF1550_CHG_TIMER_FAULT 6 +#define PF1550_CHG_SUSPEND 7 +#define PF1550_CHG_OFF_INV 8 +#define PF1550_CHG_BAT_OVER 9 +#define PF1550_CHG_OFF_TEMP 10 +#define PF1550_CHG_LINEAR_ONLY 12 +#define PF1550_CHG_SNS_MASK 0xf + +#define PF1550_BAT_NO_VBUS 0 +#define PF1550_BAT_LOW_THAN_PRECHARG 1 +#define PF1550_BAT_CHARG_FAIL 2 +#define PF1550_BAT_HIGH_THAN_PRECHARG 4 +#define PF1550_BAT_OVER_VOL 5 +#define PF1550_BAT_NO_DETECT 6 +#define PF1550_BAT_SNS_MASK 0x7 + +#define PF1550_VBUS_UVLO BIT(2) +#define PF1550_VBUS_IN2SYS BIT(3) +#define PF1550_VBUS_OVLO BIT(4) +#define PF1550_VBUS_VALID BIT(5) + +#define PF1550_CHARG_REG_BATT_REG_CHGCV_MASK 0x3f +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT 6 +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK (0x3 << 6) +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT 2 +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK (0x3 << 2) + +#define PMIC_IRQ_SW1_LS BIT(0) +#define PMIC_IRQ_SW2_LS BIT(1) +#define PMIC_IRQ_SW3_LS BIT(2) +#define PMIC_IRQ_SW1_HS BIT(0) +#define PMIC_IRQ_SW2_HS BIT(1) +#define PMIC_IRQ_SW3_HS BIT(2) +#define PMIC_IRQ_LDO1_FAULT BIT(0) +#define PMIC_IRQ_LDO2_FAULT BIT(1) +#define PMIC_IRQ_LDO3_FAULT BIT(2) +#define PMIC_IRQ_TEMP_110 BIT(0) +#define PMIC_IRQ_TEMP_125 BIT(1) + +#define ONKEY_IRQ_PUSHI BIT(0) +#define ONKEY_IRQ_1SI BIT(1) +#define ONKEY_IRQ_2SI BIT(2) +#define ONKEY_IRQ_3SI BIT(3) +#define ONKEY_IRQ_4SI BIT(4) +#define ONKEY_IRQ_8SI BIT(5) + +#define CHARG_IRQ_BAT2SOCI BIT(1) +#define CHARG_IRQ_BATI BIT(2) +#define CHARG_IRQ_CHGI BIT(3) +#define CHARG_IRQ_VBUSI BIT(5) +#define CHARG_IRQ_DPMI BIT(6) +#define CHARG_IRQ_THMI BIT(7) + +enum pf1550_pmic_irq { + PF1550_PMIC_IRQ_SW1_LS, + PF1550_PMIC_IRQ_SW2_LS, + PF1550_PMIC_IRQ_SW3_LS, + PF1550_PMIC_IRQ_SW1_HS, + PF1550_PMIC_IRQ_SW2_HS, + PF1550_PMIC_IRQ_SW3_HS, + PF1550_PMIC_IRQ_LDO1_FAULT, + PF1550_PMIC_IRQ_LDO2_FAULT, + PF1550_PMIC_IRQ_LDO3_FAULT, + PF1550_PMIC_IRQ_TEMP_110, + PF1550_PMIC_IRQ_TEMP_125, +}; + +enum pf1550_onkey_irq { + PF1550_ONKEY_IRQ_PUSHI, + PF1550_ONKEY_IRQ_1SI, + PF1550_ONKEY_IRQ_2SI, + PF1550_ONKEY_IRQ_3SI, + PF1550_ONKEY_IRQ_4SI, + PF1550_ONKEY_IRQ_8SI, +}; + +enum pf1550_charg_irq { + PF1550_CHARG_IRQ_BAT2SOCI, + PF1550_CHARG_IRQ_BATI, + PF1550_CHARG_IRQ_CHGI, + PF1550_CHARG_IRQ_VBUSI, + PF1550_CHARG_IRQ_THMI, +}; + +enum pf1550_regulators { + PF1550_SW1, + PF1550_SW2, + PF1550_SW3, + PF1550_VREFDDR, + PF1550_LDO1, + PF1550_LDO2, + PF1550_LDO3, +}; + +struct pf1550_irq_info { + unsigned int irq; + const char *name; + unsigned int virq; +}; + +struct pf1550_dev { + struct device *dev; + struct i2c_client *i2c; + int type; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data_regulator; + struct regmap_irq_chip_data *irq_data_onkey; + struct regmap_irq_chip_data *irq_data_charger; + int irq; +}; + +int pf1550_read_otp(struct pf1550_dev *pf1550, unsigned int index, + unsigned int *val); + +#endif /* __LINUX_MFD_PF1550_H */ diff --git a/include/linux/mfd/si476x-core.h b/include/linux/mfd/si476x-core.h index 674b45d5a757..78a2b2c936f3 100644 --- a/include/linux/mfd/si476x-core.h +++ b/include/linux/mfd/si476x-core.h @@ -493,6 +493,8 @@ enum si476x_common_receiver_properties { SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202, SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203, + SI476X_PROP_AUDIO_MUTE = 0x0301, + SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100, SI476X_PROP_SEEK_BAND_TOP = 0x1101, SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102, diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..29f225235782 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -101,6 +101,7 @@ #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) #define IMX6Q_GPR1_DPI_OFF BIT(24) +#define IMX6Q_GPR1_PCIE_SW_PERST BIT(23) #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) @@ -243,6 +244,23 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) +#define IMX6Q_GPR5_PRE_PRG_SEL0_MASK (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_SHIFT 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_MSB 13 +#define IMX6Q_GPR5_PRE_PRG_SEL0_LSB 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN1 (0x0 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN2 (0x1 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN1 (0x2 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN2 (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL1_MASK (0x3 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_SHIFT 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_MSB 15 +#define IMX6Q_GPR5_PRE_PRG_SEL1_LSB 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN1 (0x0 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN2 (0x1 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN1 (0x2 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN2 (0x3 << 14) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) @@ -286,23 +304,25 @@ #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2) #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0) #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IMX6Q_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) +#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) @@ -411,6 +431,15 @@ #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26) +#define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25) +#define IMX6SX_GPR2_MQS_EN_SHIFT (25) +#define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24) +#define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24) +#define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16) +#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16) + #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) @@ -423,6 +452,7 @@ #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26) +#define IMX6SX_GPR5_PCIE_PERST BIT(18) #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) @@ -437,10 +467,21 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) +/* For imx6dl iomux gpr register field definitions */ +#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6) + /* For imx6ul iomux gpr register field define */ #define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) #define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h index 4585d6105d68..e0cbf3cd8f82 100644 --- a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h @@ -34,6 +34,8 @@ #define IOMUXC_GPR22 0x58 /* For imx7d iomux gpr register field define */ +#define IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (0x3 << 7) + #define IMX7D_GPR1_IRQ_MASK (0x1 << 12) #define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13) #define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14) diff --git a/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file mode 100644 index 000000000000..cfb857774cf5 --- /dev/null +++ b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */ diff --git a/include/linux/mipi_csi2.h b/include/linux/mipi_csi2.h new file mode 100644 index 000000000000..7dc76fd293f8 --- /dev/null +++ b/include/linux/mipi_csi2.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_CSI2_H +#define __INCLUDE_MIPI_CSI2_H + +/* MIPI CSI2 registers */ +#define MIPI_CSI2_REG(offset) (offset) + +#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000) +#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004) +#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008) +#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c) +#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010) +#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014) +#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018) +#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c) +#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020) +#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024) +#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028) +#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c) +#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030) +#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034) +#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00) + +/* mipi data type */ +#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ +#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */ +#define MIPI_DT_YUV422 0x1e /* UYVY... */ +#define MIPI_DT_RGB444 0x20 +#define MIPI_DT_RGB555 0x21 +#define MIPI_DT_RGB565 0x22 +#define MIPI_DT_RGB666 0x23 +#define MIPI_DT_RGB888 0x24 +#define MIPI_DT_RAW6 0x28 +#define MIPI_DT_RAW7 0x29 +#define MIPI_DT_RAW8 0x2a +#define MIPI_DT_RAW10 0x2b +#define MIPI_DT_RAW12 0x2c +#define MIPI_DT_RAW14 0x2d + + +struct mipi_csi2_info; +/* mipi csi2 API */ +struct mipi_csi2_info *mipi_csi2_get_info(void); + +bool mipi_csi2_enable(struct mipi_csi2_info *info); + +bool mipi_csi2_disable(struct mipi_csi2_info *info); + +bool mipi_csi2_get_status(struct mipi_csi2_info *info); + +int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info, + unsigned int datatype); + +unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info); + +int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info); + +void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info); + +int mipi_csi2_reset(struct mipi_csi2_info *info); + +#endif diff --git a/include/linux/mipi_dsi.h b/include/linux/mipi_dsi.h new file mode 100644 index 000000000000..dbc249a38f68 --- /dev/null +++ b/include/linux/mipi_dsi.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_MIPI_DSI_H +#define __INCLUDE_MIPI_DSI_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_PWR_UP (0x004) +#define MIPI_DSI_CLKMGR_CFG (0x008) +#define MIPI_DSI_DPI_CFG (0x00c) +#define MIPI_DSI_DBI_CFG (0x010) +#define MIPI_DSI_DBIS_CMDSIZE (0x014) +#define MIPI_DSI_PCKHDL_CFG (0x018) +#define MIPI_DSI_VID_MODE_CFG (0x01c) +#define MIPI_DSI_VID_PKT_CFG (0x020) +#define MIPI_DSI_CMD_MODE_CFG (0x024) +#define MIPI_DSI_TMR_LINE_CFG (0x028) +#define MIPI_DSI_VTIMING_CFG (0x02c) +#define MIPI_DSI_PHY_TMR_CFG (0x030) +#define MIPI_DSI_GEN_HDR (0x034) +#define MIPI_DSI_GEN_PLD_DATA (0x038) +#define MIPI_DSI_CMD_PKT_STATUS (0x03c) +#define MIPI_DSI_TO_CNT_CFG (0x040) +#define MIPI_DSI_ERROR_ST0 (0x044) +#define MIPI_DSI_ERROR_ST1 (0x048) +#define MIPI_DSI_ERROR_MSK0 (0x04c) +#define MIPI_DSI_ERROR_MSK1 (0x050) +#define MIPI_DSI_PHY_RSTZ (0x054) +#define MIPI_DSI_PHY_IF_CFG (0x058) +#define MIPI_DSI_PHY_IF_CTRL (0x05c) +#define MIPI_DSI_PHY_STATUS (0x060) +#define MIPI_DSI_PHY_TST_CTRL0 (0x064) +#define MIPI_DSI_PHY_TST_CTRL1 (0x068) + +#define DSI_PWRUP_RESET (0x0 << 0) +#define DSI_PWRUP_POWERUP (0x1 << 0) + +#define DSI_DPI_CFG_VID_SHIFT (0) +#define DSI_DPI_CFG_VID_MASK (0x3) +#define DSI_DPI_CFG_COLORCODE_SHIFT (2) +#define DSI_DPI_CFG_COLORCODE_MASK (0x7) +#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5) +#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5) +#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6) +#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6) +#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7) +#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7) +#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8) +#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8) +#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9) +#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9) +#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10) + +#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0) +#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1) +#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2) +#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3) +#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4) +#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3) +#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5) + +#define DSI_VID_MODE_CFG_EN (0x1 << 0) +#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1) +#define DSI_VID_MODE_CFG_TYPE_MASK (0x3) +#define DSI_VID_MODE_CFG_TYPE_SHIFT (1) +#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3) +#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4) +#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5) +#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6) +#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7) +#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8) +#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9) +#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10) +#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11) +#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \ + DSI_VID_MODE_CFG_EN_LP_VBP | \ + DSI_VID_MODE_CFG_EN_LP_VFP | \ + DSI_VID_MODE_CFG_EN_LP_HFP | \ + DSI_VID_MODE_CFG_EN_LP_HBP | \ + DSI_VID_MODE_CFG_EN_LP_VACT) + + + +#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff) +#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21) + +#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF) +#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0) + +#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0) +#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9) +#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff) +#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18) + +#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf) +#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0) +#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4) +#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10) +#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff) +#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16) + +#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff) +#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20) + +#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3) +#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0) +#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff) +#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2) + +#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2) +#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1) +#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0) +#define DSI_PHY_RSTZ_RST (0x0) + +#define DSI_PHY_STATUS_LOCK (0x1 << 0) +#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2) + +#define DSI_GEN_HDR_TYPE_MASK (0xff) +#define DSI_GEN_HDR_TYPE_SHIFT (0) +#define DSI_GEN_HDR_DATA_MASK (0xffff) +#define DSI_GEN_HDR_DATA_SHIFT (8) + +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0) +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4) +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6) + +#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff) +#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff) + +#define DSI_PHY_IF_CTRL_RESET (0x0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1) +#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2) +#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3) +#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4) +#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF) +#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5) + +#define DSI_PHY_CLK_INIT_COMMAND (0x44) +#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4) +#endif diff --git a/include/linux/mipi_dsi_northwest.h b/include/linux/mipi_dsi_northwest.h new file mode 100644 index 000000000000..8cb379c85ef5 --- /dev/null +++ b/include/linux/mipi_dsi_northwest.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_NORTHWEST_H +#define __INCLUDE_MIPI_DSI_NORTHWEST_H + +/* ---------------------------- register offsets --------------------------- */ + +/* sim */ +#define SIM_SOPT1 0x0 +#define MIPI_ISO_DISABLE 0x8 + +#define SIM_SOPT1CFG 0x4 +#define DSI_RST_DPI_N 0x80000000 +#define DSI_RST_ESC_N 0x40000000 +#define DSI_RST_BYTE_N 0x20000000 +#define DSI_SD 0x200 +#define DSI_CM 0x100 +#define DSI_PLL_EN 0x80 + +/* SRC */ +#define SRC_MIPIPHY_RCR 0x28 +#define MIPI_DSI_RESET_BYTE_N 0x2 +#define MIPI_DSI_RESET_N 0x4 +#define MIPI_DSI_DPI_RESET_N 0x8 +#define MIPI_DSI_ESC_RESET_N 0x10 +#define MIPI_DSI_PCLK_RESET_N 0x20 + +/* GPR */ +#define IOMUXC_GPR_GPR13 0x34 +#define GPR_MIPI_MUX_SEL 0x4 + +/* dphy */ +#define DPHY_PD_DPHY 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ + +#endif diff --git a/include/linux/mipi_dsi_samsung.h b/include/linux/mipi_dsi_samsung.h new file mode 100644 index 000000000000..e58da9541cfb --- /dev/null +++ b/include/linux/mipi_dsi_samsung.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_SAMSUNG_H +#define __INCLUDE_MIPI_DSI_SAMSUNG_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_STATUS (0x004) +#define MIPI_DSI_RGB_STATUS (0x008) +#define MIPI_DSI_SWRST (0x00c) +#define MIPI_DSI_CLKCTRL (0x010) +#define MIPI_DSI_TIMEOUT (0x014) +#define MIPI_DSI_CONFIG (0x018) +#define MIPI_DSI_ESCMODE (0x01c) +#define MIPI_DSI_MDRESOL (0x020) +#define MIPI_DSI_MVPORCH (0x024) +#define MIPI_DSI_MHPORCH (0x028) +#define MIPI_DSI_MSYNC (0x02c) +#define MIPI_DSI_SDRESOL (0x030) +#define MIPI_DSI_INTSRC (0x034) +#define MIPI_DSI_INTMSK (0x038) +#define MIPI_DSI_PKTHDR (0x03c) +#define MIPI_DSI_PAYLOAD (0x040) +#define MIPI_DSI_RXFIFO (0x044) +#define MIPI_DSI_FIFOTHLD (0x048) +#define MIPI_DSI_FIFOCTRL (0x04c) +#define MIPI_DSI_MEMACCHR (0x050) +#define MIPI_DSI_MULTI_PKT (0x078) +#define MIPI_DSI_PLLCTRL_1G (0x090) +#define MIPI_DSI_PLLCTRL (0x094) +#define MIPI_DSI_PLLCTRL1 (0x098) +#define MIPI_DSI_PLLCTRL2 (0x09c) +#define MIPI_DSI_PLLTMR (0x0a0) +#define MIPI_DSI_PHYCTRL_B1 (0x0a4) +#define MIPI_DSI_PHYCTRL_B2 (0x0a8) +#define MIPI_DSI_PHYCTRL_M1 (0x0a8) +#define MIPI_DSI_PHYCTRL_M2 (0x0ac) +#define MIPI_DSI_PHYTIMING (0x0b4) +#define MIPI_DSI_PHYTIMING1 (0x0b8) +#define MIPI_DSI_PHYTIMING2 (0x0bc) + +#define MIPI_DSI_SWRST_SWRST (0x1 << 0) +#define MIPI_DSI_SWRST_FUNCRST (0x1 << 16) +#define MIPI_DSI_MAIN_HRESOL(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_MAIN_STANDBY(x) (((x) & 0x1) << 31) +#define MIPI_DSI_MAIN_VBP(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_STABLE_VFP(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_CMDALLOW(x) (((x) & 0xf) << 28) +#define MIPI_DSI_MAIN_HBP(x) (((x) & 0xffff) << 0) +#define MIPI_DSI_MAIN_HFP(x) (((x) & 0xffff) << 16) +#define MIPI_DSI_MAIN_VSA(x) (((x) & 0x3ff) << 22) +#define MIPI_DSI_MAIN_HSA(x) (((x) & 0xffff) << 0) + +#define MIPI_DSI_LANE_EN(x) (((x) & 0x1f) << 0) +#define MIPI_DSI_NUM_OF_DATALANE(x) (((x) & 0x3) << 5) +#define MIPI_DSI_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) +#define MIPI_DSI_MAIN_PIX_FORMAT(x) (((x) & 0x7) << 12) +#define MIPI_DSI_SUB_VC(x) (((x) & 0x3) << 16) +#define MIPI_DSI_MAIN_VC(x) (((x) & 0x3) << 18) +#define MIPI_DSI_HSA_DISABLE_MODE(x) (((x) & 0x1) << 20) +#define MIPI_DSI_HBP_DISABLE_MODE(x) (((x) & 0x1) << 21) +#define MIPI_DSI_HFP_DISABLE_MODE(x) (((x) & 0x1) << 22) +#define MIPI_DSI_HSE_DISABLE_MODE(x) (((x) & 0x1) << 23) +#define MIPI_DSI_AUTO_MODE(x) (((x) & 0x1) << 24) +#define MIPI_DSI_VIDEO_MODE(x) (((x) & 0x1) << 25) +#define MIPI_DSI_BURST_MODE(x) (((x) & 0x1) << 26) +#define MIPI_DSI_SYNC_IN_FORM(x) (((x) & 0x1) << 27) +#define MIPI_DSI_EOT_R03(x) (((x) & 0x1) << 28) +#define MIPI_DSI_MFLUSH_VS(x) (((x) & 0x1) << 29) + +#define MIPI_DSI_DP_DN_SWAP_DATA (0x1 << 24) +#define MIPI_DSI_PLL_EN(x) (((x) & 0x1) << 23) +#define MIPI_DSI_PMS(x) (((x) & 0x7ffff) << 1) + +#define MIPI_DSI_TX_REQUEST_HSCLK(x) (((x) & 0x1) << 31) +#define MIPI_DSI_DPHY_SEL(x) (((x) & 0x1) << 29) +#define MIPI_DSI_ESC_CLK_EN(x) (((x) & 0x1) << 28) +#define MIPI_DSI_PLL_BYPASS(x) (((x) & 0x1) << 27) +#define MIPI_DSI_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) +#define MIPI_DSI_BYTE_CLK_EN(x) (((x) & 0x1) << 24) +#define MIPI_DSI_LANE_ESC_CLK_EN(x) (((x) & 0x1f) << 19) + +#define MIPI_DSI_FORCE_STOP_STATE(x) (((x) & 0x1) << 20) + +#define MIPI_DSI_M_TLPXCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSEXITCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_TCLKPRPRCTL(x) (((x) & 0xff) << 24) +#define MIPI_DSI_M_TCLKZEROCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_TCLKPOSTCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_TCLKTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_THSPRPRCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_THSZEROCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_PLL_STABLE(x) (((x) & 0x1) << 31) +#define MIPI_DSI_TX_READY_HS_CLK(x) (((x) & 0x1) << 10) +#define MIPI_DSI_ULPS_CLK(x) (((x) & 0x1) << 9) +#define MIPI_DSI_STOP_STATE_CLK(x) (((x) & 0x1) << 8) +#define MIPI_DSI_ULPS_DAT(x) (((x) & 0xf) << 4) +#define MIPI_DSI_STOP_STATE_DAT(x) (((x) & 0xf) << 0) + +#define INTSRC_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTSRC_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTSRC_RX_DATA_DONE (0x1 << 18) +#define INTMSK_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTMSK_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTMSK_RX_DATA_DONE (0x1 << 18) + +#define MIPI_DSI_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) +#define MIPI_DSI_CMD_LPDT (0x1 << 7) +#define MIPI_DSI_TX_LPDT (0x1 << 6) + +#endif diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 73fad83acbcb..46c73e97e61f 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -11,7 +11,6 @@ #define LINUX_MMC_CARD_H #include <linux/device.h> -#include <linux/mmc/core.h> #include <linux/mod_devicetable.h> struct mmc_cid { @@ -84,11 +83,15 @@ struct mmc_ext_csd { unsigned int hpi_cmd; /* cmd used as HPI */ bool bkops; /* background support bit */ bool man_bkops_en; /* manual bkops enable bit */ + bool auto_bkops_en; /* auto bkops enable bit */ unsigned int data_sector_size; /* 512 bytes or 4KB */ unsigned int data_tag_unit_size; /* DATA TAG UNIT size */ unsigned int boot_ro_lock; /* ro lock support */ bool boot_ro_lockable; bool ffu_capable; /* Firmware upgrade support */ + bool cmdq_en; /* Command Queue enabled */ + bool cmdq_support; /* Command Queue supported */ + unsigned int cmdq_depth; /* Command Queue depth */ #define MMC_FIRMWARE_LEN 8 u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */ u8 raw_exception_status; /* 54 */ @@ -119,6 +122,9 @@ struct mmc_ext_csd { u8 raw_pwr_cl_ddr_200_360; /* 253 */ u8 raw_bkops_status; /* 246 */ u8 raw_sectors[4]; /* 212 - 4 bytes */ + u8 pre_eol_info; /* 267 */ + u8 device_life_time_est_typ_a; /* 268 */ + u8 device_life_time_est_typ_b; /* 269 */ unsigned int feature_support; #define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */ @@ -201,24 +207,12 @@ struct sdio_cis { }; struct mmc_host; -struct mmc_ios; struct sdio_func; struct sdio_func_tuple; +struct mmc_queue_req; #define SDIO_MAX_FUNCS 7 -enum mmc_blk_status { - MMC_BLK_SUCCESS = 0, - MMC_BLK_PARTIAL, - MMC_BLK_CMD_ERR, - MMC_BLK_RETRY, - MMC_BLK_ABORT, - MMC_BLK_DATA_ERR, - MMC_BLK_ECC_ERR, - MMC_BLK_NOMEDIUM, - MMC_BLK_NEW_REQUEST, -}; - /* The number of MMC physical partitions. These consist of: * boot partitions (2), general purpose partitions (4) and * RPMB partition (1) in MMC v4.4. @@ -257,13 +251,6 @@ struct mmc_card { #define MMC_TYPE_SDIO 2 /* SDIO card */ #define MMC_TYPE_SD_COMBO 3 /* SD combo (IO+mem) card */ unsigned int state; /* (our) card state */ -#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ -#define MMC_STATE_READONLY (1<<1) /* card is read-only */ -#define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */ -#define MMC_CARD_SDXC (1<<3) /* card is SDXC */ -#define MMC_CARD_REMOVED (1<<4) /* card has been removed */ -#define MMC_STATE_DOING_BKOPS (1<<5) /* card is doing BKOPS */ -#define MMC_STATE_SUSPENDED (1<<6) /* card is suspended */ unsigned int quirks; /* card quirks */ #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ @@ -282,6 +269,7 @@ struct mmc_card { #define MMC_QUIRK_TRIM_BROKEN (1<<12) /* Skip trim */ #define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */ + bool reenable_cmdq; /* Re-enable Command Queue */ unsigned int erase_size; /* erase size in sectors */ unsigned int erase_shift; /* if erase unit is power 2 */ @@ -316,247 +304,19 @@ struct mmc_card { struct dentry *debugfs_root; struct mmc_part part[MMC_NUM_PHY_PARTITION]; /* physical partitions */ unsigned int nr_parts; -}; -/* - * This function fill contents in mmc_part. - */ -static inline void mmc_part_add(struct mmc_card *card, unsigned int size, - unsigned int part_cfg, char *name, int idx, bool ro, - int area_type) -{ - card->part[card->nr_parts].size = size; - card->part[card->nr_parts].part_cfg = part_cfg; - sprintf(card->part[card->nr_parts].name, name, idx); - card->part[card->nr_parts].force_ro = ro; - card->part[card->nr_parts].area_type = area_type; - card->nr_parts++; -} + unsigned int bouncesz; /* Bounce buffer size */ +}; static inline bool mmc_large_sector(struct mmc_card *card) { return card->ext_csd.data_sector_size == 4096; } -/* - * The world is not perfect and supplies us with broken mmc/sdio devices. - * For at least some of these bugs we need a work-around. - */ - -struct mmc_fixup { - /* CID-specific fields. */ - const char *name; - - /* Valid revision range */ - u64 rev_start, rev_end; - - unsigned int manfid; - unsigned short oemid; - - /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */ - u16 cis_vendor, cis_device; - - /* for MMC cards */ - unsigned int ext_csd_rev; - - void (*vendor_fixup)(struct mmc_card *card, int data); - int data; -}; - -#define CID_MANFID_ANY (-1u) -#define CID_OEMID_ANY ((unsigned short) -1) -#define CID_NAME_ANY (NULL) - -#define EXT_CSD_REV_ANY (-1u) - -#define CID_MANFID_SANDISK 0x2 -#define CID_MANFID_TOSHIBA 0x11 -#define CID_MANFID_MICRON 0x13 -#define CID_MANFID_SAMSUNG 0x15 -#define CID_MANFID_KINGSTON 0x70 -#define CID_MANFID_HYNIX 0x90 - -#define END_FIXUP { NULL } - -#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ - _cis_vendor, _cis_device, \ - _fixup, _data, _ext_csd_rev) \ - { \ - .name = (_name), \ - .manfid = (_manfid), \ - .oemid = (_oemid), \ - .rev_start = (_rev_start), \ - .rev_end = (_rev_end), \ - .cis_vendor = (_cis_vendor), \ - .cis_device = (_cis_device), \ - .vendor_fixup = (_fixup), \ - .data = (_data), \ - .ext_csd_rev = (_ext_csd_rev), \ - } - -#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \ - _fixup, _data, _ext_csd_rev) \ - _FIXUP_EXT(_name, _manfid, \ - _oemid, _rev_start, _rev_end, \ - SDIO_ANY_ID, SDIO_ANY_ID, \ - _fixup, _data, _ext_csd_rev) \ - -#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \ - MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \ - EXT_CSD_REV_ANY) - -#define MMC_FIXUP_EXT_CSD_REV(_name, _manfid, _oemid, _fixup, _data, \ - _ext_csd_rev) \ - MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \ - _ext_csd_rev) - -#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \ - _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \ - CID_OEMID_ANY, 0, -1ull, \ - _vendor, _device, \ - _fixup, _data, EXT_CSD_REV_ANY) \ - -#define cid_rev(hwrev, fwrev, year, month) \ - (((u64) hwrev) << 40 | \ - ((u64) fwrev) << 32 | \ - ((u64) year) << 16 | \ - ((u64) month)) - -#define cid_rev_card(card) \ - cid_rev(card->cid.hwrev, \ - card->cid.fwrev, \ - card->cid.year, \ - card->cid.month) - -/* - * Unconditionally quirk add/remove. - */ - -static inline void __maybe_unused add_quirk(struct mmc_card *card, int data) -{ - card->quirks |= data; -} - -static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data) -{ - card->quirks &= ~data; -} +bool mmc_card_is_blockaddr(struct mmc_card *card); #define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC) #define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD) #define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) -#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) -#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) -#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) -#define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC) -#define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) -#define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS) -#define mmc_card_suspended(c) ((c)->state & MMC_STATE_SUSPENDED) - -#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) -#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) -#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) -#define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC) -#define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED) -#define mmc_card_set_doing_bkops(c) ((c)->state |= MMC_STATE_DOING_BKOPS) -#define mmc_card_clr_doing_bkops(c) ((c)->state &= ~MMC_STATE_DOING_BKOPS) -#define mmc_card_set_suspended(c) ((c)->state |= MMC_STATE_SUSPENDED) -#define mmc_card_clr_suspended(c) ((c)->state &= ~MMC_STATE_SUSPENDED) - -/* - * Quirk add/remove for MMC products. - */ - -static inline void __maybe_unused add_quirk_mmc(struct mmc_card *card, int data) -{ - if (mmc_card_mmc(card)) - card->quirks |= data; -} - -static inline void __maybe_unused remove_quirk_mmc(struct mmc_card *card, - int data) -{ - if (mmc_card_mmc(card)) - card->quirks &= ~data; -} - -/* - * Quirk add/remove for SD products. - */ - -static inline void __maybe_unused add_quirk_sd(struct mmc_card *card, int data) -{ - if (mmc_card_sd(card)) - card->quirks |= data; -} - -static inline void __maybe_unused remove_quirk_sd(struct mmc_card *card, - int data) -{ - if (mmc_card_sd(card)) - card->quirks &= ~data; -} - -static inline int mmc_card_lenient_fn0(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_LENIENT_FN0; -} - -static inline int mmc_blksz_for_byte_mode(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; -} - -static inline int mmc_card_disable_cd(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_DISABLE_CD; -} - -static inline int mmc_card_nonstd_func_interface(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_NONSTD_FUNC_IF; -} - -static inline int mmc_card_broken_byte_mode_512(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_BROKEN_BYTE_MODE_512; -} - -static inline int mmc_card_long_read_time(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_LONG_READ_TIME; -} - -static inline int mmc_card_broken_irq_polling(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_BROKEN_IRQ_POLLING; -} - -static inline int mmc_card_broken_hpi(const struct mmc_card *c) -{ - return c->quirks & MMC_QUIRK_BROKEN_HPI; -} - -#define mmc_card_name(c) ((c)->cid.prod_name) -#define mmc_card_id(c) (dev_name(&(c)->dev)) - -#define mmc_dev_to_card(d) container_of(d, struct mmc_card, dev) - -/* - * MMC device driver (e.g., Flash card, I/O card...) - */ -struct mmc_driver { - struct device_driver drv; - int (*probe)(struct mmc_card *); - void (*remove)(struct mmc_card *); - void (*shutdown)(struct mmc_card *); -}; - -extern int mmc_register_driver(struct mmc_driver *); -extern void mmc_unregister_driver(struct mmc_driver *); - -extern void mmc_fixup_device(struct mmc_card *card, - const struct mmc_fixup *table); - #endif /* LINUX_MMC_CARD_H */ diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 2b953eb8ceae..1974fcfd4284 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -8,13 +8,24 @@ #ifndef LINUX_MMC_CORE_H #define LINUX_MMC_CORE_H -#include <linux/interrupt.h> #include <linux/completion.h> +#include <linux/types.h> -struct request; struct mmc_data; struct mmc_request; +enum mmc_blk_status { + MMC_BLK_SUCCESS = 0, + MMC_BLK_PARTIAL, + MMC_BLK_CMD_ERR, + MMC_BLK_RETRY, + MMC_BLK_ABORT, + MMC_BLK_DATA_ERR, + MMC_BLK_ECC_ERR, + MMC_BLK_NOMEDIUM, + MMC_BLK_NEW_REQUEST, +}; + struct mmc_command { u32 opcode; u32 arg; @@ -111,11 +122,18 @@ struct mmc_data { unsigned int timeout_clks; /* data timeout (in clocks) */ unsigned int blksz; /* data block size */ unsigned int blocks; /* number of blocks */ + unsigned int blk_addr; /* block address */ int error; /* data error */ unsigned int flags; -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_WRITE BIT(8) +#define MMC_DATA_READ BIT(9) +/* Extra flags used by CQE */ +#define MMC_DATA_QBR BIT(10) /* CQE queue barrier*/ +#define MMC_DATA_PRIO BIT(11) /* CQE high priority */ +#define MMC_DATA_REL_WR BIT(12) /* Reliable write */ +#define MMC_DATA_DAT_TAG BIT(13) /* Tag request */ +#define MMC_DATA_FORCED_PRG BIT(14) /* Forced programming */ unsigned int bytes_xfered; @@ -142,82 +160,26 @@ struct mmc_request { /* Allow other commands during this ongoing data transfer or busy wait */ bool cap_cmd_during_tfr; + + int tag; }; struct mmc_card; struct mmc_async_req; -extern int mmc_stop_bkops(struct mmc_card *); -extern int mmc_read_bkops_status(struct mmc_card *); -extern struct mmc_async_req *mmc_start_req(struct mmc_host *, - struct mmc_async_req *, int *); -extern int mmc_interrupt_hpi(struct mmc_card *); -extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *); -extern void mmc_wait_for_req_done(struct mmc_host *host, - struct mmc_request *mrq); -extern bool mmc_is_req_done(struct mmc_host *host, struct mmc_request *mrq); -extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); -extern int mmc_app_cmd(struct mmc_host *, struct mmc_card *); -extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, - struct mmc_command *, int); -extern void mmc_start_bkops(struct mmc_card *card, bool from_exception); -extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int); -extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); -extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); - -#define MMC_ERASE_ARG 0x00000000 -#define MMC_SECURE_ERASE_ARG 0x80000000 -#define MMC_TRIM_ARG 0x00000001 -#define MMC_DISCARD_ARG 0x00000003 -#define MMC_SECURE_TRIM1_ARG 0x80000001 -#define MMC_SECURE_TRIM2_ARG 0x80008000 - -#define MMC_SECURE_ARGS 0x80000000 -#define MMC_TRIM_ARGS 0x00008001 - -extern int mmc_erase(struct mmc_card *card, unsigned int from, unsigned int nr, - unsigned int arg); -extern int mmc_can_erase(struct mmc_card *card); -extern int mmc_can_trim(struct mmc_card *card); -extern int mmc_can_discard(struct mmc_card *card); -extern int mmc_can_sanitize(struct mmc_card *card); -extern int mmc_can_secure_erase_trim(struct mmc_card *card); -extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from, - unsigned int nr); -extern unsigned int mmc_calc_max_discard(struct mmc_card *card); - -extern int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen); -extern int mmc_set_blockcount(struct mmc_card *card, unsigned int blockcount, - bool is_rel_write); -extern int mmc_hw_reset(struct mmc_host *host); -extern int mmc_can_reset(struct mmc_card *card); - -extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *); -extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int); - -extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort); -extern void mmc_release_host(struct mmc_host *host); - -extern void mmc_get_card(struct mmc_card *card); -extern void mmc_put_card(struct mmc_card *card); - -extern int mmc_flush_cache(struct mmc_card *); - -extern int mmc_detect_card_removed(struct mmc_host *host); - -/** - * mmc_claim_host - exclusively claim a host - * @host: mmc host to claim - * - * Claim a host for a set of operations. - */ -static inline void mmc_claim_host(struct mmc_host *host) -{ - __mmc_claim_host(host, NULL); -} - -struct device_node; -extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max); -extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask); +struct mmc_async_req *mmc_start_areq(struct mmc_host *host, + struct mmc_async_req *areq, + enum mmc_blk_status *ret_stat); +void mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq); +int mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd, + int retries); + +int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq); +void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); +void mmc_cqe_post_req(struct mmc_host *host, struct mmc_request *mrq); +int mmc_cqe_recovery(struct mmc_host *host); + +int mmc_hw_reset(struct mmc_host *host); +void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card); #endif /* LINUX_MMC_CORE_H */ diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 0b2439441cc8..726f932f0661 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -10,17 +10,14 @@ #ifndef LINUX_MMC_HOST_H #define LINUX_MMC_HOST_H -#include <linux/leds.h> -#include <linux/mutex.h> -#include <linux/timer.h> #include <linux/sched.h> #include <linux/device.h> #include <linux/fault-inject.h> #include <linux/mmc/core.h> #include <linux/mmc/card.h> -#include <linux/mmc/mmc.h> #include <linux/mmc/pm.h> +#include <linux/dma-direction.h> struct mmc_ios { unsigned int clock; /* clock rate */ @@ -82,6 +79,8 @@ struct mmc_ios { bool enhanced_strobe; /* hs400es selection */ }; +struct mmc_host; + struct mmc_host_ops { /* * It is optional for the host to implement pre_req and post_req in @@ -93,8 +92,7 @@ struct mmc_host_ops { */ void (*post_req)(struct mmc_host *host, struct mmc_request *req, int err); - void (*pre_req)(struct mmc_host *host, struct mmc_request *req, - bool is_first_req); + void (*pre_req)(struct mmc_host *host, struct mmc_request *req); void (*request)(struct mmc_host *host, struct mmc_request *req); /* @@ -132,6 +130,7 @@ struct mmc_host_ops { int (*get_cd)(struct mmc_host *host); void (*enable_sdio_irq)(struct mmc_host *host, int enable); + void (*ack_sdio_irq)(struct mmc_host *host); /* optional callback for HC quirks */ void (*init_card)(struct mmc_host *host, struct mmc_card *card); @@ -163,8 +162,18 @@ struct mmc_host_ops { unsigned int direction, int blk_size); }; -struct mmc_card; -struct device; +struct mmc_cqe_ops { + int (*cqe_enable)(struct mmc_host *host, struct mmc_card *card); + void (*cqe_disable)(struct mmc_host *host); + int (*cqe_request)(struct mmc_host *host, struct mmc_request *mrq); + void (*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq); + void (*cqe_off)(struct mmc_host *host); + int (*cqe_wait_for_idle)(struct mmc_host *host); + bool (*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq, + bool *recovery_needed); + void (*cqe_recovery_start)(struct mmc_host *host); + void (*cqe_recovery_finish)(struct mmc_host *host); +}; struct mmc_async_req { /* active mmc request */ @@ -173,7 +182,7 @@ struct mmc_async_req { * Check error status of completed mmc request. * Returns 0 if success otherwise non zero. */ - int (*err_check) (struct mmc_card *, struct mmc_async_req *); + enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *); }; /** @@ -198,14 +207,12 @@ struct mmc_slot { * @is_new_req wake up reason was new request * @is_waiting_last_req mmc context waiting for single running request * @wait wait queue - * @lock lock to protect data fields */ struct mmc_context_info { bool is_done_rcv; bool is_new_req; bool is_waiting_last_req; wait_queue_head_t wait; - spinlock_t lock; }; struct regulator; @@ -267,17 +274,17 @@ struct mmc_host { #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ -#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ - /* DDR mode at 1.8V */ -#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ - /* DDR mode at 1.2V */ -#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ -#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ -#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ -#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ -#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ -#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ -#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ +#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ +#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ +#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ +#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ +#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_NO_BOUNCE_BUFF (1 << 21) /* Disable bounce buffers on host */ #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ @@ -312,7 +319,10 @@ struct mmc_host { #define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ #define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ #define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ - +#define MMC_CAP2_CD_POST (1 << 23) /* post card rescan, let client driver to start */ +#define MMC_CAP2_DDR52_3_3V (1 << 24) /* Only supprot eMMC DDR52 at 3.3v */ +#define MMC_CAP2_CQE (1 << 25) /* Has eMMC command queue engine */ +#define MMC_CAP2_CQE_DCMD (1 << 26) /* CQE can issue a direct command */ mmc_pm_flag_t pm_caps; /* supported pm features */ /* host specific block data */ @@ -366,6 +376,7 @@ struct mmc_host { unsigned int sdio_irqs; struct task_struct *sdio_irq_thread; + struct delayed_work sdio_irq_work; bool sdio_irq_pending; atomic_t sdio_irq_thread_abort; @@ -397,14 +408,26 @@ struct mmc_host { int dsr_req; /* DSR value is valid */ u32 dsr; /* optional driver stage (DSR) value */ + /* Command Queue Engine (CQE) support */ + const struct mmc_cqe_ops *cqe_ops; + void *cqe_private; + void (*cqe_recovery_notifier)(struct mmc_host *, + struct mmc_request *); + int cqe_qdepth; + bool cqe_enabled; + bool cqe_on; + unsigned long private[0] ____cacheline_aligned; }; +struct device_node; + struct mmc_host *mmc_alloc_host(int extra, struct device *); int mmc_add_host(struct mmc_host *); void mmc_remove_host(struct mmc_host *); void mmc_free_host(struct mmc_host *); int mmc_of_parse(struct mmc_host *host); +int mmc_of_parse_voltage(struct device_node *np, u32 *mask); static inline void *mmc_priv(struct mmc_host *host) { @@ -433,6 +456,7 @@ static inline void mmc_signal_sdio_irq(struct mmc_host *host) } void sdio_run_irqs(struct mmc_host *host); +void sdio_signal_irq(struct mmc_host *host); #ifdef CONFIG_REGULATOR int mmc_regulator_get_ocrmask(struct regulator *supply); @@ -460,6 +484,7 @@ static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, } #endif +u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max); int mmc_regulator_get_supply(struct mmc_host *mmc); static inline int mmc_card_is_removable(struct mmc_host *host) @@ -477,61 +502,20 @@ static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; } -static inline int mmc_host_cmd23(struct mmc_host *host) -{ - return host->caps & MMC_CAP_CMD23; -} - -static inline int mmc_boot_partition_access(struct mmc_host *host) -{ - return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); -} - -static inline int mmc_host_uhs(struct mmc_host *host) -{ - return host->caps & - (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | - MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | - MMC_CAP_UHS_DDR50); -} - -static inline int mmc_host_packed_wr(struct mmc_host *host) -{ - return host->caps2 & MMC_CAP2_PACKED_WR; -} - +/* TODO: Move to private header */ static inline int mmc_card_hs(struct mmc_card *card) { return card->host->ios.timing == MMC_TIMING_SD_HS || card->host->ios.timing == MMC_TIMING_MMC_HS; } +/* TODO: Move to private header */ static inline int mmc_card_uhs(struct mmc_card *card) { return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && card->host->ios.timing <= MMC_TIMING_UHS_DDR50; } -static inline bool mmc_card_hs200(struct mmc_card *card) -{ - return card->host->ios.timing == MMC_TIMING_MMC_HS200; -} - -static inline bool mmc_card_ddr52(struct mmc_card *card) -{ - return card->host->ios.timing == MMC_TIMING_MMC_DDR52; -} - -static inline bool mmc_card_hs400(struct mmc_card *card) -{ - return card->host->ios.timing == MMC_TIMING_MMC_HS400; -} - -static inline bool mmc_card_hs400es(struct mmc_card *card) -{ - return card->host->ios.enhanced_strobe; -} - void mmc_retune_timer_stop(struct mmc_host *host); static inline void mmc_retune_needed(struct mmc_host *host) @@ -540,13 +524,17 @@ static inline void mmc_retune_needed(struct mmc_host *host) host->need_retune = 1; } -static inline void mmc_retune_recheck(struct mmc_host *host) +static inline bool mmc_can_retune(struct mmc_host *host) +{ + return host->can_retune == 1; +} + +static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data) { - if (host->hold_retune <= 1) - host->retune_now = 1; + return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; } -void mmc_retune_pause(struct mmc_host *host); -void mmc_retune_unpause(struct mmc_host *host); +int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); +int mmc_abort_tuning(struct mmc_host *host, u32 opcode); #endif /* LINUX_MMC_HOST_H */ diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index c376209c70ef..3ffc27aaeeaf 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -24,6 +24,8 @@ #ifndef LINUX_MMC_MMC_H #define LINUX_MMC_MMC_H +#include <linux/types.h> + /* Standard MMC commands (4.1) type argument response */ /* class 1 */ #define MMC_GO_IDLE_STATE 0 /* bc */ @@ -84,6 +86,13 @@ #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ + /* class 11 */ +#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */ +#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */ +#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */ +#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */ +#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */ + static inline bool mmc_op_multi(u32 opcode) { return opcode == MMC_WRITE_MULTIPLE_BLOCK || @@ -175,50 +184,6 @@ static inline bool mmc_op_multi(u32 opcode) #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE -/* These are unpacked versions of the actual responses */ - -struct _mmc_csd { - u8 csd_structure; - u8 spec_vers; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc; - u8 read_bl_len; - u8 read_bl_partial; - u8 write_blk_misalign; - u8 read_blk_misalign; - u8 dsr_imp; - u16 c_size; - u8 vdd_r_curr_min; - u8 vdd_r_curr_max; - u8 vdd_w_curr_min; - u8 vdd_w_curr_max; - u8 c_size_mult; - union { - struct { /* MMC system specification version 3.1 */ - u8 erase_grp_size; - u8 erase_grp_mult; - } v31; - struct { /* MMC system specification version 2.2 */ - u8 sector_size; - u8 erase_grp_size; - } v22; - } erase; - u8 wp_grp_size; - u8 wp_grp_enable; - u8 default_ecc; - u8 r2w_factor; - u8 write_bl_len; - u8 write_bl_partial; - u8 file_format_grp; - u8 copy; - u8 perm_write_protect; - u8 tmp_write_protect; - u8 file_format; - u8 ecc; -}; - /* * OCR bits are mostly in host.h */ @@ -272,6 +237,7 @@ struct _mmc_csd { * EXT_CSD fields */ +#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */ #define EXT_CSD_FLUSH_CACHE 32 /* W */ #define EXT_CSD_CACHE_CTRL 33 /* R/W */ #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ @@ -331,6 +297,11 @@ struct _mmc_csd { #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ +#define EXT_CSD_PRE_EOL_INFO 267 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ +#define EXT_CSD_CMDQ_DEPTH 307 /* RO */ +#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ @@ -436,16 +407,35 @@ struct _mmc_csd { * BKOPS modes */ #define EXT_CSD_MANUAL_BKOPS_MASK 0x01 +#define EXT_CSD_AUTO_BKOPS_MASK 0x02 /* - * MMC_SWITCH access modes + * Command Queue */ +#define EXT_CSD_CMDQ_MODE_ENABLED BIT(0) +#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0) +#define EXT_CSD_CMDQ_SUPPORTED BIT(0) +/* + * MMC_SWITCH access modes + */ #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ +/* + * Erase/trim/discard + */ +#define MMC_ERASE_ARG 0x00000000 +#define MMC_SECURE_ERASE_ARG 0x80000000 +#define MMC_TRIM_ARG 0x00000001 +#define MMC_DISCARD_ARG 0x00000003 +#define MMC_SECURE_TRIM1_ARG 0x80000001 +#define MMC_SECURE_TRIM2_ARG 0x80008000 +#define MMC_SECURE_ARGS 0x80000000 +#define MMC_TRIM_ARGS 0x00008001 + #define mmc_driver_type_mask(n) (1 << (n)) #endif /* LINUX_MMC_MMC_H */ diff --git a/include/linux/mmc/pm.h b/include/linux/mmc/pm.h index 4a139204c20c..6e2d6a135c7e 100644 --- a/include/linux/mmc/pm.h +++ b/include/linux/mmc/pm.h @@ -26,5 +26,6 @@ typedef unsigned int mmc_pm_flag_t; #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */ #endif /* LINUX_MMC_PM_H */ diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 17446d3c3602..bbb9c0010cce 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -12,6 +12,8 @@ #ifndef LINUX_MMC_SDIO_H #define LINUX_MMC_SDIO_H +#include <linux/mmc/host.h> + /* SDIO commands type argument response */ #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ @@ -190,4 +192,6 @@ #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ +void mmc_sdio_force_remove(struct mmc_host *host); + #endif /* LINUX_MMC_SDIO_H */ diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h index 3e4d4f4bccd3..1d83f05891d4 100644 --- a/include/linux/mmc/sdio_ids.h +++ b/include/linux/mmc/sdio_ids.h @@ -52,6 +52,7 @@ #define SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103 #define SDIO_DEVICE_ID_MARVELL_8688WLAN 0x9104 #define SDIO_DEVICE_ID_MARVELL_8688BT 0x9105 +#define SDIO_DEVICE_ID_MARVELL_8797_F0 0x9128 #define SDIO_VENDOR_ID_SIANO 0x039a #define SDIO_DEVICE_ID_SIANO_NOVA_B0 0x0201 @@ -61,4 +62,10 @@ #define SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100 #define SDIO_DEVICE_ID_SIANO_STELLAR 0x5347 +#define SDIO_VENDOR_ID_TI 0x0097 +#define SDIO_DEVICE_ID_TI_WL1271 0x4076 + +#define SDIO_VENDOR_ID_STE 0x0020 +#define SDIO_DEVICE_ID_STE_CW1200 0x2280 + #endif /* LINUX_MMC_SDIO_IDS_H */ diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h index 3945a8c9d3cb..82f0d289f110 100644 --- a/include/linux/mmc/slot-gpio.h +++ b/include/linux/mmc/slot-gpio.h @@ -11,6 +11,9 @@ #ifndef MMC_SLOT_GPIO_H #define MMC_SLOT_GPIO_H +#include <linux/types.h> +#include <linux/irqreturn.h> + struct mmc_host; int mmc_gpio_get_ro(struct mmc_host *host); @@ -29,5 +32,6 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id, void mmc_gpio_set_cd_isr(struct mmc_host *host, irqreturn_t (*isr)(int irq, void *dev_id)); void mmc_gpiod_request_cd_irq(struct mmc_host *host); +bool mmc_can_gpio_cd(struct mmc_host *host); #endif diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b1b081..d4e63202d8a4 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -377,6 +377,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002c #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index b5b43f94f311..2ae1f8d5fa42 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -446,7 +446,7 @@ static inline void inline_map_copy_from(struct map_info *map, void *to, unsigned if (map->cached) memcpy(to, (char *)map->cached + from, len); else - memcpy_fromio(to, map->virt + from, len); + memcpy(to, map->virt + from, len); } static inline void inline_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c425c7b4c2a0..3d55de99180e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +24,7 @@ #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_MICRONO CFI_MFR_MICRON /* Original Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST @@ -31,10 +32,11 @@ /* * Note on opcode nomenclature: some opcodes have a format like - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number + * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y, and z stand for the number * of I/O lines used for the opcode, address, and data (respectively). The * FUNCTION has an optional suffix of '4', to represent an opcode which - * requires a 4-byte (32-bit) address. + * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the + * DDR mode. */ /* Flash opcodes. */ @@ -45,6 +47,9 @@ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */ +#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */ +#define SPINOR_OP_READ_1_1_8_D 0x9d /* Read data bytes (Octal Output SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ @@ -60,6 +65,7 @@ #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ @@ -78,6 +84,8 @@ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_RD_VCR 0x85 /* Read VCR register */ +#define SPINOR_OP_WR_VCR 0x81 /* Write VCR register */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ @@ -105,6 +113,9 @@ enum read_mode { SPI_NOR_FAST, SPI_NOR_DUAL, SPI_NOR_QUAD, + SPI_NOR_DDR_QUAD, + SPI_NOR_OCTAL, + SPI_NOR_DDR_OCTAL, }; #define SPI_NOR_MAX_CMD_SIZE 8 diff --git a/include/linux/mx8_mu.h b/include/linux/mx8_mu.h new file mode 100644 index 000000000000..a26d2c6f9b17 --- /dev/null +++ b/include/linux/mx8_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MU_ATR0_OFFSET1 0x0 +#define MU_ARR0_OFFSET1 0x10 +#define MU_ASR_OFFSET1 0x20 +#define MU_ACR_OFFSET1 0x24 + +/* Registers offsets of the MU Version 1.0 */ +#define MU_V10_VER_OFFSET1 0x0 +#define MU_V10_ATR0_OFFSET1 0x20 +#define MU_V10_ARR0_OFFSET1 0x40 +#define MU_V10_ASR_OFFSET1 0x60 +#define MU_V10_ACR_OFFSET1 0x64 +#define MU_VER_ID_V10 0x0100 /* Version 1.0 */ + +#define MU_TR_COUNT1 4 +#define MU_RR_COUNT1 4 + +#define MU_CR_GIEn_MASK1 (0xF << 28) +#define MU_CR_RIEn_MASK1 (0xF << 24) +#define MU_CR_TIEn_MASK1 (0xF << 20) +#define MU_CR_GIRn_MASK1 (0xF << 16) +#define MU_CR_NMI_MASK1 (1 << 3) +#define MU_CR_Fn_MASK1 0x7 + +#define MU_SR_TE0_MASK1 (1 << 23) +#define MU_SR_RF0_MASK1 (1 << 27) +#define MU_CR_RIE0_MASK1 (1 << 27) +#define MU_CR_GIE0_MASK1 (1 << 31) + +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + + +void MU_Init(void __iomem *base); +void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg); +void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg); +void MU_EnableGeneralInt(void __iomem *base, uint32_t index); +void MU_EnableRxFullInt(void __iomem *base, uint32_t index); +uint32_t MU_ReadStatus(void __iomem *base); +int32_t MU_SetFn(void __iomem *base, uint32_t Fn); + diff --git a/include/linux/mxc_dcic.h b/include/linux/mxc_dcic.h new file mode 100644 index 000000000000..8e330bd466da --- /dev/null +++ b/include/linux/mxc_dcic.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file linux/mxc_dcic.h + * + * @brief Global header file for the MXC DCIC driver + * + * @ingroup MXC DCIC + */ + +#ifndef __LINUX_DCIC_H__ +#define __LINUX_DCIC_H__ + +#include <uapi/linux/mxc_dcic.h> + +#define DCICC_IC_ENABLE 0x1 +#define DCICC_IC_DISABLE 0x0 +#define DCICC_IC_MASK 0x1 +#define DCICC_DE_ACTIVE_HIGH 0 +#define DCICC_DE_ACTIVE_LOW (0x1 << 4) +#define DCICC_DE_ACTIVE_MASK (0x1 << 4) +#define DCICC_HSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5) +#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5) +#define DCICC_VSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6) +#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6) +#define DCICC_CLK_POL_NO_INVERTED 0 +#define DCICC_CLK_POL_INVERTED (0x1 << 7) +#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7) + +#define DCICIC_ERROR_INT_DISABLE 1 +#define DCICIC_ERROR_INT_ENABLE 0 +#define DCICIC_ERROR_INT_MASK_MASK 1 +#define DCICIC_FUN_INT_DISABLE (0x1 << 1) +#define DCICIC_FUN_INT_ENABLE 0 +#define DCICIC_FUN_INT_MASK (0x1 << 1) +#define DCICIC_FREEZE_MASK_CHANGED 0 +#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3) +#define DCICIC_FREEZE_MASK_MASK (0x1 << 3) +#define DCICIC_EXT_SIG_EX_DISABLE 0 +#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16) +#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16) + +#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF +#define DCICS_EI_STAT_PENDING (0x1 << 16) +#define DCICS_EI_STAT_NO_PENDING 0 +#define DCICS_FI_STAT_PENDING (0x1 << 17) +#define DCICS_FI_STAT_NO_PENDING 0 + +#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF +#define DCICRC_ROI_START_OFFSET_X_SHIFT 0 +#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16 +#define DCICRC_ROI_CHANGED 0 +#define DCICRC_ROI_FROZEN (0x1 << 30) +#define DCICRC_ROI_ENABLE (0x1 << 31) +#define DCICRC_ROI_DISABLE 0 + +#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF +#define DCICRS_ROI_END_OFFSET_X_SHIFT 0 +#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16 + +struct roi_regs { + u32 dcicrc; + u32 dcicrs; + u32 dcicrrs; + u32 dcicrcs; +}; + +struct dcic_regs { + u32 dcicc; + u32 dcicic; + u32 dcics; + u32 dcic_reserved; + struct roi_regs ROI[16]; +}; + +struct dcic_mux { + char dcic[16]; + u32 val; +}; + +struct bus_mux { + char name[16]; + int reg; + int shift; + int mask; + int dcic_mux_num; + const struct dcic_mux *dcics; +}; + +struct dcic_info { + int bus_mux_num; + const struct bus_mux *buses; +}; + +struct dcic_data { + struct regmap *regmap; + struct device *dev; + struct dcic_regs *regs; + const struct bus_mux *buses; + u32 bus_n; + u32 mux_n; + struct clk *disp_axi_clk; + struct clk *dcic_clk; + struct mutex lock; + struct completion roi_crc_comp; + struct class *class; + int major; + struct cdev cdev; /* Char device structure */ + dev_t devt; + unsigned int result; +}; +#endif diff --git a/include/linux/mxc_mlb.h b/include/linux/mxc_mlb.h new file mode 100644 index 000000000000..d7c792a2bee4 --- /dev/null +++ b/include/linux/mxc_mlb.h @@ -0,0 +1,55 @@ +/* + * mxc_mlb.h + * + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_MLB_H +#define _MXC_MLB_H + +/* define IOCTL command */ +#define MLB_DBG_RUNTIME _IO('S', 0x09) +#define MLB_SET_FPS _IOW('S', 0x10, unsigned int) +#define MLB_GET_VER _IOR('S', 0x11, unsigned long) +#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char) + +/*! + * set channel address for each logical channel + * the MSB 16bits is for tx channel, the left LSB is for rx channel + */ +#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int) +#define MLB_CHAN_STARTUP _IO('S', 0x14) +#define MLB_CHAN_SHUTDOWN _IO('S', 0x15) +#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long) + +#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17) +#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18) +#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int) +#define MLB_IRQ_ENABLE _IO('S', 0x20) +#define MLB_IRQ_DISABLE _IO('S', 0x21) + +/*! + * MLB event define + */ +enum { + MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0, + MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1, + MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8, + MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9, + MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16, + MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17, + MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24, + MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25, +}; + + +#endif /* _MXC_MLB_H */ diff --git a/include/linux/mxc_sim_interface.h b/include/linux/mxc_sim_interface.h new file mode 100644 index 000000000000..5eae53a59075 --- /dev/null +++ b/include/linux/mxc_sim_interface.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef MXC_SIM_INTERFACE_H +#define MXC_SIM_INTERFACE_H + +#define SIM_ATR_LENGTH_MAX 32 + +/* Raw ATR SIM_IOCTL_GET_ATR */ +typedef struct { + unsigned int size;/* length of ATR received */ + unsigned char *atr_buffer;/* raw ATR string received */ + int errval;/* The error vale reported to user space after completing ATR*/ +} sim_atr_t; + +/* ISO7816-3 protocols */ +#define SIM_PROTOCOL_T0 1 +#define SIM_PROTOCOL_T1 2 + +/* Transfer types for SIM_IOCTL_XFER */ +#define SIM_XFER_TYPE_TPDU 1 +#define SIM_XFER_TYPE_PTS 2 + +typedef struct { + unsigned int wwt; + unsigned int cwt; + unsigned int bwt; + unsigned int bgt; + unsigned int cgt; +} sim_timing_t; + +/* Transfer data for SIM_IOCTL_XFER */ +typedef struct { + unsigned char *xmt_buffer; /* transmit buffer pointer */ + int xmt_length;/* transmit buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after completing transmitting*/ +} sim_xmt_t; + +typedef struct { + unsigned char *rcv_buffer; /* receive buffer pointer */ + int rcv_length; /* receive buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after receiving*/ +} sim_rcv_t; + +typedef struct { + unsigned char di; + unsigned char fi; +} sim_baud_t; + +/* Interface power states */ +#define SIM_POWER_OFF (0) +#define SIM_POWER_ON (1) + +/* Return values for SIM_IOCTL_GET_PRESENSE */ +#define SIM_PRESENT_REMOVED (0) +#define SIM_PRESENT_DETECTED (1) +#define SIM_PRESENT_OPERATIONAL (2) + +/* The error value */ +#define SIM_OK (0) +#define SIM_ERROR_CWT (1 << 0) +#define SIM_ERROR_BWT (1 << 1) +#define SIM_ERROR_PARITY (1 << 2) +#define SIM_ERROR_INVALID_TS (1 << 3) +#define SIM_ERROR_FRAME (1 << 4) +#define SIM_ERROR_ATR_TIMEROUT (1 << 5) +#define SIM_ERROR_NACK_THRESHOLD (1 << 6) +#define SIM_ERROR_BGT (1 << 7) +#define SIM_ERROR_ATR_DELAY (1 << 8) + +/* Return values for SIM_IOCTL_GET_ERROR */ +#define SIM_E_ACCESS (1) +#define SIM_E_TPDUSHORT (2) +#define SIM_E_PTSEMPTY (3) +#define SIM_E_INVALIDXFERTYPE (4) +#define SIM_E_INVALIDXMTLENGTH (5) +#define SIM_E_INVALIDRCVLENGTH (6) +#define SIM_E_NACK (7) +#define SIM_E_TIMEOUT (8) +#define SIM_E_NOCARD (9) +#define SIM_E_PARAM_FI_INVALID (10) +#define SIM_E_PARAM_DI_INVALID (11) +#define SIM_E_PARAM_FBYD_WITHFRACTION (12) +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 (13) +#define SIM_E_PARAM_DIVISOR_RANGE (14) +#define SIM_E_MALLOC (15) +#define SIM_E_IRQ (16) +#define SIM_E_POWERED_ON (17) +#define SIM_E_POWERED_OFF (18) + +/* ioctl encodings */ +#define SIM_IOCTL_BASE (0xc0) +#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int) +#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t) +#define SIM_IOCTL_XMT _IOR(SIM_IOCTL_BASE, 3, sim_xmt_t) +#define SIM_IOCTL_RCV _IOR(SIM_IOCTL_BASE, 4, sim_rcv_t) +#define SIM_IOCTL_ACTIVATE _IO(SIM_IOCTL_BASE, 5) +#define SIM_IOCTL_DEACTIVATE _IO(SIM_IOCTL_BASE, 6) +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 7) +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 8) +#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 9) +#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 10) +#define SIM_IOCTL_SET_PROTOCOL _IOR(SIM_IOCTL_BASE, 11, unsigned int) +#define SIM_IOCTL_SET_TIMING _IOR(SIM_IOCTL_BASE, 12, sim_timing_t) +#define SIM_IOCTL_SET_BAUD _IOR(SIM_IOCTL_BASE, 13, sim_baud_t) +#define SIM_IOCTL_WAIT _IOR(SIM_IOCTL_BASE, 14, unsigned int) + +#endif diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h new file mode 100644 index 000000000000..6d778e83ef53 --- /dev/null +++ b/include/linux/mxc_v4l2.h @@ -0,0 +1,27 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file linux/mxc_v4l2.h + * + * @brief MXC V4L2 private header file + * + * @ingroup MXC V4L2 + */ + +#ifndef __LINUX_MXC_V4L2_H__ +#define __LINUX_MXC_V4L2_H__ + +#include <uapi/linux/mxc_v4l2.h> + +#endif diff --git a/include/linux/mxc_vpu-malone.h b/include/linux/mxc_vpu-malone.h new file mode 100755 index 000000000000..4541c8733124 --- /dev/null +++ b/include/linux/mxc_vpu-malone.h @@ -0,0 +1,49 @@ +/* + * Copyright 2017 NXP + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu-malone.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_MALONE_H__ +#define __LINUX_MXC_VPU_MALONE_H__ + +#include <linux/fs.h> + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + void *cpu_addr; /* cpu address to free the dma mem */ + u64 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 5) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 7) + +#endif diff --git a/include/linux/mxc_vpu.h b/include/linux/mxc_vpu.h new file mode 100644 index 000000000000..df024698dee7 --- /dev/null +++ b/include/linux/mxc_vpu.h @@ -0,0 +1,118 @@ +/* + * Copyright 2004-2013, 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_H__ +#define __LINUX_MXC_VPU_H__ + +#include <linux/fs.h> + +struct mxc_vpu_platform_data { + bool iram_enable; + int iram_size; + void (*reset) (void); + void (*pg) (int); +}; + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) +#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13) +#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14) +#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 +#define BIT_CUR_PC 0x018 +#define BIT_INT_REASON 0x174 + +#define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#ifndef CONFIG_SOC_IMX6Q +#define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h new file mode 100644 index 000000000000..67db5ee3fd11 --- /dev/null +++ b/include/linux/mxcfb.h @@ -0,0 +1,46 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/mxcfb.h + * + * @brief Global header file for the MXC Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __LINUX_MXCFB_H__ +#define __LINUX_MXCFB_H__ + +#include <uapi/linux/mxcfb.h> + +extern struct fb_videomode mxcfb_modedb[]; +extern int mxcfb_modedb_sz; + +enum { + MXC_DISP_SPEC_DEV = 0, + MXC_DISP_DDC_DEV = 1, +}; + +enum { + MXCFB_REFRESH_OFF, + MXCFB_REFRESH_AUTO, + MXCFB_REFRESH_PARTIAL, +}; + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region); +int mxc_elcdif_frame_addr_setup(dma_addr_t phys); +void mxcfb_elcdif_register_mode(const struct fb_videomode *modedb, + int num_modes, int dev_mode); + +#endif diff --git a/include/linux/mxcfb_epdc.h b/include/linux/mxcfb_epdc.h new file mode 100644 index 000000000000..35a8b83b22d3 --- /dev/null +++ b/include/linux/mxcfb_epdc.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _MXCFB_EPDC_KERNEL +#define _MXCFB_EPDC_KERNEL + +struct imx_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct imx_epdc_fb_platform_data { + struct imx_epdc_fb_mode *epdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +#endif diff --git a/include/linux/of.h b/include/linux/of.h index a19cc85b9373..15338b45ea22 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -367,6 +367,7 @@ extern int of_phandle_iterator_args(struct of_phandle_iterator *it, extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)); extern int of_alias_get_id(struct device_node *np, const char *stem); extern int of_alias_get_highest_id(const char *stem); +extern int of_alias_max_index(const char *stem); extern int of_machine_is_compatible(const char *compat); @@ -791,6 +792,11 @@ static inline int of_alias_get_highest_id(const char *stem) return -ENOSYS; } +static inline int of_alias_max_index(const char *stem) +{ + return -ENODEV; +} + static inline int of_machine_is_compatible(const char *compat) { return 0; diff --git a/include/linux/of_reserved_mem.h b/include/linux/of_reserved_mem.h index f8e1992d6423..4cd75fcf6c78 100644 --- a/include/linux/of_reserved_mem.h +++ b/include/linux/of_reserved_mem.h @@ -34,13 +34,13 @@ int of_reserved_mem_device_init_by_idx(struct device *dev, struct device_node *np, int idx); void of_reserved_mem_device_release(struct device *dev); -int early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, +int early_init_dt_alloc_reserved_memory_arch(unsigned long node, + phys_addr_t size, phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap, phys_addr_t *res_base); - void fdt_init_reserved_mem(void); void fdt_reserved_mem_save_node(unsigned long node, const char *uname, phys_addr_t base, phys_addr_t size); diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index e19efac11d13..92a9a9572b38 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -63,5 +63,6 @@ extern struct pci_ecam_ops pci_generic_ecam_ops; /* for DT-based PCI controllers that support ECAM */ int pci_host_common_probe(struct platform_device *pdev, struct pci_ecam_ops *ops); +int pci_host_common_remove(struct platform_device *pdev); #endif #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 534cb43e8635..4366eb3424e8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1442,12 +1442,10 @@ void pci_cfg_access_unlock(struct pci_dev *dev); */ #ifdef CONFIG_PCI_DOMAINS extern int pci_domains_supported; -int pci_get_new_domain_nr(void); #else enum { pci_domains_supported = 0 }; static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #endif /* CONFIG_PCI_DOMAINS */ /* @@ -1603,7 +1601,6 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #define dev_is_pci(d) (false) #define dev_is_pf(d) (false) diff --git a/include/linux/phy.h b/include/linux/phy.h index 867110c9d707..a652e86b1bdb 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -799,6 +799,7 @@ void phy_attached_info(struct phy_device *phydev); int genphy_config_init(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); +int genphy_config_aneg_check(struct phy_device *phydev); int genphy_config_aneg(struct phy_device *phydev); int genphy_aneg_done(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); @@ -833,6 +834,7 @@ void phy_print_status(struct phy_device *phydev); void phy_device_free(struct phy_device *phydev); int phy_set_max_speed(struct phy_device *phydev, u32 max_speed); +int phy_scan_fixups(struct phy_device *phydev); int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, int (*run)(struct phy_device *)); int phy_register_fixup_for_id(const char *bus_id, diff --git a/include/linux/phy/phy-mixel-lvds-combo.h b/include/linux/phy/phy-mixel-lvds-combo.h new file mode 100644 index 000000000000..9eac98c42829 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds-combo.h @@ -0,0 +1,38 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_COMBO_H_ +#define PHY_MIXEL_LVDS_COMBO_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS_COMBO) +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate); +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate) +{ +} +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_COMBO_H_ */ diff --git a/include/linux/phy/phy-mixel-lvds.h b/include/linux/phy/phy-mixel-lvds.h new file mode 100644 index 000000000000..3540857b7a65 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds.h @@ -0,0 +1,36 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_H_ +#define PHY_MIXEL_LVDS_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS) +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate); +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate) +{ +} +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_H_ */ diff --git a/include/linux/phy/phy-mixel-mipi-dsi.h b/include/linux/phy/phy-mixel-mipi-dsi.h new file mode 100644 index 000000000000..a76eea4d2704 --- /dev/null +++ b/include/linux/phy/phy-mixel-mipi-dsi.h @@ -0,0 +1,35 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_MIPI_DSI_H_ +#define PHY_MIXEL_MIPI_DSI_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_MIPI_DSI) +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match); +#else +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match) +{ + return -ENODEV; +} +#endif + +#endif /* PHY_MIXEL_MIPI_DSI_H_ */ diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h index 2d08816720f6..3ecbf2fac02c 100644 --- a/include/linux/platform_data/dma-imx-sdma.h +++ b/include/linux/platform_data/dma-imx-sdma.h @@ -50,7 +50,12 @@ struct sdma_script_start_addrs { /* End of v2 array */ s32 zcanfd_2_mcu_addr; s32 zqspi_2_mcu_addr; + s32 mcu_2_ecspi_addr; /* End of v3 array */ + s32 mcu_2_zqspi_addr; + s32 mcu_2_sai_addr; + s32 sai_2_mcu_addr; + /* End of v4 array */ }; /** diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h index 7d964e787299..59e34a321da4 100644 --- a/include/linux/platform_data/dma-imx.h +++ b/include/linux/platform_data/dma-imx.h @@ -1,5 +1,6 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -42,6 +43,8 @@ enum sdma_peripheral_type { IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */ IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_SAI, /* SAI */ + IMX_DMATYPE_HDMI, /* HDMI Audio */ + IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */ }; enum imx_dma_prio { @@ -55,6 +58,10 @@ struct imx_dma_data { int dma_request2; /* secondary DMA request line */ enum sdma_peripheral_type peripheral_type; int priority; + bool src_dualfifo; + bool dst_dualfifo; + int idx; + int done_sel; }; static inline int imx_dma_is_ipu(struct dma_chan *chan) @@ -62,6 +69,11 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan) return !strcmp(dev_name(chan->device->dev), "ipu-core"); } +static inline int imx_dma_is_pxp(struct dma_chan *chan) +{ + return strstr(dev_name(chan->device->dev), "pxp") != NULL; +} + static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { return !strcmp(chan->device->dev->driver->name, "imx-sdma") || diff --git a/include/linux/platform_data/mmc-esdhc-imx.h b/include/linux/platform_data/mmc-esdhc-imx.h index 7daa78a2f342..4ddb21718356 100644 --- a/include/linux/platform_data/mmc-esdhc-imx.h +++ b/include/linux/platform_data/mmc-esdhc-imx.h @@ -47,5 +47,6 @@ struct esdhc_platform_data { unsigned int delay_line; unsigned int tuning_step; /* The delay cell steps in tuning procedure */ unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ + unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/include/linux/platform_data/mmc-mxcmmc.h b/include/linux/platform_data/mmc-mxcmmc.h index 29115f405af9..b0fdaa9bd185 100644 --- a/include/linux/platform_data/mmc-mxcmmc.h +++ b/include/linux/platform_data/mmc-mxcmmc.h @@ -1,6 +1,7 @@ #ifndef ASMARM_ARCH_MMC_H #define ASMARM_ARCH_MMC_H +#include <linux/interrupt.h> #include <linux/mmc/host.h> struct device; diff --git a/include/linux/pm.h b/include/linux/pm.h index 06eb353182ab..721a70241fcd 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -559,6 +559,7 @@ struct dev_pm_info { pm_message_t power_state; unsigned int can_wakeup:1; unsigned int async_suspend:1; + bool in_dpm_list:1; /* Owned by the PM core */ bool is_prepared:1; /* Owned by the PM core */ bool is_suspended:1; /* Ditto */ bool is_noirq_suspended:1; diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index a09fe5c009c8..ee6776b6feb7 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -73,7 +73,7 @@ struct generic_pm_domain { struct genpd_power_state states[GENPD_MAX_NUM_STATES]; unsigned int state_count; /* number of states */ unsigned int state_idx; /* state that genpd will go to when off */ - + unsigned int state_idx_saved; /* saved power state for recovery after system suspend/resume */ }; static inline struct generic_pm_domain *pd_to_genpd(struct dev_pm_domain *pd) @@ -207,6 +207,8 @@ extern int of_genpd_add_subdomain(struct of_phandle_args *parent, extern struct generic_pm_domain *of_genpd_remove_last(struct device_node *np); int genpd_dev_pm_attach(struct device *dev); +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec); #else /* !CONFIG_PM_GENERIC_DOMAINS_OF */ static inline int of_genpd_add_provider_simple(struct device_node *np, struct generic_pm_domain *genpd) @@ -244,6 +246,13 @@ struct generic_pm_domain *of_genpd_remove_last(struct device_node *np) { return ERR_PTR(-ENOTSUPP); } + +static inline +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec) +{ + return ERR_PTR(-ENOTSUPP); +} #endif /* CONFIG_PM_GENERIC_DOMAINS_OF */ #ifdef CONFIG_PM diff --git a/include/linux/pmic_status.h b/include/linux/pmic_status.h new file mode 100644 index 000000000000..a127c7117e13 --- /dev/null +++ b/include/linux/pmic_status.h @@ -0,0 +1,82 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__ +#define __ASM_ARCH_MXC_PMIC_STATUS_H__ +#include <asm-generic/errno-base.h> +#ifdef __KERNEL__ +#include <asm/uaccess.h> /* copy_{from,to}_user() */ +#endif +/*! + * @file arch-mxc/pmic_status.h + * @brief PMIC APIs return code definition. + * + * @ingroup PMIC_CORE + */ + +/*! + * @enum PMIC_STATUS + * @brief Define return values for all PMIC APIs. + * + * These return values are used by all of the PMIC APIs. + * + * @ingroup PMIC + */ +typedef enum { + PMIC_SUCCESS = 0, /*!< The requested operation was successfully + completed. */ + PMIC_ERROR = -1, /*!< The requested operation could not be completed + due to an error. */ + PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because + one or more of the parameters was + invalid. */ + PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be + completed because the PMIC hardware + does not support it. */ + PMIC_SYSTEM_ERROR_EINTR = -EINTR, + + PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */ + PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */ + PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */ + PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */ + PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be + completed because there are too many + PMIC client requests */ +} PMIC_STATUS; + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Macros implementing error handling + */ +#define CHECK_ERROR(a) \ +do { \ + int ret = (a); \ + if (ret != PMIC_SUCCESS) \ + return ret; \ +} while (0) + +#define CHECK_ERROR_KFREE(func, freeptrs) \ +do { \ + int ret = (func); \ + if (ret != PMIC_SUCCESS) { \ + freeptrs; \ + return ret; \ + } \ +} while (0); + +#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */ diff --git a/include/linux/power/sabresd_battery.h b/include/linux/power/sabresd_battery.h new file mode 100644 index 000000000000..10bfa4588864 --- /dev/null +++ b/include/linux/power/sabresd_battery.h @@ -0,0 +1,65 @@ +/* + * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * Based on max8903_charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MAX8903_SABRESD_H__ +#define __MAX8903_SABRESD_H__ + +struct max8903_pdata { + /* + * GPIOs + * cen, chg, flt, and usus are optional. + * dok, dcm, and uok are not optional depending on the status of + * dc_valid and usb_valid. + */ + int cen; /* Charger Enable input */ + int dok; /* DC(Adapter) Power OK output */ + int uok; /* USB Power OK output */ + int chg; /* Charger status output */ + int flt; /* Fault output */ + int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */ + int usus; /* USB Suspend Input (1: suspended) */ + int feature_flag;/* battery capacity feature(0:enable, 1:disable) */ + + /* + * DCM wired to Logic High Set this true when DCM pin connect to + * Logic high. + */ + bool dcm_always_high; + + /* + * DC(Adapter/TA) is wired + * When dc_valid is true, + * dok and dcm should be valid. + * + * At least one of dc_valid or usb_valid should be true. + */ + bool dc_valid; + /* + * USB is wired + * When usb_valid is true, + * uok should be valid. + */ + bool usb_valid; +}; + +#endif /* __SABRESD_BATTERY_H__ */ diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h index efdd9227a49c..3619c9a260b6 100644 --- a/include/linux/pwm_backlight.h +++ b/include/linux/pwm_backlight.h @@ -20,6 +20,7 @@ struct platform_pwm_backlight_data { void (*notify_after)(struct device *dev, int brightness); void (*exit)(struct device *dev); int (*check_fb)(struct device *dev, struct fb_info *info); + char fb_id[16]; }; #endif diff --git a/include/linux/pxp_device.h b/include/linux/pxp_device.h new file mode 100644 index 000000000000..df185c49d017 --- /dev/null +++ b/include/linux/pxp_device.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DEVICE +#define _PXP_DEVICE + +#include <linux/idr.h> +#include <linux/hash.h> +#include <uapi/linux/pxp_device.h> + +struct pxp_irq_info { + wait_queue_head_t waitq; + atomic_t irq_pending; + int hist_status; +}; + +struct pxp_buffer_hash { + struct hlist_head *hash_table; + u32 order; + spinlock_t hash_lock; +}; + +struct pxp_buf_obj { + uint32_t handle; + + uint32_t size; + uint32_t mem_type; + + unsigned long offset; + void *virtual; + + struct hlist_node item; +}; + +struct pxp_chan_obj { + uint32_t handle; + struct dma_chan *chan; +}; + +/* File private data */ +struct pxp_file { + struct file *filp; + + /* record allocated dma buffer */ + struct idr buffer_idr; + spinlock_t buffer_lock; + + /* record allocated dma channel */ + struct idr channel_idr; + spinlock_t channel_lock; +}; + +#endif diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h new file mode 100644 index 000000000000..a48871caebfc --- /dev/null +++ b/include/linux/pxp_dma.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DMA +#define _PXP_DMA + +#include <uapi/linux/pxp_dma.h> + +struct pxp_tx_desc { + struct dma_async_tx_descriptor txd; + struct list_head tx_list; + struct list_head list; + int len; + union { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; + struct pxp_layer_param ol_param; + struct pxp_layer_param processing_param; + } layer_param; + struct pxp_proc_data proc_data; + + u32 hist_status; /* Histogram output status */ + + struct pxp_tx_desc *next; +}; + +struct pxp_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + enum pxp_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct pxp_tx_desc *desc; /* allocated tx-descriptors */ + struct list_head active_list; /* active tx-descriptors */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + struct list_head list; /* track queued channel number */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) + +void pxp_txd_ack(struct dma_async_tx_descriptor *txd, + struct pxp_channel *pxp_chan); + +#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE +int register_pxp_device(void); +void unregister_pxp_device(void); +#else +static int register_pxp_device(void) { return 0; } +static void unregister_pxp_device(void) {} +#endif +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch); + +void m4_process(void); +#endif diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index 692108222271..ce63a80679d1 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -119,6 +119,9 @@ struct regmap; #define REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE 0x200 #define REGULATOR_EVENT_PRE_DISABLE 0x400 #define REGULATOR_EVENT_ABORT_DISABLE 0x800 +#define REGULATOR_EVENT_PRE_DO_ENABLE 0x1000 +#define REGULATOR_EVENT_PRE_DO_DISABLE 0x2000 +#define REGULATOR_EVENT_AFT_DO_ENABLE 0x4000 /** * struct pre_voltage_change_data - Data sent with PRE_VOLTAGE_CHANGE event diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h index 48918be649d4..ba4ac009d832 100644 --- a/include/linux/regulator/fixed.h +++ b/include/linux/regulator/fixed.h @@ -51,6 +51,7 @@ struct fixed_voltage_config { int microvolts; int gpio; unsigned startup_delay; + unsigned off_on_delay; unsigned gpio_is_open_drain:1; unsigned enable_high:1; unsigned enabled_at_boot:1; diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index 452d393cc8dd..51c2fbdc8804 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -41,6 +41,8 @@ #include <linux/kref.h> #include <linux/mutex.h> +#define VIRTIO_RPMSG_F_NS 0 + #define RPMSG_ADDR_ANY 0xFFFFFFFF struct rpmsg_device; @@ -64,6 +66,7 @@ struct rpmsg_channel_info { * rpmsg_device - device that belong to the rpmsg bus * @dev: the device struct * @id: device id (used to match between rpmsg drivers and devices) + * @driver_override: driver name to force a match * @src: local address * @dst: destination address * @ept: the rpmsg endpoint of this channel @@ -72,6 +75,7 @@ struct rpmsg_channel_info { struct rpmsg_device { struct device dev; struct rpmsg_device_id id; + char *driver_override; u32 src; u32 dst; struct rpmsg_endpoint *ept; diff --git a/include/linux/string.h b/include/linux/string.h index 60042e5e88ff..2a9180942f03 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -136,6 +136,16 @@ static inline int strtobool(const char *s, bool *res) } int match_string(const char * const *array, size_t n, const char *string); +int __sysfs_match_string(const char * const *array, size_t n, const char *s); + +/** + * sysfs_match_string - matches given string in an array + * @_a: array of strings + * @_s: string to match with + * + * Helper for __sysfs_match_string(). Calculates the size of @a automatically. + */ +#define sysfs_match_string(_a, _s) __sysfs_match_string(_a, ARRAY_SIZE(_a), _s) #ifdef CONFIG_BINARY_PRINTF int vbin_printf(u32 *bin_buf, size_t size, const char *fmt, va_list args); diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h new file mode 100644 index 000000000000..07bd226cd5f9 --- /dev/null +++ b/include/linux/tee_drv.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015-2016, Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEE_DRV_H +#define __TEE_DRV_H + +#include <linux/types.h> +#include <linux/idr.h> +#include <linux/list.h> +#include <linux/tee.h> + +/* + * The file describes the API provided by the generic TEE driver to the + * specific TEE driver. + */ + +#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */ +#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */ +#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */ + +struct device; +struct tee_device; +struct tee_shm; +struct tee_shm_pool; + +/** + * struct tee_context - driver specific context on file pointer data + * @teedev: pointer to this drivers struct tee_device + * @list_shm: List of shared memory object owned by this context + * @data: driver specific context data, managed by the driver + */ +struct tee_context { + struct tee_device *teedev; + struct list_head list_shm; + void *data; +}; + +struct tee_param_memref { + size_t shm_offs; + size_t size; + struct tee_shm *shm; +}; + +struct tee_param_value { + u64 a; + u64 b; + u64 c; +}; + +struct tee_param { + u64 attr; + union { + struct tee_param_memref memref; + struct tee_param_value value; + } u; +}; + +/** + * struct tee_driver_ops - driver operations vtable + * @get_version: returns version of driver + * @open: called when the device file is opened + * @release: release this open file + * @open_session: open a new session + * @close_session: close a session + * @invoke_func: invoke a trusted function + * @cancel_req: request cancel of an ongoing invoke or open + * @supp_revc: called for supplicant to get a command + * @supp_send: called for supplicant to send a response + */ +struct tee_driver_ops { + void (*get_version)(struct tee_device *teedev, + struct tee_ioctl_version_data *vers); + int (*open)(struct tee_context *ctx); + void (*release)(struct tee_context *ctx); + int (*open_session)(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param); + int (*close_session)(struct tee_context *ctx, u32 session); + int (*invoke_func)(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param); + int (*cancel_req)(struct tee_context *ctx, u32 cancel_id, u32 session); + int (*supp_recv)(struct tee_context *ctx, u32 *func, u32 *num_params, + struct tee_param *param); + int (*supp_send)(struct tee_context *ctx, u32 ret, u32 num_params, + struct tee_param *param); +}; + +/** + * struct tee_desc - Describes the TEE driver to the subsystem + * @name: name of driver + * @ops: driver operations vtable + * @owner: module providing the driver + * @flags: Extra properties of driver, defined by TEE_DESC_* below + */ +#define TEE_DESC_PRIVILEGED 0x1 +struct tee_desc { + const char *name; + const struct tee_driver_ops *ops; + struct module *owner; + u32 flags; +}; + +/** + * tee_device_alloc() - Allocate a new struct tee_device instance + * @teedesc: Descriptor for this driver + * @dev: Parent device for this device + * @pool: Shared memory pool, NULL if not used + * @driver_data: Private driver data for this device + * + * Allocates a new struct tee_device instance. The device is + * removed by tee_device_unregister(). + * + * @returns a pointer to a 'struct tee_device' or an ERR_PTR on failure + */ +struct tee_device *tee_device_alloc(const struct tee_desc *teedesc, + struct device *dev, + struct tee_shm_pool *pool, + void *driver_data); + +/** + * tee_device_register() - Registers a TEE device + * @teedev: Device to register + * + * tee_device_unregister() need to be called to remove the @teedev if + * this function fails. + * + * @returns < 0 on failure + */ +int tee_device_register(struct tee_device *teedev); + +/** + * tee_device_unregister() - Removes a TEE device + * @teedev: Device to unregister + * + * This function should be called to remove the @teedev even if + * tee_device_register() hasn't been called yet. Does nothing if + * @teedev is NULL. + */ +void tee_device_unregister(struct tee_device *teedev); + +/** + * struct tee_shm_pool_mem_info - holds information needed to create a shared + * memory pool + * @vaddr: Virtual address of start of pool + * @paddr: Physical address of start of pool + * @size: Size in bytes of the pool + */ +struct tee_shm_pool_mem_info { + unsigned long vaddr; + phys_addr_t paddr; + size_t size; +}; + +/** + * tee_shm_pool_alloc_res_mem() - Create a shared memory pool from reserved + * memory range + * @priv_info: Information for driver private shared memory pool + * @dmabuf_info: Information for dma-buf shared memory pool + * + * Start and end of pools will must be page aligned. + * + * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied + * in @dmabuf, others will use the range provided by @priv. + * + * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. + */ +struct tee_shm_pool * +tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info, + struct tee_shm_pool_mem_info *dmabuf_info); + +/** + * tee_shm_pool_free() - Free a shared memory pool + * @pool: The shared memory pool to free + * + * The must be no remaining shared memory allocated from this pool when + * this function is called. + */ +void tee_shm_pool_free(struct tee_shm_pool *pool); + +/** + * tee_get_drvdata() - Return driver_data pointer + * @returns the driver_data pointer supplied to tee_register(). + */ +void *tee_get_drvdata(struct tee_device *teedev); + +/** + * tee_shm_alloc() - Allocate shared memory + * @ctx: Context that allocates the shared memory + * @size: Requested size of shared memory + * @flags: Flags setting properties for the requested shared memory. + * + * Memory allocated as global shared memory is automatically freed when the + * TEE file pointer is closed. The @flags field uses the bits defined by + * TEE_SHM_* above. TEE_SHM_MAPPED must currently always be set. If + * TEE_SHM_DMA_BUF global shared memory will be allocated and associated + * with a dma-buf handle, else driver private memory. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags); + +/** + * tee_shm_register_fd() - Register shared memory from file descriptor + * + * @ctx: Context that allocates the shared memory + * @fd: shared memory file descriptor reference. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_register_fd(struct tee_context *ctx, int fd); + +/** + * tee_shm_free() - Free shared memory + * @shm: Handle to shared memory to free + */ +void tee_shm_free(struct tee_shm *shm); + +/** + * tee_shm_put() - Decrease reference count on a shared memory handle + * @shm: Shared memory handle + */ +void tee_shm_put(struct tee_shm *shm); + +/** + * tee_shm_va2pa() - Get physical address of a virtual address + * @shm: Shared memory handle + * @va: Virtual address to tranlsate + * @pa: Returned physical address + * @returns 0 on success and < 0 on failure + */ +int tee_shm_va2pa(struct tee_shm *shm, void *va, phys_addr_t *pa); + +/** + * tee_shm_pa2va() - Get virtual address of a physical address + * @shm: Shared memory handle + * @pa: Physical address to tranlsate + * @va: Returned virtual address + * @returns 0 on success and < 0 on failure + */ +int tee_shm_pa2va(struct tee_shm *shm, phys_addr_t pa, void **va); + +/** + * tee_shm_get_va() - Get virtual address of a shared memory plus an offset + * @shm: Shared memory handle + * @offs: Offset from start of this shared memory + * @returns virtual address of the shared memory + offs if offs is within + * the bounds of this shared memory, else an ERR_PTR + */ +void *tee_shm_get_va(struct tee_shm *shm, size_t offs); + +/** + * tee_shm_get_pa() - Get physical address of a shared memory plus an offset + * @shm: Shared memory handle + * @offs: Offset from start of this shared memory + * @pa: Physical address to return + * @returns 0 if offs is within the bounds of this shared memory, else an + * error code. + */ +int tee_shm_get_pa(struct tee_shm *shm, size_t offs, phys_addr_t *pa); + +/** + * tee_shm_get_id() - Get id of a shared memory object + * @shm: Shared memory handle + * @returns id + */ +int tee_shm_get_id(struct tee_shm *shm); + +/** + * tee_shm_get_from_id() - Find shared memory object and increase reference + * count + * @ctx: Context owning the shared memory + * @id: Id of shared memory object + * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure + */ +struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); + +static inline bool tee_param_is_memref(struct tee_param *param) +{ + switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: + return true; + default: + return false; + } +} + +struct tee_context *tee_client_open_context(struct tee_context *start, + int (*match)(struct tee_ioctl_version_data *, + const void *), + const void *data, struct tee_ioctl_version_data *vers); + +void tee_client_close_context(struct tee_context *ctx); + +void tee_client_get_version(struct tee_context *ctx, + struct tee_ioctl_version_data *vers); + +int tee_client_open_session(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param); + +int tee_client_close_session(struct tee_context *ctx, u32 session); + +int tee_client_invoke_func(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param); + +#endif /*__TEE_DRV_H*/ diff --git a/include/linux/usb.h b/include/linux/usb.h index eba1f10e8cfd..48992bbb7f49 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -354,6 +354,7 @@ struct usb_devmap { */ struct usb_bus { struct device *controller; /* host/master side hardware */ + struct device *sysdev; /* as seen from firmware or bus */ int busnum; /* Bus number (in order of reg) */ const char *bus_name; /* stable id (PCI slot_name etc) */ u8 uses_dma; /* Does the host controller use DMA? */ @@ -361,6 +362,7 @@ struct usb_bus { * Does the host controller use PIO * for control transfers? */ + struct otg_fsm *otg_fsm; /* usb otg finite state machine */ u8 otg_port; /* 0, or number of OTG/HNP port */ unsigned is_b_host:1; /* true during some HNP roleswitches */ unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */ diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index f9be467d6695..c25e448f5ce3 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -12,7 +12,7 @@ struct ci_hdrc; /** * struct ci_hdrc_cable - structure for external connector cable state tracking - * @state: current state of the line + * @connected: true if cable is connected, false otherwise * @changed: set to true when extcon event happen * @enabled: set to true if we've enabled the vbus or id interrupt * @edev: device which generate events @@ -21,7 +21,7 @@ struct ci_hdrc; * @conn: used for notification registration */ struct ci_hdrc_cable { - bool state; + bool connected; bool changed; bool enabled; struct extcon_dev *edev; @@ -57,10 +57,21 @@ struct ci_hdrc_platform_data { #define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) #define CI_HDRC_OVERRIDE_TX_BURST BIT(10) #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) +#define CI_HDRC_IMX_EHCI_QUIRK BIT(12) +#define CI_HDRC_IMX_IS_HSIC BIT(13) +/* need request pmqos during low power */ +#define CI_HDRC_PMQOS BIT(14) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 - void (*notify_event) (struct ci_hdrc *ci, unsigned event); +#define CI_HDRC_CONTROLLER_VBUS_EVENT 2 +#define CI_HDRC_NOTIFY_RET_DEFER_EVENT 3 +#define CI_HDRC_CONTROLLER_CHARGER_POST_EVENT 4 +#define CI_HDRC_IMX_HSIC_ACTIVE_EVENT 5 +#define CI_HDRC_IMX_HSIC_SUSPEND_EVENT 6 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_FS 7 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_OFF 8 + int (*notify_event)(struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; struct usb_otg_caps ci_otg_caps; bool tpl_support; @@ -86,4 +97,6 @@ struct platform_device *ci_hdrc_add_device(struct device *dev, /* Remove ci hdrc device */ void ci_hdrc_remove_device(struct platform_device *pdev); +/* Get current available role */ +enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev); #endif diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 492034126876..4f5d7b25fb20 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -148,6 +148,7 @@ struct usb_hcd { unsigned rh_registered:1;/* is root hub registered? */ unsigned rh_pollable:1; /* may we poll the root hub? */ unsigned msix_enabled:1; /* driver has MSI-X enabled? */ + unsigned msi_enabled:1; /* driver has MSI enabled? */ unsigned remove_phy:1; /* auto-remove USB phy */ /* The next flag is a stopgap, to be removed when all the HCDs @@ -397,7 +398,10 @@ struct hc_driver { int (*find_raw_port_number)(struct usb_hcd *, int); /* Call for power on/off the port if necessary */ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable); - + /* Call for SINGLE_STEP_SET_FEATURE Test for USB2 EH certification */ +#define EHSET_TEST_SINGLE_STEP_SET_FEATURE 0x06 + int (*submit_single_step_set_feature)(struct usb_hcd *, + struct urb *, int); }; static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd) @@ -437,6 +441,9 @@ extern int usb_hcd_alloc_bandwidth(struct usb_device *udev, struct usb_host_interface *new_alt); extern int usb_hcd_get_frame_number(struct usb_device *udev); +struct usb_hcd *__usb_create_hcd(const struct hc_driver *driver, + struct device *sysdev, struct device *dev, const char *bus_name, + struct usb_hcd *primary_hcd); extern struct usb_hcd *usb_create_hcd(const struct hc_driver *driver, struct device *dev, const char *bus_name); extern struct usb_hcd *usb_create_shared_hcd(const struct hc_driver *driver, @@ -452,6 +459,14 @@ extern int usb_hcd_find_raw_port_number(struct usb_hcd *hcd, int port1); struct platform_device; extern void usb_hcd_platform_shutdown(struct platform_device *dev); +#ifdef CONFIG_USB_HCD_TEST_MODE +extern int ehset_single_step_set_feature(struct usb_hcd *hcd, int port); +#else +static inline int ehset_single_step_set_feature(struct usb_hcd *hcd, int port) +{ + return 0; +} +#endif /* CONFIG_USB_HCD_TEST_MODE */ #ifdef CONFIG_PCI struct pci_dev; diff --git a/include/linux/usb/otg-fsm.h b/include/linux/usb/otg-fsm.h index 7a0350535cb1..229d3649d858 100644 --- a/include/linux/usb/otg-fsm.h +++ b/include/linux/usb/otg-fsm.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. +/* Copyright (C) 2007-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -68,6 +68,10 @@ enum otg_fsm_timer { A_WAIT_ENUM, B_DATA_PLS, B_SSEND_SRP, + A_DP_END, + A_TST_MAINT, + B_SRP_REQD, + B_TST_SUSP, NUM_OTG_FSM_TIMERS, }; @@ -185,6 +189,13 @@ struct otg_fsm { int b_srp_done; int b_hnp_enable; int a_clr_err; + int hnp_polling; + + /* OTG test device */ + int tst_maint; + int otg_vbus_off; + int otg_srp_reqd; + int otg_hnp_reqd; /* Informative variables. All unused as of now */ int a_bus_drop_inf; diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index 31a8068c42a5..cfc463c30b1f 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -60,6 +60,13 @@ enum usb_otg_state { OTG_STATE_A_VBUS_ERR, }; +/* The usb role of phy to be working with */ +enum usb_current_mode { + USB_MODE_NONE, + USB_MODE_HOST, + USB_MODE_DEVICE, +}; + struct usb_phy; struct usb_otg; @@ -122,6 +129,14 @@ struct usb_phy { enum usb_device_speed speed); int (*notify_disconnect)(struct usb_phy *x, enum usb_device_speed speed); + int (*notify_suspend)(struct usb_phy *x, + enum usb_device_speed speed); + int (*notify_resume)(struct usb_phy *x, + enum usb_device_speed speed); + + int (*set_mode)(struct usb_phy *x, + enum usb_current_mode mode); + }; /** @@ -196,6 +211,15 @@ usb_phy_vbus_off(struct usb_phy *x) return x->set_vbus(x, false); } +static inline int +usb_phy_set_mode(struct usb_phy *x, enum usb_current_mode mode) +{ + if (!x || !x->set_mode) + return 0; + + return x->set_mode(x, mode); +} + /* for usb host and peripheral controller drivers */ #if IS_ENABLED(CONFIG_USB_PHY) extern struct usb_phy *usb_get_phy(enum usb_phy_type type); @@ -310,6 +334,24 @@ usb_phy_notify_disconnect(struct usb_phy *x, enum usb_device_speed speed) return 0; } +static inline int usb_phy_notify_suspend + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_suspend) + return x->notify_suspend(x, speed); + else + return 0; +} + +static inline int usb_phy_notify_resume + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_resume) + return x->notify_resume(x, speed); + else + return 0; +} + /* notifiers */ static inline int usb_register_notifier(struct usb_phy *x, struct notifier_block *nb) diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h new file mode 100644 index 000000000000..e54728caf44a --- /dev/null +++ b/include/linux/usb/typec.h @@ -0,0 +1,247 @@ + +#ifndef __LINUX_USB_TYPEC_H +#define __LINUX_USB_TYPEC_H + +#include <linux/types.h> + +/* XXX: Once we have a header for USB Power Delivery, this belongs there */ +#define ALTMODE_MAX_MODES 6 + +/* USB Type-C Specification releases */ +#define USB_TYPEC_REV_1_0 0x100 /* 1.0 */ +#define USB_TYPEC_REV_1_1 0x110 /* 1.1 */ +#define USB_TYPEC_REV_1_2 0x120 /* 1.2 */ + +struct typec_altmode; +struct typec_partner; +struct typec_cable; +struct typec_plug; +struct typec_port; + +struct fwnode_handle; + +enum typec_port_type { + TYPEC_PORT_DFP, + TYPEC_PORT_UFP, + TYPEC_PORT_DRP, + TYPEC_PORT_TYPE_UNKNOWN, +}; + +enum typec_plug_type { + USB_PLUG_NONE, + USB_PLUG_TYPE_A, + USB_PLUG_TYPE_B, + USB_PLUG_TYPE_C, + USB_PLUG_CAPTIVE, +}; + +enum typec_data_role { + TYPEC_DEVICE, + TYPEC_HOST, +}; + +enum typec_role { + TYPEC_SINK, + TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, +}; + +enum typec_pwr_opmode { + TYPEC_PWR_MODE_USB, + TYPEC_PWR_MODE_1_5A, + TYPEC_PWR_MODE_3_0A, + TYPEC_PWR_MODE_PD, +}; + +enum typec_accessory { + TYPEC_ACCESSORY_NONE, + TYPEC_ACCESSORY_AUDIO, + TYPEC_ACCESSORY_DEBUG, +}; + +#define TYPEC_MAX_ACCESSORY 3 + +/* + * struct usb_pd_identity - USB Power Delivery identity data + * @id_header: ID Header VDO + * @cert_stat: Cert Stat VDO + * @product: Product VDO + * + * USB power delivery Discover Identity command response data. + * + * REVISIT: This is USB Power Delivery specific information, so this structure + * probable belongs to USB Power Delivery header file once we have them. + */ +struct usb_pd_identity { + u32 id_header; + u32 cert_stat; + u32 product; +}; + +int typec_partner_set_identity(struct typec_partner *partner); +int typec_cable_set_identity(struct typec_cable *cable); + +/* + * struct typec_mode_desc - Individual Mode of an Alternate Mode + * @index: Index of the Mode within the SVID + * @vdo: VDO returned by Discover Modes USB PD command + * @desc: Optional human readable description of the mode + * @roles: Only for ports. DRP if the mode is available in both roles + * + * Description of a mode of an Alternate Mode which a connector, cable plug or + * partner supports. Every mode will have it's own sysfs group. The details are + * the VDO returned by discover modes command, description for the mode and + * active flag telling has the mode being entered or not. + */ +struct typec_mode_desc { + int index; + u32 vdo; + char *desc; + /* Only used with ports */ + enum typec_port_type roles; +}; + +/* + * struct typec_altmode_desc - USB Type-C Alternate Mode Descriptor + * @svid: Standard or Vendor ID + * @n_modes: Number of modes + * @modes: Array of modes supported by the Alternate Mode + * + * Representation of an Alternate Mode that has SVID assigned by USB-IF. The + * array of modes will list the modes of a particular SVID that are supported by + * a connector, partner of a cable plug. + */ +struct typec_altmode_desc { + u16 svid; + int n_modes; + struct typec_mode_desc modes[ALTMODE_MAX_MODES]; +}; + +struct typec_altmode +*typec_partner_register_altmode(struct typec_partner *partner, + struct typec_altmode_desc *desc); +struct typec_altmode +*typec_plug_register_altmode(struct typec_plug *plug, + struct typec_altmode_desc *desc); +struct typec_altmode +*typec_port_register_altmode(struct typec_port *port, + struct typec_altmode_desc *desc); +void typec_unregister_altmode(struct typec_altmode *altmode); + +struct typec_port *typec_altmode2port(struct typec_altmode *alt); + +void typec_altmode_update_active(struct typec_altmode *alt, int mode, + bool active); + +enum typec_plug_index { + TYPEC_PLUG_SOP_P, + TYPEC_PLUG_SOP_PP, +}; + +/* + * struct typec_plug_desc - USB Type-C Cable Plug Descriptor + * @index: SOP Prime for the plug connected to DFP and SOP Double Prime for the + * plug connected to UFP + * + * Represents USB Type-C Cable Plug. + */ +struct typec_plug_desc { + enum typec_plug_index index; +}; + +/* + * struct typec_cable_desc - USB Type-C Cable Descriptor + * @type: The plug type from USB PD Cable VDO + * @active: Is the cable active or passive + * @identity: Result of Discover Identity command + * + * Represents USB Type-C Cable attached to USB Type-C port. + */ +struct typec_cable_desc { + enum typec_plug_type type; + unsigned int active:1; + struct usb_pd_identity *identity; +}; + +/* + * struct typec_partner_desc - USB Type-C Partner Descriptor + * @usb_pd: USB Power Delivery support + * @accessory: Audio, Debug or none. + * @identity: Discover Identity command data + * + * Details about a partner that is attached to USB Type-C port. If @identity + * member exists when partner is registered, a directory named "identity" is + * created to sysfs for the partner device. + */ +struct typec_partner_desc { + unsigned int usb_pd:1; + enum typec_accessory accessory; + struct usb_pd_identity *identity; +}; + +/* + * struct typec_capability - USB Type-C Port Capabilities + * @role: DFP (Host-only), UFP (Device-only) or DRP (Dual Role) + * @revision: USB Type-C Specification release. Binary coded decimal + * @pd_revision: USB Power Delivery Specification revision if supported + * @prefer_role: Initial role preference + * @accessory: Supported Accessory Modes + * @fwnode: Optional fwnode of the port + * @try_role: Set data role preference for DRP port + * @dr_set: Set Data Role + * @pr_set: Set Power Role + * @vconn_set: Set VCONN Role + * @activate_mode: Enter/exit given Alternate Mode + * + * Static capabilities of a single USB Type-C port. + */ +struct typec_capability { + enum typec_port_type type; + u16 revision; /* 0120H = "1.2" */ + u16 pd_revision; /* 0300H = "3.0" */ + int prefer_role; + enum typec_accessory accessory[TYPEC_MAX_ACCESSORY]; + + struct fwnode_handle *fwnode; + + int (*try_role)(const struct typec_capability *, + int role); + + int (*dr_set)(const struct typec_capability *, + enum typec_data_role); + int (*pr_set)(const struct typec_capability *, + enum typec_role); + int (*vconn_set)(const struct typec_capability *, + enum typec_role); + + int (*activate_mode)(const struct typec_capability *, + int mode, int activate); +}; + +/* Specific to try_role(). Indicates the user want's to clear the preference. */ +#define TYPEC_NO_PREFERRED_ROLE (-1) + +struct typec_port *typec_register_port(struct device *parent, + const struct typec_capability *cap); +void typec_unregister_port(struct typec_port *port); + +struct typec_partner *typec_register_partner(struct typec_port *port, + struct typec_partner_desc *desc); +void typec_unregister_partner(struct typec_partner *partner); + +struct typec_cable *typec_register_cable(struct typec_port *port, + struct typec_cable_desc *desc); +void typec_unregister_cable(struct typec_cable *cable); + +struct typec_plug *typec_register_plug(struct typec_cable *cable, + struct typec_plug_desc *desc); +void typec_unregister_plug(struct typec_plug *plug); + +void typec_set_data_role(struct typec_port *port, enum typec_data_role role); +void typec_set_pwr_role(struct typec_port *port, enum typec_role role); +void typec_set_vconn_role(struct typec_port *port, enum typec_role role); +void typec_set_pwr_opmode(struct typec_port *port, enum typec_pwr_opmode mode); +enum typec_port_type typec_get_port_type(struct device *dev); +enum typec_role typec_get_power_role(struct device *dev); + +#endif /* __LINUX_USB_TYPEC_H */ diff --git a/include/linux/wakelock.h b/include/linux/wakelock.h new file mode 100644 index 000000000000..f4a698a22880 --- /dev/null +++ b/include/linux/wakelock.h @@ -0,0 +1,67 @@ +/* include/linux/wakelock.h + * + * Copyright (C) 2007-2012 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_WAKELOCK_H +#define _LINUX_WAKELOCK_H + +#include <linux/ktime.h> +#include <linux/device.h> + +/* A wake_lock prevents the system from entering suspend or other low power + * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock + * prevents a full system suspend. + */ + +enum { + WAKE_LOCK_SUSPEND, /* Prevent suspend */ + WAKE_LOCK_TYPE_COUNT +}; + +struct wake_lock { + struct wakeup_source ws; +}; + +static inline void wake_lock_init(struct wake_lock *lock, int type, + const char *name) +{ + wakeup_source_init(&lock->ws, name); +} + +static inline void wake_lock_destroy(struct wake_lock *lock) +{ + wakeup_source_trash(&lock->ws); +} + +static inline void wake_lock(struct wake_lock *lock) +{ + __pm_stay_awake(&lock->ws); +} + +static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) +{ + __pm_wakeup_event(&lock->ws, jiffies_to_msecs(timeout)); +} + +static inline void wake_unlock(struct wake_lock *lock) +{ + __pm_relax(&lock->ws); +} + +static inline int wake_lock_active(struct wake_lock *lock) +{ + return lock->ws.active; +} + +#endif |