diff options
Diffstat (limited to 'include')
159 files changed, 11453 insertions, 232 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index c13c919ab99e..f45b2a7800c4 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -455,7 +455,11 @@ struct acpi_pci_root { }; /* helper */ -acpi_handle acpi_get_child(acpi_handle, u64); +acpi_handle acpi_find_child(acpi_handle, u64, bool); +static inline acpi_handle acpi_get_child(acpi_handle handle, u64 addr) +{ + return acpi_find_child(handle, addr, false); +} int acpi_is_root_bridge(acpi_handle); struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)ACPI_HANDLE(dev)) diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index 13821c339a41..5672d7ea1fa0 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -112,7 +112,7 @@ struct mmu_gather { #define HAVE_GENERIC_MMU_GATHER -void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, bool fullmm); +void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end); void tlb_flush_mmu(struct mmu_gather *tlb); void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end); diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index eb58d2d7d971..b3b1cb24e644 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -494,7 +494,7 @@ #ifdef CONFIG_CONSTRUCTORS #define KERNEL_CTORS() . = ALIGN(8); \ VMLINUX_SYMBOL(__ctors_start) = .; \ - *(.ctors) \ + *(CONFIG_GCOV_CTORS) \ VMLINUX_SYMBOL(__ctors_end) = .; #else #define KERNEL_CTORS() diff --git a/include/linux/adt7461.h b/include/linux/adt7461.h new file mode 100644 index 000000000000..36f637ad287e --- /dev/null +++ b/include/linux/adt7461.h @@ -0,0 +1,42 @@ +/* + * include/linux/adt8461.h + * + * ADT7461, temperature monitoring device from ON Semiconductors + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_ADT7461_H +#define _LINUX_ADT7461_H + +#include <linux/types.h> + +struct adt7461_platform_data { + bool supported_hwrev; + bool ext_range; + bool therm2; + u8 conv_rate; + u8 offset; + u8 hysteresis; + u8 shutdown_ext_limit; + u8 shutdown_local_limit; + u8 throttling_ext_limit; + void (*alarm_fn)(bool raised); + int irq_gpio; +}; + +#endif /* _LINUX_ADT7461_H */ diff --git a/include/linux/backlight.h b/include/linux/backlight.h index da9a0825e007..ae0dd8f441bc 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -11,6 +11,7 @@ #include <linux/device.h> #include <linux/mutex.h> #include <linux/notifier.h> +#include <linux/list.h> /* Notes on locking: * @@ -101,6 +102,7 @@ struct backlight_device { struct notifier_block fb_notif; struct device dev; + struct list_head devices_list; }; static inline void backlight_update_status(struct backlight_device *bd) @@ -110,6 +112,7 @@ static inline void backlight_update_status(struct backlight_device *bd) bd->ops->update_status(bd); mutex_unlock(&bd->update_lock); } +extern struct backlight_device *get_backlight_device_by_name(char *name); extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, diff --git a/include/linux/bq27x00.h b/include/linux/bq27x00.h new file mode 100644 index 000000000000..b95cd2035238 --- /dev/null +++ b/include/linux/bq27x00.h @@ -0,0 +1,30 @@ +/* + * include/linux/bq27x00.h + * + * BQ27x00 battery driver + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_BQ27x00_H +#define _LINUX_BQ27x00_H + +struct bq27x00_platform_data { + int ac_persent_gpio; +}; + +#endif /* _LINUX_BQ27x00_H */ diff --git a/include/linux/ceph/decode.h b/include/linux/ceph/decode.h index 379f71508995..0442c3d800f0 100644 --- a/include/linux/ceph/decode.h +++ b/include/linux/ceph/decode.h @@ -160,11 +160,6 @@ static inline void ceph_decode_timespec(struct timespec *ts, static inline void ceph_encode_timespec(struct ceph_timespec *tv, const struct timespec *ts) { - BUG_ON(ts->tv_sec < 0); - BUG_ON(ts->tv_sec > (__kernel_time_t)U32_MAX); - BUG_ON(ts->tv_nsec < 0); - BUG_ON(ts->tv_nsec > (long)U32_MAX); - tv->tv_sec = cpu_to_le32((u32)ts->tv_sec); tv->tv_nsec = cpu_to_le32((u32)ts->tv_nsec); } diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h index 8f73d835d4d5..32a4f95d0bd7 100644 --- a/include/linux/cgroup.h +++ b/include/linux/cgroup.h @@ -647,22 +647,60 @@ static inline struct cgroup_subsys_state *cgroup_subsys_state( return cgrp->subsys[subsys_id]; } -/* - * function to get the cgroup_subsys_state which allows for extra - * rcu_dereference_check() conditions, such as locks used during the - * cgroup_subsys::attach() methods. +/** + * task_css_set_check - obtain a task's css_set with extra access conditions + * @task: the task to obtain css_set for + * @__c: extra condition expression to be passed to rcu_dereference_check() + * + * A task's css_set is RCU protected, initialized and exited while holding + * task_lock(), and can only be modified while holding both cgroup_mutex + * and task_lock() while the task is alive. This macro verifies that the + * caller is inside proper critical section and returns @task's css_set. + * + * The caller can also specify additional allowed conditions via @__c, such + * as locks used during the cgroup_subsys::attach() methods. */ #ifdef CONFIG_PROVE_RCU extern struct mutex cgroup_mutex; -#define task_subsys_state_check(task, subsys_id, __c) \ - rcu_dereference_check((task)->cgroups->subsys[(subsys_id)], \ - lockdep_is_held(&(task)->alloc_lock) || \ - lockdep_is_held(&cgroup_mutex) || (__c)) +#define task_css_set_check(task, __c) \ + rcu_dereference_check((task)->cgroups, \ + lockdep_is_held(&(task)->alloc_lock) || \ + lockdep_is_held(&cgroup_mutex) || (__c)) #else -#define task_subsys_state_check(task, subsys_id, __c) \ - rcu_dereference((task)->cgroups->subsys[(subsys_id)]) +#define task_css_set_check(task, __c) \ + rcu_dereference((task)->cgroups) #endif +/** + * task_subsys_state_check - obtain css for (task, subsys) w/ extra access conds + * @task: the target task + * @subsys_id: the target subsystem ID + * @__c: extra condition expression to be passed to rcu_dereference_check() + * + * Return the cgroup_subsys_state for the (@task, @subsys_id) pair. The + * synchronization rules are the same as task_css_set_check(). + */ +#define task_subsys_state_check(task, subsys_id, __c) \ + task_css_set_check((task), (__c))->subsys[(subsys_id)] + +/** + * task_css_set - obtain a task's css_set + * @task: the task to obtain css_set for + * + * See task_css_set_check(). + */ +static inline struct css_set *task_css_set(struct task_struct *task) +{ + return task_css_set_check(task, false); +} + +/** + * task_subsys_state - obtain css for (task, subsys) + * @task: the target task + * @subsys_id: the target subsystem ID + * + * See task_subsys_state_check(). + */ static inline struct cgroup_subsys_state * task_subsys_state(struct task_struct *task, int subsys_id) { diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 642789baec74..735a6d17571c 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -120,9 +120,58 @@ static inline void tegra_cpu_clock_resume(void) } #endif +enum tegra_clk_ex_param { + TEGRA_CLK_VI_INP_SEL, + TEGRA_CLK_DTV_INVERT, + TEGRA_CLK_NAND_PAD_DIV2_ENB, + TEGRA_CLK_PLLD_CSI_OUT_ENB, + TEGRA_CLK_PLLD_DSI_OUT_ENB, + TEGRA_CLK_PLLD_MIPI_MUX_SEL, +}; + void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); + +#ifdef CONFIG_COMMON_CLK void tegra_clocks_init(void); void tegra_clocks_apply_init_table(void); +static inline int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + return -EINVAL; +} +#else +static inline void tegra_clocks_init(void) +{} +static inline void tegra_clocks_apply_init_table(void) +{} + +struct dvfs; +struct notifier_block; + +#ifdef CONFIG_TEGRA_SILICON_PLATFORM +int tegra_dvfs_set_rate(struct clk *c, unsigned long rate); +#else +static inline int tegra_dvfs_set_rate(struct clk *c, unsigned long rate) +{ return 0; } +#endif +unsigned long clk_get_rate_all_locked(struct clk *c); +int tegra_dvfs_rail_disable_by_name(const char *reg_id); +int tegra_register_clk_rate_notifier(struct clk *c, struct notifier_block *nb); +void tegra_unregister_clk_rate_notifier( + struct clk *c, struct notifier_block *nb); +int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting); + +/** + * tegra_is_clk_enabled - get info if the clk is enabled or not + * @clk: clock source + * + * Returns refcnt. + */ +int tegra_is_clk_enabled(struct clk *clk); + +void tegra_cpu_user_cap_set(unsigned int speed_khz); + +#endif + #endif /* __LINUX_CLK_TEGRA_H_ */ diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 7279b94c01da..f6827558dc10 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -333,8 +333,7 @@ extern int clocksource_mmio_init(void __iomem *, const char *, extern int clocksource_i8253_init(void); -struct device_node; -typedef void(*clocksource_of_init_fn)(struct device_node *); +typedef void(*clocksource_of_init_fn)(); #ifdef CONFIG_CLKSRC_OF extern void clocksource_of_init(void); diff --git a/include/linux/cm3217.h b/include/linux/cm3217.h new file mode 100644 index 000000000000..29c72b58f8e7 --- /dev/null +++ b/include/linux/cm3217.h @@ -0,0 +1,59 @@ +/* include/linux/cm3217.h + * + * Copyright (C) 2011 Capella Microsystems Inc. + * Author: Frank Hsieh <pengyueh@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_CM3217_H +#define __LINUX_CM3217_H + +#define CM3217_I2C_NAME "cm3217" + +#define ALS_W_CMD1_addr (0x20 >> 1) +#define ALS_W_CMD2_addr (0x22 >> 1) +#define ALS_R_MSB_addr (0x21 >> 1) +#define ALS_R_LSB_addr (0x23 >> 1) + +#define ALS_CALIBRATED 0x6E93 + +/* cm3217 */ + +/* for ALS command 20h */ +#define CM3217_ALS_BIT5_Default_1 (1 << 5) +#define CM3217_ALS_IT_HALF_T (0 << 2) +#define CM3217_ALS_IT_1_T (1 << 2) +#define CM3217_ALS_IT_2_T (2 << 2) +#define CM3217_ALS_IT_4_T (4 << 2) +#define CM3217_ALS_WDM_DEFAULT_1 (1 << 1) +#define CM3217_ALS_SD (1 << 0) + +/* for ALS command 22h */ +#define CM3217_ALS_IT_800ms (0 << 5) +#define CM3217_ALS_IT_400ms (1 << 5) +#define CM3217_ALS_IT_266ms (2 << 5) +#define CM3217_ALS_IT_200ms (3 << 5) +#define CM3217_ALS_IT_130ms (4 << 5) +#define CM3217_ALS_IT_100ms (5 << 5) +#define CM3217_ALS_IT_80ms (6 << 5) +#define CM3217_ALS_IT_66ms (7 << 5) + +struct cm3217_platform_data { + uint16_t levels[10]; + uint16_t golden_adc; + int (*power) (int, uint8_t); /* power to the chip */ + uint16_t ALS_slave_address; +}; + +#define LS_PWR_ON (1 << 0) + +#endif diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h index 282e27028418..a5d52eea8232 100644 --- a/include/linux/cpu_cooling.h +++ b/include/linux/cpu_cooling.h @@ -41,7 +41,7 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus); */ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev); -unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int); +unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq); #else /* !CONFIG_CPU_THERMAL */ static inline struct thermal_cooling_device * cpufreq_cooling_register(const struct cpumask *clip_cpus) @@ -54,7 +54,7 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) return; } static inline -unsigned long cpufreq_cooling_get_level(unsigned int, unsigned int) +unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq) { return THERMAL_CSTATE_INVALID; } diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index a6dc4013b0c7..2f1e4a44f240 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -278,8 +278,8 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data); int cpufreq_unregister_driver(struct cpufreq_driver *driver_data); -void cpufreq_notify_transition(struct cpufreq_policy *policy, - struct cpufreq_freqs *freqs, unsigned int state); +void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state); + static inline void cpufreq_verify_within_limits(struct cpufreq_policy *policy, unsigned int min, unsigned int max) { @@ -340,6 +340,7 @@ const char *cpufreq_get_current_driver(void); int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); int cpufreq_update_policy(unsigned int cpu); bool have_governor_per_policy(void); +int cpufreq_set_gov(char *target_gov, unsigned int cpu); #ifdef CONFIG_CPU_FREQ /* query the current CPU frequency (in kHz). If zero, cpufreq couldn't detect it */ diff --git a/include/linux/cpuquiet.h b/include/linux/cpuquiet.h new file mode 100644 index 000000000000..5558c015bb50 --- /dev/null +++ b/include/linux/cpuquiet.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef _LINUX_CPUONLINE_H +#define _LINUX_CPUONLINE_H + +#include <linux/sysfs.h> +#include <linux/kobject.h> + +#define CPUQUIET_NAME_LEN 16 + +struct cpuquiet_governor { + char name[CPUQUIET_NAME_LEN]; + struct list_head governor_list; + int (*start) (void); + void (*stop) (void); + int (*store_active) (unsigned int cpu, bool active); + void (*device_free_notification) (void); + void (*device_busy_notification) (void); + struct module *owner; +}; + +struct cpuquiet_driver { + char name[CPUQUIET_NAME_LEN]; + int (*quiesence_cpu) (unsigned int cpunumber); + int (*wake_cpu) (unsigned int cpunumber); +}; + +extern int cpuquiet_register_governor(struct cpuquiet_governor *gov); +extern void cpuquiet_unregister_governor(struct cpuquiet_governor *gov); +extern int cpuquiet_quiesence_cpu(unsigned int cpunumber); +extern int cpuquiet_wake_cpu(unsigned int cpunumber); +extern int cpuquiet_register_driver(struct cpuquiet_driver *drv); +extern void cpuquiet_unregister_driver(struct cpuquiet_driver *drv); +extern int cpuquiet_add_group(struct attribute_group *attrs); +extern void cpuquiet_remove_group(struct attribute_group *attrs); +extern void cpuquiet_device_busy(void); +extern void cpuquiet_device_free(void); +int cpuquiet_kobject_init(struct kobject *kobj, struct kobj_type *type, + char *name); +extern unsigned int nr_cluster_ids; + +/* Sysfs support */ +struct cpuquiet_attribute { + struct attribute attr; + ssize_t (*show)(struct cpuquiet_attribute *attr, char *buf); + ssize_t (*store)(struct cpuquiet_attribute *attr, const char *buf, + size_t count); + /* Optional. Called after store is called */ + void (*store_callback)(struct cpuquiet_attribute *attr); + void *param; +}; + +#define CPQ_ATTRIBUTE(_name, _mode, _type, _callback) \ + static struct cpuquiet_attribute _name ## _attr = { \ + .attr = {.name = __stringify(_name), .mode = _mode }, \ + .show = show_ ## _type ## _attribute, \ + .store = store_ ## _type ## _attribute, \ + .store_callback = _callback, \ + .param = &_name, \ +} + +#define CPQ_BASIC_ATTRIBUTE(_name, _mode, _type) \ + CPQ_ATTRIBUTE(_name, _mode, _type, NULL) + +#define CPQ_ATTRIBUTE_CUSTOM(_name, _mode, _show, _store) \ + static struct cpuquiet_attribute _name ## _attr = { \ + .attr = {.name = __stringify(_name), .mode = _mode }, \ + .show = _show, \ + .store = _store \ + .store_callback = NULL, \ + .param = &_name, \ +} + + +extern ssize_t show_int_attribute(struct cpuquiet_attribute *cattr, char *buf); +extern ssize_t store_int_attribute(struct cpuquiet_attribute *cattr, + const char *buf, size_t count); +extern ssize_t show_bool_attribute(struct cpuquiet_attribute *cattr, char *buf); +extern ssize_t store_bool_attribute(struct cpuquiet_attribute *cattr, + const char *buf, size_t count); +extern ssize_t store_uint_attribute(struct cpuquiet_attribute *cattr, + const char *buf, size_t count); +extern ssize_t show_uint_attribute(struct cpuquiet_attribute *cattr, char *buf); +extern ssize_t store_ulong_attribute(struct cpuquiet_attribute *cattr, + const char *buf, size_t count); +extern ssize_t show_ulong_attribute(struct cpuquiet_attribute *cattr, + char *buf); +extern ssize_t cpuquiet_auto_sysfs_show(struct kobject *kobj, + struct attribute *attr, char *buf); +extern ssize_t cpuquiet_auto_sysfs_store(struct kobject *kobj, + struct attribute *attr, const char *buf, + size_t count); +#endif diff --git a/include/linux/edac.h b/include/linux/edac.h index 0b763276f619..5c6d7fbaf89e 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -622,7 +622,7 @@ struct edac_raw_error_desc { */ struct mem_ctl_info { struct device dev; - struct bus_type bus; + struct bus_type *bus; struct list_head link; /* for global list of mem_ctl_info structs */ @@ -742,4 +742,9 @@ struct mem_ctl_info { #endif }; +/* + * Maximum number of memory controllers in the coherent fabric. + */ +#define EDAC_MAX_MCS 16 + #endif diff --git a/include/linux/elevator.h b/include/linux/elevator.h index acd0312d46fb..306dd8cd0b6f 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -7,6 +7,7 @@ #ifdef CONFIG_BLOCK struct io_cq; +struct elevator_type; typedef int (elevator_merge_fn) (struct request_queue *, struct request **, struct bio *); @@ -35,7 +36,8 @@ typedef void (elevator_put_req_fn) (struct request *); typedef void (elevator_activate_req_fn) (struct request_queue *, struct request *); typedef void (elevator_deactivate_req_fn) (struct request_queue *, struct request *); -typedef int (elevator_init_fn) (struct request_queue *); +typedef int (elevator_init_fn) (struct request_queue *, + struct elevator_type *e); typedef void (elevator_exit_fn) (struct elevator_queue *); struct elevator_ops @@ -155,6 +157,8 @@ extern int elevator_init(struct request_queue *, char *); extern void elevator_exit(struct elevator_queue *); extern int elevator_change(struct request_queue *, const char *); extern bool elv_rq_merge_ok(struct request *, struct bio *); +extern struct elevator_queue *elevator_alloc(struct request_queue *, + struct elevator_type *); /* * Helper functions. diff --git a/include/linux/fb.h b/include/linux/fb.h index d49c60f5aa4c..183f192fb5a9 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -47,6 +47,8 @@ struct device_node; #define FB_MISC_PRIM_COLOR 1 #define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */ +#define FB_MISC_HDMI 4 /* display supports HDMI signaling */ + struct fb_chroma { __u32 redx; /* in fraction of 1024 */ __u32 greenx; @@ -726,6 +728,8 @@ extern int fb_videomode_from_videomode(const struct videomode *vm, /* drivers/video/modedb.c */ #define VESA_MODEDB_SIZE 34 +#define CEA_MODEDB_SIZE 65 +#define HDMI_EXT_MODEDB_SIZE 5 extern void fb_var_to_videomode(struct fb_videomode *mode, const struct fb_var_screeninfo *var); extern void fb_videomode_to_var(struct fb_var_screeninfo *var, @@ -778,7 +782,8 @@ struct fb_videomode { extern const char *fb_mode_option; extern const struct fb_videomode vesa_modes[]; -extern const struct fb_videomode cea_modes[64]; +extern const struct fb_videomode cea_modes[]; +extern const struct fb_videomode hdmi_ext_modes[]; struct fb_modelist { struct list_head list; diff --git a/include/linux/firewire.h b/include/linux/firewire.h index 191501afd7fb..217e4b42b7c8 100644 --- a/include/linux/firewire.h +++ b/include/linux/firewire.h @@ -434,6 +434,7 @@ struct fw_iso_context { int type; int channel; int speed; + bool drop_overflow_headers; size_t header_size; union { fw_iso_callback_t sc; diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index a82296af413f..790fc5a95117 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -104,6 +104,8 @@ struct fsl_usb2_platform_data { u32 pm_configured_flag; u32 pm_portsc; u32 pm_usbgenctrl; + + void *phy_config; }; /* Flags in fsl_usb2_mph_platform_data */ diff --git a/include/linux/ftrace_event.h b/include/linux/ftrace_event.h index 4372658c73ae..120d57a1c3a5 100644 --- a/include/linux/ftrace_event.h +++ b/include/linux/ftrace_event.h @@ -78,6 +78,11 @@ struct trace_iterator { /* trace_seq for __print_flags() and __print_symbolic() etc. */ struct trace_seq tmp_seq; + cpumask_var_t started; + + /* it's true when current open file is snapshot */ + bool snapshot; + /* The below is zeroed out in pipe_read */ struct trace_seq seq; struct trace_entry *ent; @@ -90,10 +95,7 @@ struct trace_iterator { loff_t pos; long idx; - cpumask_var_t started; - - /* it's true when current open file is snapshot */ - bool snapshot; + /* All new field here will be zeroed out in pipe_read */ }; enum trace_iter_flags { @@ -332,7 +334,7 @@ extern int trace_define_field(struct ftrace_event_call *call, const char *type, const char *name, int offset, int size, int is_signed, int filter_type); extern int trace_add_event_call(struct ftrace_event_call *call); -extern void trace_remove_event_call(struct ftrace_event_call *call); +extern int trace_remove_event_call(struct ftrace_event_call *call); #define is_signed_type(type) (((type)(-1)) < (type)1) diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h index 661d374aeb2d..590612bc1f77 100644 --- a/include/linux/genalloc.h +++ b/include/linux/genalloc.h @@ -93,7 +93,17 @@ static inline int gen_pool_add(struct gen_pool *pool, unsigned long addr, return gen_pool_add_virt(pool, addr, -1, size, nid); } extern void gen_pool_destroy(struct gen_pool *); -extern unsigned long gen_pool_alloc(struct gen_pool *, size_t); +extern unsigned long gen_pool_alloc_addr(struct gen_pool *, + size_t, unsigned long); +/** + * gen_pool_alloc - allocate special memory from the pool + * @pool: pool to allocate from + * @size: number of bytes to allocate from the pool + */ +static inline unsigned long gen_pool_alloc(struct gen_pool *pool, size_t size) +{ + return gen_pool_alloc_addr(pool, size, 0); +} extern void gen_pool_free(struct gen_pool *, unsigned long, size_t); extern void gen_pool_for_each_chunk(struct gen_pool *, void (*)(struct gen_pool *, struct gen_pool_chunk *, void *), void *); diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index a7e977ff4abf..42530dc017d0 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -26,6 +26,7 @@ struct gpio_keys_platform_data { int (*enable)(struct device *dev); void (*disable)(struct device *dev); const char *name; /* input device name */ + int (*wakeup_key)(void); }; #endif diff --git a/include/linux/gpio_scrollwheel.h b/include/linux/gpio_scrollwheel.h new file mode 100644 index 000000000000..33d17a0199ea --- /dev/null +++ b/include/linux/gpio_scrollwheel.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2010, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _GPIO_SCROLLWHEEL_H +#define _GPIO_SCROLLWHEEL_H + +#define GPIO_SCROLLWHEEL_PIN_ONOFF 0 +#define GPIO_SCROLLWHEEL_PIN_PRESS 1 +#define GPIO_SCROLLWHEEL_PIN_ROT1 2 +#define GPIO_SCROLLWHEEL_PIN_ROT2 3 +#define GPIO_SCROLLWHEEL_PIN_MAX 4 + +struct gpio_scrollwheel_button { + /* Configuration parameters */ + int pinaction; /* GPIO_SCROLLWHEEL_PIN_* */ + int gpio; + char *desc; + int active_low; + int debounce_interval; /* debounce ticks interval in msecs */ +}; + +struct gpio_scrollwheel_platform_data { + struct gpio_scrollwheel_button *buttons; + int nbuttons; + unsigned int rep:1; /* enable input subsystem auto repeat */ + int (*enable)(struct device *dev); + void (*disable)(struct device *dev); +}; + +#endif + diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 6b4890fa57e7..feaf0c7fb7d8 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -358,6 +358,17 @@ static inline int hstate_index(struct hstate *h) return h - hstates; } +pgoff_t __basepage_index(struct page *page); + +/* Return page->index in PAGE_SIZE units */ +static inline pgoff_t basepage_index(struct page *page) +{ + if (!PageCompound(page)) + return page->index; + + return __basepage_index(page); +} + #else /* CONFIG_HUGETLB_PAGE */ struct hstate {}; #define alloc_huge_page_node(h, nid) NULL @@ -378,6 +389,11 @@ static inline unsigned int pages_per_huge_page(struct hstate *h) } #define hstate_index_to_shift(index) 0 #define hstate_index(h) 0 + +static inline pgoff_t basepage_index(struct page *page) +{ + return page->index; +} #endif /* CONFIG_HUGETLB_PAGE */ #endif /* _LINUX_HUGETLB_H */ diff --git a/include/linux/i2c-algo-pca.h b/include/linux/i2c-algo-pca.h index a3c3ecd59f08..afd50a76ab3f 100644 --- a/include/linux/i2c-algo-pca.h +++ b/include/linux/i2c-algo-pca.h @@ -5,6 +5,11 @@ #define I2C_PCA_CHIP_9564 0x00 #define I2C_PCA_CHIP_9665 0x01 + +#define I2C_PCA_CHIP_9665_BUFSIZE 64 +#define I2C_PCA_BYTE_MODE 0x0 +#define I2C_PCA_BUFFERED_MODE 0x1 + /* Internal period for PCA9665 oscilator */ #define I2C_PCA_OSC_PER 3 /* e10-8s */ @@ -50,19 +55,24 @@ #define I2C_PCA_CON_STA 0x20 /* Start */ #define I2C_PCA_CON_STO 0x10 /* Stop */ #define I2C_PCA_CON_SI 0x08 /* Serial Interrupt */ +#define I2C_PCA_CON_MODE 0x01 /* Mode */ #define I2C_PCA_CON_CR 0x07 /* Clock Rate (MASK) */ struct i2c_algo_pca_data { - void *data; /* private low level data */ + void *data; /* private low level data */ void (*write_byte) (void *data, int reg, int val); int (*read_byte) (void *data, int reg); int (*wait_for_completion) (void *data); void (*reset_chip) (void *data); + void (*request_access) (void *data); + void (*release_access) (void *data); /* For PCA9564, use one of the predefined frequencies: * 330000, 288000, 217000, 146000, 88000, 59000, 44000, 36000 * For PCA9665, use the frequency you want here. */ unsigned int i2c_clock; unsigned int chip; + unsigned int mode; + unsigned int buf_size; }; int i2c_pca_add_bus(struct i2c_adapter *); diff --git a/include/linux/i2c-slave.h b/include/linux/i2c-slave.h new file mode 100755 index 000000000000..34df64f73f6f --- /dev/null +++ b/include/linux/i2c-slave.h @@ -0,0 +1,259 @@ +/* + * i2c-slave.h - definitions for the i2c-slave-bus interface + * + * Copyright (c) 2009-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* ------------------------------------------------------------------------- */ + +#ifndef _LINUX_I2C_SLAVE_H +#define _LINUX_I2C_SLAVE_H + +#include <linux/types.h> +#ifdef __KERNEL__ +/* --- General options ------------------------------------------------ */ + +struct i2c_client; +struct i2c_slave_algorithm; +struct i2c_slave_adapter; +#if defined(CONFIG_I2C_SLAVE) && defined(CONFIG_I2C) + +/** + * i2c_slave_send - Sends data to master. When master issues a read cycle, the + * data is sent by the slave. + * This function copies the client data into the slave tx buffer and return to + * client. This is not a blocking call. Data will be sent to master later once + * slave got the master-ready cycle transfer. + * if there is no sufficient space to write the client buffer, it will return + * error. it will not write partial data. + * @client: Handle to i2c-slave client. + * @buf: Data that will be written to the master + * @count: How many bytes to write. + * + * Returns negative errno, or else the number of bytes written. + */ +extern int i2c_slave_send(struct i2c_client *client, const char *buf, + int count); + +/** + * i2c_slave_get_tx_status - Get amount of data available in tx buffer. If there + * is still data in tx buffer then wait for given time to transfer complete + * for a give timeout. + * @client: Handle to i2c-slave client. + * @timeout_ms: Time to wait for transfer to complete. + * + * Returns negative errno, or else the number of bytes remaining in tx buffer. + */ +extern int i2c_slave_get_tx_status(struct i2c_client *client, int timeout_ms); + +/** + * i2c_slave_recv - Receive data from master. The data received from master is + * stored on slave rx buffer. When this api will be called, the data will be + * copied from the slave rx buffer to client buffer. If requested amount (count) + * of data is not available then it will wait for either min_count to be receive + * or timeout whatever first. + * + * if timeout_ms = 0, then wait for min_count data to be read. + * if timoue_ms non zero then wait for the data till timeout happen. + * @client: Handle to i2c-slave client. + * @buf: Data that will be read from the master + * @count: How many bytes to read. + * @min_count: Block till read min_count of data. + * @timeout_ms: Time to wait for read to be complete. + * + * Returns negative errno, or else the number of bytes read. + */ +extern int i2c_slave_recv(struct i2c_client *client, char *buf, int count, + int min_count, int timeout_ms); + +/** + * i2c_slave_start - Start the i2c slave to receive/transmit data. + * After this i2c controller starts responding master. + * The dummy-char will send to master if there is no data to send on slave tx + * buffer. + * @client: Handle to i2c-slave client. + * @dummy_char: Data which will be send to master if there is no data to be send + * in slave tx buffer. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_start(struct i2c_client *client, unsigned char dummy_char); + +/** + * i2c_slave_stop - Stop slave to receive/transmit data. + * After this i2c controller stops responding master. + * @client: Handle to i2c-slave client. + * @is_buffer_clear: Reset the tx and rx slave buffer or not. + */ +extern void i2c_slave_stop(struct i2c_client *client, int is_buffer_clear); + +/** + * i2c_slave_flush_buffer - Flush the receive and transmit buffer. + * @client: Handle to i2c-slave client. + * @is_flush_tx_buffer: Reset the tx slave buffer or not. + * @is_flush_rx_buffer: Reset the rx slave buffer or not. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_flush_buffer(struct i2c_client *client, + int is_flush_tx_buffer, int is_flush_rx_buffer); + +/** + * i2c_slave_get_nack_cycle - Get the number of master read cycle on which + * dummy char sent. This is the way to find that how much cycle slave sent the + * NACK packet. + * + * @client: Handle to i2c-slave client. + * @is_cout_reset: Reset the nack count or not. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_slave_get_nack_cycle(struct i2c_client *client, + int is_cout_reset); + + +/** + * i2c_add_slave_adapter - Add slave adapter. + * + * @slv_adap: Slave adapter. + * @force_nr: Adapter number. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_add_slave_adapter(struct i2c_slave_adapter *slv_adap, + bool force_nr); + +/** + * i2c_del_slave_adapter - Delete slave adapter. + * + * @slv_adap: Slave adapter. + * + * Returns negative errno, or else 0 for success. + */ +extern int i2c_del_slave_adapter(struct i2c_slave_adapter *slv_adap); + +#endif /* I2C_SLAVE */ + +/* + * i2c_slave_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_slave_adapter { + struct module *owner; + unsigned int id; + unsigned int class; /* classes to allow probing for */ + /* the algorithm to access the i2c-slave bus */ + const struct i2c_slave_algorithm *slv_algo; + void *algo_data; + void *parent_data; + + /* data fields that are valid for all devices */ + u8 level; /* nesting level for lockdep */ + struct mutex bus_lock; + + int timeout; /* in jiffies */ + int retries; + struct device *dev; /* the adapter device */ + struct device *parent_dev; /* the adapter device */ + + int nr; + char name[48]; + struct completion dev_released; +}; + +static inline void *i2c_get_slave_adapdata(const struct i2c_slave_adapter *dev) +{ + return dev_get_drvdata(dev->dev); +} + +static inline void i2c_set_slave_adapdata(struct i2c_slave_adapter *dev, + void *data) +{ + dev_set_drvdata(dev->dev, data); +} + +/* + * The following struct are for those who like to implement new i2c slave + * bus drivers: + * i2c_slave_algorithm is the interface to a class of hardware solutions which + * can be addressed using the same bus algorithms. + */ +struct i2c_slave_algorithm { + /* Start the slave to receive/transmit data. + * The dummy-char will send to master if there is no data to send on + * slave tx buffer. + */ + int (*slave_start)(struct i2c_slave_adapter *slv_adap, int addr, + int is_ten_bit_addr, unsigned char dummy_char); + + /* Stop slave to receive/transmit data. + * Required information to reset the slave rx and tx buffer to reset + * or not. + */ + void (*slave_stop)(struct i2c_slave_adapter *slv_adap, + int is_buffer_clear); + + /* + * Send data to master. The data will be copied on the slave tx buffer + * and will send to master once master initiates the master-read cycle. + * Function will return immediately once the buffer copied into slave + * tx buffer. + * Client will not wait till data is sent to master. + * This function will not copy data partially. If sufficient space is + * not available, it will return error. + */ + int (*slave_send)(struct i2c_slave_adapter *slv_adap, const char *buf, + int count); + + /* + * Get amount of data available in tx buffer. If there is still data in + * tx buffer wait for given time to get slave tx buffer emptied. + * returns number of data available in slave tx buffer. + */ + int (*slave_get_tx_status)(struct i2c_slave_adapter *slv_adap, + int timeout_ms); + + /* + * Receive data to master. The data received from master is stored on + * slave rx buffer. When this api will be called, the data will be + * coped from the slave rx buffer to client buffer. If requested (count) + * data is not available then it will wait for either min_count to be + * receive or timeout whatever first. + * + * if timeout_ms = 0, then wait for min_count data to be read. + * if timoue_ms non zero then wait for the data till timeout happen. + * returns number of bytes read as positive integer otherwise error. + */ + int (*slave_recv)(struct i2c_slave_adapter *slv_adap, char *buf, + int count, int min_count, int timeout_ms); + + /* Flush the receive and transmit buffer. + */ + int (*slave_flush_buffer)(struct i2c_slave_adapter *slv_adap, + int is_flush_tx_buffer, int is_flush_rx_buffer); + + /* Get the number of dummy char cycle. + * Get the number of master read cycle on which dummy character has + * been sent. + * This can be treat as NACK cycle from slave side. + * Pass option whether count need to be reset or not. + */ + int (*slave_get_nack_cycle)(struct i2c_slave_adapter *slv_adap, + int is_cout_reset); +}; +#endif /* __KERNEL__ */ +#endif /* _LINUX_I2C_SLAVE_H */ diff --git a/include/linux/i2c-tegra.h b/include/linux/i2c-tegra.h new file mode 100644 index 000000000000..ffa3a591dadb --- /dev/null +++ b/include/linux/i2c-tegra.h @@ -0,0 +1,45 @@ +/* + * drivers/i2c/busses/i2c-tegra.c + * + * Copyright (C) 2010 Google, Inc. + * Author: Colin Cross <ccross@android.com> + * + * Copyright (C) 2010-2011 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_I2C_TEGRA_H +#define _LINUX_I2C_TEGRA_H + +struct tegra_i2c_platform_data { + unsigned long bus_clk_rate; + bool is_dvc; + bool is_clkon_always; + int retries; + int timeout; /* in jiffies */ + u16 slave_addr; + int scl_gpio; + int sda_gpio; + bool is_high_speed_enable; + u16 hs_master_code; +}; + +struct tegra_i2c_slave_platform_data { + int adapter_nr; + const struct tegra_pingroup_config *pinmux; + int bus_mux_len; + unsigned long bus_clk_rate; + int max_rx_buffer_size; + int max_tx_buffer_size; +}; + +#endif /* _LINUX_I2C_TEGRA_H */ diff --git a/include/linux/i2c.h b/include/linux/i2c.h index e988fa935b3c..3999c140a941 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -548,4 +548,18 @@ extern void acpi_i2c_register_devices(struct i2c_adapter *adap); static inline void acpi_i2c_register_devices(struct i2c_adapter *adap) {} #endif +/* Bus clear logic using the GPIO */ +#ifdef CONFIG_I2C_ALGO_BUSCLEAR +int i2c_algo_busclear_gpio(struct device *dev, int scl_gpio, + int scl_gpio_flags, int sda_gpio, int sda_gpio_flags, + int max_retry_clock, int clock_speed_hz); +#else +static inline int i2c_algo_busclear_gpio(struct device *dev, int scl_gpio, + int scl_gpio_flags, int sda_gpio, int sda_gpio_flags, + int max_retry_clock, int clock_speed_hz) +{ + return -EINVAL; +} +#endif /* CONFIG_I2C_ALGO_BUSCLEAR */ + #endif /* _LINUX_I2C_H */ diff --git a/include/linux/i2c/ds90uh925q_ser.h b/include/linux/i2c/ds90uh925q_ser.h new file mode 100644 index 000000000000..7c18edcebb01 --- /dev/null +++ b/include/linux/i2c/ds90uh925q_ser.h @@ -0,0 +1,31 @@ +/* + * FPDLink Serializer driver + * + * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_DS90UH925Q_SER_H +#define __LINUX_DS90UH925Q_SER_H + +#include <linux/types.h> + +/* The platform data for the FPDLink Serializer driver */ +struct ds90uh925q_platform_data { + bool has_lvds_en_gpio; /* has GPIO to enable */ + int lvds_en_gpio; /* GPIO */ + + bool is_fpdlinkII; + bool support_hdcp; + bool clk_rise_edge; +}; + +#endif /* __LINUX_DS90UH925Q_SER_H */ diff --git a/include/linux/i2c/panjit_ts.h b/include/linux/i2c/panjit_ts.h new file mode 100644 index 000000000000..1dd51e1ecae8 --- /dev/null +++ b/include/linux/i2c/panjit_ts.h @@ -0,0 +1,30 @@ +/* + * include/linux/i2c/panjit_ts.h + * + * Copyright (c) 2010, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_I2C_PANJIT_TS_H +#define _LINUX_I2C_PANJIT_TS_H + +struct device; + +struct panjit_i2c_ts_platform_data { + int gpio_reset; +}; + +#endif diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index 637fa71de0c7..0b3498800ba0 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -79,9 +79,8 @@ static inline int is_vlan_dev(struct net_device *dev) } #define vlan_tx_tag_present(__skb) ((__skb)->vlan_tci & VLAN_TAG_PRESENT) -#define vlan_tx_nonzero_tag_present(__skb) \ - (vlan_tx_tag_present(__skb) && ((__skb)->vlan_tci & VLAN_VID_MASK)) #define vlan_tx_tag_get(__skb) ((__skb)->vlan_tci & ~VLAN_TAG_PRESENT) +#define vlan_tx_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK) #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 8d171f427632..3d35b7023591 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -211,8 +211,8 @@ struct iio_chan_spec { static inline bool iio_channel_has_info(const struct iio_chan_spec *chan, enum iio_chan_info_enum type) { - return (chan->info_mask_separate & type) | - (chan->info_mask_shared_by_type & type); + return (chan->info_mask_separate & BIT(type)) | + (chan->info_mask_shared_by_type & BIT(type)); } #define IIO_ST(si, rb, sb, sh) \ diff --git a/include/linux/ina219.h b/include/linux/ina219.h new file mode 100644 index 000000000000..de4113714c0f --- /dev/null +++ b/include/linux/ina219.h @@ -0,0 +1,40 @@ +/* + * linux/include/linux/ina219.h + * + * Copyright (c) 2011-2012, NVIDIA Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _INA219_H +#define _INA219_H + +#include <linux/types.h> + +#define INA219_RAIL_NAME_SIZE 32 + +struct ina219_platform_data { + u16 divisor; /*divisor needed to get current value */ + u32 calibration_data; + u32 power_lsb; + u32 precision_multiplier; + u16 trig_conf; + u16 cont_conf; + u32 shunt_resistor; /*mOhms*/ + char rail_name[INA219_RAIL_NAME_SIZE]; +}; + +#endif /* _LINUX_INA219_H */ + diff --git a/include/linux/ina3221.h b/include/linux/ina3221.h new file mode 100644 index 000000000000..bcabf17f0d8a --- /dev/null +++ b/include/linux/ina3221.h @@ -0,0 +1,61 @@ +/* + * include/linux/ina3221.h + * + * Copyright (c) 2012, NVIDIA Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _INA3221_H +#define _INA3221_H + +#include <linux/types.h> + +#define INA3221_CONFIG 0x00 +#define INA3221_SHUNT_VOL_CHAN1 0x01 +#define INA3221_BUS_VOL_CHAN1 0x02 +#define INA3221_SHUNT_VOL_CHAN2 0x03 +#define INA3221_BUS_VOL_CHAN2 0x04 +#define INA3221_SHUNT_VOL_CHAN3 0x05 +#define INA3221_BUS_VOL_CHAN3 0x06 +#define INA3221_MASK_ENABLE 0x0F + +#define INA3221_RESET 0x8000 +#define INA3221_POWER_DOWN 0 +#define INA3221_ENABLE_CHAN (7 << 12) /* enable all 3 channels */ +#define INA3221_AVG (3 << 9) /* 64 averages */ +#define INA3221_VBUS_CT (4 << 6) /* Vbus 1.1 mS conv time */ +#define INA3221_VSHUNT_CT (4 << 3) /* Vshunt 1.1 mS conv time */ +#define INA3221_CONT_MODE 7 /* continuous bus n shunt V measure */ +#define INA3221_TRIG_MODE 3 /* triggered bus n shunt V measure */ + +#define INA3221_CONT_CONFIG_DATA (INA3221_ENABLE_CHAN | INA3221_AVG | \ + INA3221_VBUS_CT | INA3221_VSHUNT_CT | \ + INA3221_CONT_MODE) /* 0x7727 */ + +#define INA3221_TRIG_CONFIG_DATA (INA3221_ENABLE_CHAN | \ + INA3221_TRIG_MODE) /* 0x7723 */ + +#define INA3221_NUMBER_OF_RAILS 3 +#define INA3221_RAIL_NAME_SIZE 32 + +struct ina3221_platform_data { + char rail_name[INA3221_NUMBER_OF_RAILS][INA3221_RAIL_NAME_SIZE]; + u32 shunt_resistor[INA3221_NUMBER_OF_RAILS]; /* specify in mOhms */ + u16 cont_conf_data; /* config data for continuous mode */ + u16 trig_conf_data; /* config data for triggered mode */ +}; + +#endif /* _LINUX_INA3221_H */ diff --git a/include/linux/input.h b/include/linux/input.h index 82ce323b9986..97b417065f76 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -122,6 +122,7 @@ struct input_dev { const char *name; const char *phys; const char *uniq; + bool enabled; struct input_id id; unsigned long propbit[BITS_TO_LONGS(INPUT_PROP_CNT)]; @@ -168,6 +169,8 @@ struct input_dev { void (*close)(struct input_dev *dev); int (*flush)(struct input_dev *dev, struct file *file); int (*event)(struct input_dev *dev, unsigned int type, unsigned int code, int value); + int (*enable)(struct input_dev *dev); + int (*disable)(struct input_dev *dev); struct input_handle __rcu *grab; diff --git a/include/linux/input/max77665-haptic.h b/include/linux/input/max77665-haptic.h new file mode 100644 index 000000000000..043ca189318b --- /dev/null +++ b/include/linux/input/max77665-haptic.h @@ -0,0 +1,118 @@ +/* + * MAX77665 Haptic Driver + * + * Copyright (c) 2012, NVIDIA Corporation, All Rights Reserved + * Author: Syed Rafiuddin <srafiuddin@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_INPUT_MAX77665_HAPTIC_H +#define _LINUX_INPUT_MAX77665_HAPTIC_H + +#include <linux/platform_device.h> +#include <linux/mfd/max77665.h> + +#define MAX77665_HAPTIC_REG_GENERAL 0x00 +#define MAX77665_HAPTIC_REG_CONF1 0x01 +#define MAX77665_HAPTIC_REG_CONF2 0x02 +#define MAX77665_HAPTIC_REG_DRVCONF 0x03 +#define MAX77665_HAPTIC_REG_CYCLECONF1 0x04 +#define MAX77665_HAPTIC_REG_CYCLECONF2 0x05 +#define MAX77665_HAPTIC_REG_SIGCONF1 0x06 +#define MAX77665_HAPTIC_REG_SIGCONF2 0x07 +#define MAX77665_HAPTIC_REG_SIGCONF3 0x08 +#define MAX77665_HAPTIC_REG_SIGCONF4 0x09 +#define MAX77665_HAPTIC_REG_SIGDC1 0x0a +#define MAX77665_HAPTIC_REG_SIGDC2 0x0b +#define MAX77665_HAPTIC_REG_SIGPWMDC1 0x0c +#define MAX77665_HAPTIC_REG_SIGPWMDC2 0x0d +#define MAX77665_HAPTIC_REG_SIGPWMDC3 0x0e +#define MAX77665_HAPTIC_REG_SIGPWMDC4 0x0f +#define MAX77665_HAPTIC_REG_MTR_REV 0x10 +#define MAX77665_HAPTIC_REG_END 0x11 + +#define MAX77665_PMIC_REG_LSCNFG 0x2B + +/* Haptic configuration 1 register */ +#define MAX77665_INVERT_SHIFT 7 +#define MAX77665_CONT_MODE_SHIFT 6 +#define MAX77665_MOTOR_STRT_SHIFT 3 + +/* Haptic configuration 2 register */ +#define MAX77665_MOTOR_TYPE_SHIFT 7 +#define MAX77665_ENABLE_SHIFT 6 +#define MAX77665_MODE_SHIFT 5 + +/* Haptic driver configuration register */ +#define MAX77665_CYCLE_SHIFT 6 +#define MAX77665_SIG_PERIOD_SHIFT 4 +#define MAX77665_SIG_DUTY_SHIFT 2 +#define MAX77665_PWM_DUTY_SHIFT 0 + +enum max77665_haptic_motor_type { + MAX77665_HAPTIC_ERM, + MAX77665_HAPTIC_LRA, +}; + +enum max77665_haptic_pulse_mode { + MAX77665_EXTERNAL_MODE, + MAX77665_INTERNAL_MODE, +}; + +enum max77665_haptic_pwm_divisor { + MAX77665_PWM_DIVISOR_32, + MAX77665_PWM_DIVISOR_64, + MAX77665_PWM_DIVISOR_128, + MAX77665_PWM_DIVISOR_256, +}; + +enum max77665_haptic_invert { + MAX77665_INVERT_OFF, + MAX77665_INVERT_ON, +}; + +enum max77665_haptic_continous_mode { + MAX77665_NORMAL_MODE, + MAX77665_CONT_MODE, +}; + +enum max77665_haptic_edp_states { + MAX77665_HAPTIC_EDP_HIGH, + MAX77665_HAPTIC_EDP_LOW, + MAX77665_HAPTIC_EDP_NUM_STATES, +}; + +struct max77665_haptic_platform_data { + int pwm_channel_id; + int pwm_period; + + enum max77665_haptic_motor_type type; + enum max77665_haptic_pulse_mode mode; + enum max77665_haptic_pwm_divisor pwm_divisor; + enum max77665_haptic_invert invert; + enum max77665_haptic_continous_mode cont_mode; + + int internal_mode_pattern; + int pattern_cycle; + int pattern_signal_period; + int feedback_duty_cycle; + int motor_startup_val; + int scf_val; + + unsigned int edp_states[MAX77665_HAPTIC_EDP_NUM_STATES]; +}; + +#endif diff --git a/include/linux/input/tegra_kbc.h b/include/linux/input/tegra_kbc.h new file mode 100644 index 000000000000..7ee422c46eba --- /dev/null +++ b/include/linux/input/tegra_kbc.h @@ -0,0 +1,67 @@ +/* + * Platform definitions for tegra-kbc keyboard input driver + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef ASMARM_ARCH_TEGRA_KBC_H +#define ASMARM_ARCH_TEGRA_KBC_H + +#include <linux/types.h> +#include <linux/input/matrix_keypad.h> + +#define KBC_MAX_GPIO 24 +#define KBC_MAX_KPENT 8 + +#define KBC_MAX_ROW 16 +#define KBC_MAX_COL 8 +#define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL) + +enum tegra_pin_type { + PIN_CFG_IGNORE, + PIN_CFG_COL, + PIN_CFG_ROW, +}; + +struct tegra_kbc_pin_cfg { + enum tegra_pin_type type; + unsigned char num; +}; + +struct tegra_kbc_wake_key { + u8 row:4; + u8 col:4; +}; + +struct tegra_kbc_platform_data { + unsigned int debounce_cnt; + unsigned int repeat_cnt; + unsigned int scan_count; + + unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */ + const struct tegra_kbc_wake_key *wake_cfg; + + struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; + const struct matrix_keymap_data *keymap_data; + + u32 wakeup_key; + bool wakeup; + bool use_fn_map; + bool use_ghost_filter; + bool disable_ev_rep; +}; +#endif diff --git a/include/linux/lightsensor.h b/include/linux/lightsensor.h new file mode 100644 index 000000000000..7a87853ac064 --- /dev/null +++ b/include/linux/lightsensor.h @@ -0,0 +1,28 @@ +/* include/linux/lightsensor.h + * + * Copyright (C) 2011 Capella Microsystems Inc. + * Author: Frank Hsieh <pengyueh@gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_LIGHTSENSOR_H +#define __LINUX_LIGHTSENSOR_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define LIGHTSENSOR_IOCTL_MAGIC 'l' + +#define LIGHTSENSOR_IOCTL_GET_ENABLED _IOR(LIGHTSENSOR_IOCTL_MAGIC, 1, int *) +#define LIGHTSENSOR_IOCTL_ENABLE _IOW(LIGHTSENSOR_IOCTL_MAGIC, 2, int *) + +#endif diff --git a/include/linux/max17048_battery.h b/include/linux/max17048_battery.h new file mode 100644 index 000000000000..d997082fb5a9 --- /dev/null +++ b/include/linux/max17048_battery.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Copyright (C) 2012 Nvidia Cooperation + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MAX17048_BATTERY_H_ +#define __MAX17048_BATTERY_H_ +#include <linux/smb349-charger.h> + +struct max17048_battery_model { + uint8_t rcomp; + uint8_t soccheck_A; + uint8_t soccheck_B; + uint8_t bits; + uint8_t alert_threshold; + uint8_t one_percent_alerts; + uint8_t alert_on_reset; + uint16_t rcomp_seg; + uint16_t hibernate; + uint16_t vreset; + uint16_t valert; + uint16_t ocvtest; +}; + +struct max17048_platform_data { + int (*battery_online)(void); + int (*charging_status)(void); + int (*charger_online)(void); +}; +#endif diff --git a/include/linux/max8831_backlight.h b/include/linux/max8831_backlight.h new file mode 100644 index 000000000000..f92857485c1a --- /dev/null +++ b/include/linux/max8831_backlight.h @@ -0,0 +1,17 @@ +/* + * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c + */ +#ifndef __LINUX_MAX8831_BACKLIGHT_H +#define __LINUX_PWM8831_BACKLIGHT_H + +#include <linux/backlight.h> + +struct platform_max8831_backlight_data { + int id; + const char *name; + unsigned int max_brightness; + unsigned int dft_brightness; + int (*notify)(struct device *dev, int brightness); +}; + +#endif diff --git a/include/linux/mfd/max77663-core.h b/include/linux/mfd/max77663-core.h new file mode 100644 index 000000000000..acfe22aac535 --- /dev/null +++ b/include/linux/mfd/max77663-core.h @@ -0,0 +1,178 @@ +/* + * include/linux/mfd/max77663-core.h + * + * Copyright 2011 Maxim Integrated Products, Inc. + * Copyright (C) 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_MFD_MAX77663_CORE_H__ +#define __LINUX_MFD_MAX77663_CORE_H__ + +#include <linux/irq.h> +#include <linux/mfd/core.h> + +/* + * Interrupts + */ +enum { + MAX77663_IRQ_LBT_LB, /* Low-Battery */ + MAX77663_IRQ_LBT_THERM_ALRM1, /* Thermal alarm status, > 120C */ + MAX77663_IRQ_LBT_THERM_ALRM2, /* Thermal alarm status, > 140C */ + + MAX77663_IRQ_GPIO0, /* GPIO0 edge detection */ + MAX77663_IRQ_GPIO1, /* GPIO1 edge detection */ + MAX77663_IRQ_GPIO2, /* GPIO2 edge detection */ + MAX77663_IRQ_GPIO3, /* GPIO3 edge detection */ + MAX77663_IRQ_GPIO4, /* GPIO4 edge detection */ + MAX77663_IRQ_GPIO5, /* GPIO5 edge detection */ + MAX77663_IRQ_GPIO6, /* GPIO6 edge detection */ + MAX77663_IRQ_GPIO7, /* GPIO7 edge detection */ + + MAX77663_IRQ_ONOFF_HRDPOWRN, /* Hard power off warnning */ + MAX77663_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */ + MAX77663_IRQ_ONOFF_EN0_FALLING, /* EN0 falling */ + MAX77663_IRQ_ONOFF_EN0_RISING, /* EN0 rising */ + MAX77663_IRQ_ONOFF_LID_FALLING, /* LID falling */ + MAX77663_IRQ_ONOFF_LID_RISING, /* LID rising */ + MAX77663_IRQ_ONOFF_ACOK_FALLING,/* ACOK falling */ + MAX77663_IRQ_ONOFF_ACOK_RISING, /* ACOK rising */ + + MAX77663_IRQ_RTC, /* RTC */ + MAX77663_IRQ_SD_PF, /* SD power fail */ + MAX77663_IRQ_LDO_PF, /* LDO power fail */ + MAX77663_IRQ_32K, /* 32kHz oscillator */ + MAX77663_IRQ_NVER, /* Non-Volatile Event Recorder */ + + MAX77663_IRQ_NR, +}; + +/* + *GPIOs + */ +enum { + MAX77663_GPIO0, + MAX77663_GPIO1, + MAX77663_GPIO2, + MAX77663_GPIO3, + MAX77663_GPIO4, + MAX77663_GPIO5, + MAX77663_GPIO6, + MAX77663_GPIO7, + + MAX77663_GPIO_NR, +}; + +/* Direction */ +enum max77663_gpio_dir { + GPIO_DIR_DEF, + GPIO_DIR_IN, + GPIO_DIR_OUT, +}; + +/* Data output */ +enum max77663_gpio_data_out { + GPIO_DOUT_DEF, + GPIO_DOUT_HIGH, + GPIO_DOUT_LOW, +}; + +/* Output drive */ +enum max77663_gpio_out_drv { + GPIO_OUT_DRV_DEF, + GPIO_OUT_DRV_PUSH_PULL, + GPIO_OUT_DRV_OPEN_DRAIN, +}; + +/* Pull-up */ +enum max77663_gpio_pull_up { + GPIO_PU_DEF, + GPIO_PU_ENABLE, + GPIO_PU_DISABLE, +}; + +/* Pull-down */ +enum max77663_gpio_pull_down { + GPIO_PD_DEF, + GPIO_PD_ENABLE, + GPIO_PD_DISABLE, +}; + +/* Alternate */ +enum max77663_gpio_alt { + GPIO_ALT_DEF, + GPIO_ALT_ENABLE, + GPIO_ALT_DISABLE, +}; + +/* + * Flags + */ +#define SLP_LPM_ENABLE 0x01 + +struct max77663_gpio_config { + int gpio; /* gpio number */ + enum max77663_gpio_dir dir; + enum max77663_gpio_data_out dout; + enum max77663_gpio_out_drv out_drv; + enum max77663_gpio_pull_up pull_up; + enum max77663_gpio_pull_down pull_down; + enum max77663_gpio_alt alternate; +}; + +struct max77663_platform_data { + int irq_base; + int gpio_base; + + int num_gpio_cfgs; + struct max77663_gpio_config *gpio_cfgs; + + int num_subdevs; + struct mfd_cell *sub_devices; + + unsigned int flags; + + unsigned char rtc_i2c_addr; + + bool use_power_off; +}; + +#if defined(CONFIG_MFD_MAX77663) +int max77663_read(struct device *dev, u8 addr, void *values, u32 len, + bool is_rtc); +int max77663_write(struct device *dev, u8 addr, void *values, u32 len, + bool is_rtc); +int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value, + bool is_rtc); +int max77663_gpio_set_alternate(int gpio, int alternate); +#else +static inline int max77663_read(struct device *dev, u8 addr, void *values, + u32 len, bool is_rtc) +{ + return 0; +} + +static inline int max77663_write(struct device *dev, u8 addr, void *values, + u32 len, bool is_rtc) +{ + return 0; +} + +static inline int max77663_set_bits(struct device *dev, u8 addr, u8 mask, + u8 value, bool is_rtc) +{ + return 0; +} + +static inline int max77663_gpio_set_alternate(int gpio, int alternate) +{ + return 0; +} +#endif /* defined(CONFIG_MFD_MAX77663) */ + +#endif /* __LINUX_MFD_MAX77663_CORE_H__ */ diff --git a/include/linux/mfd/max8907c.h b/include/linux/mfd/max8907c.h new file mode 100644 index 000000000000..48014b0485c5 --- /dev/null +++ b/include/linux/mfd/max8907c.h @@ -0,0 +1,259 @@ +/* linux/mfd/max8907c.h + * + * Functions to access MAX8907C power management chip. + * + * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_MAX8907C_H +#define __LINUX_MFD_MAX8907C_H + +/* MAX8907C register map */ +#define MAX8907C_REG_SYSENSEL 0x00 +#define MAX8907C_REG_ON_OFF_IRQ1 0x01 +#define MAX8907C_REG_ON_OFF_IRQ1_MASK 0x02 +#define MAX8907C_REG_ON_OFF_STAT 0x03 +#define MAX8907C_REG_SDCTL1 0x04 +#define MAX8907C_REG_SDSEQCNT1 0x05 +#define MAX8907C_REG_SDV1 0x06 +#define MAX8907C_REG_SDCTL2 0x07 +#define MAX8907C_REG_SDSEQCNT2 0x08 +#define MAX8907C_REG_SDV2 0x09 +#define MAX8907C_REG_SDCTL3 0x0A +#define MAX8907C_REG_SDSEQCNT3 0x0B +#define MAX8907C_REG_SDV3 0x0C +#define MAX8907C_REG_ON_OFF_IRQ2 0x0D +#define MAX8907C_REG_ON_OFF_IRQ2_MASK 0x0E +#define MAX8907C_REG_RESET_CNFG 0x0F +#define MAX8907C_REG_LDOCTL16 0x10 +#define MAX8907C_REG_LDOSEQCNT16 0x11 +#define MAX8907C_REG_LDO16VOUT 0x12 +#define MAX8907C_REG_SDBYSEQCNT 0x13 +#define MAX8907C_REG_LDOCTL17 0x14 +#define MAX8907C_REG_LDOSEQCNT17 0x15 +#define MAX8907C_REG_LDO17VOUT 0x16 +#define MAX8907C_REG_LDOCTL1 0x18 +#define MAX8907C_REG_LDOSEQCNT1 0x19 +#define MAX8907C_REG_LDO1VOUT 0x1A +#define MAX8907C_REG_LDOCTL2 0x1C +#define MAX8907C_REG_LDOSEQCNT2 0x1D +#define MAX8907C_REG_LDO2VOUT 0x1E +#define MAX8907C_REG_LDOCTL3 0x20 +#define MAX8907C_REG_LDOSEQCNT3 0x21 +#define MAX8907C_REG_LDO3VOUT 0x22 +#define MAX8907C_REG_LDOCTL4 0x24 +#define MAX8907C_REG_LDOSEQCNT4 0x25 +#define MAX8907C_REG_LDO4VOUT 0x26 +#define MAX8907C_REG_LDOCTL5 0x28 +#define MAX8907C_REG_LDOSEQCNT5 0x29 +#define MAX8907C_REG_LDO5VOUT 0x2A +#define MAX8907C_REG_LDOCTL6 0x2C +#define MAX8907C_REG_LDOSEQCNT6 0x2D +#define MAX8907C_REG_LDO6VOUT 0x2E +#define MAX8907C_REG_LDOCTL7 0x30 +#define MAX8907C_REG_LDOSEQCNT7 0x31 +#define MAX8907C_REG_LDO7VOUT 0x32 +#define MAX8907C_REG_LDOCTL8 0x34 +#define MAX8907C_REG_LDOSEQCNT8 0x35 +#define MAX8907C_REG_LDO8VOUT 0x36 +#define MAX8907C_REG_LDOCTL9 0x38 +#define MAX8907C_REG_LDOSEQCNT9 0x39 +#define MAX8907C_REG_LDO9VOUT 0x3A +#define MAX8907C_REG_LDOCTL10 0x3C +#define MAX8907C_REG_LDOSEQCNT10 0x3D +#define MAX8907C_REG_LDO10VOUT 0x3E +#define MAX8907C_REG_LDOCTL11 0x40 +#define MAX8907C_REG_LDOSEQCNT11 0x41 +#define MAX8907C_REG_LDO11VOUT 0x42 +#define MAX8907C_REG_LDOCTL12 0x44 +#define MAX8907C_REG_LDOSEQCNT12 0x45 +#define MAX8907C_REG_LDO12VOUT 0x46 +#define MAX8907C_REG_LDOCTL13 0x48 +#define MAX8907C_REG_LDOSEQCNT13 0x49 +#define MAX8907C_REG_LDO13VOUT 0x4A +#define MAX8907C_REG_LDOCTL14 0x4C +#define MAX8907C_REG_LDOSEQCNT14 0x4D +#define MAX8907C_REG_LDO14VOUT 0x4E +#define MAX8907C_REG_LDOCTL15 0x50 +#define MAX8907C_REG_LDOSEQCNT15 0x51 +#define MAX8907C_REG_LDO15VOUT 0x52 +#define MAX8907C_REG_OUT5VEN 0x54 +#define MAX8907C_REG_OUT5VSEQ 0x55 +#define MAX8907C_REG_OUT33VEN 0x58 +#define MAX8907C_REG_OUT33VSEQ 0x59 +#define MAX8907C_REG_LDOCTL19 0x5C +#define MAX8907C_REG_LDOSEQCNT19 0x5D +#define MAX8907C_REG_LDO19VOUT 0x5E +#define MAX8907C_REG_LBCNFG 0x60 +#define MAX8907C_REG_SEQ1CNFG 0x64 +#define MAX8907C_REG_SEQ2CNFG 0x65 +#define MAX8907C_REG_SEQ3CNFG 0x66 +#define MAX8907C_REG_SEQ4CNFG 0x67 +#define MAX8907C_REG_SEQ5CNFG 0x68 +#define MAX8907C_REG_SEQ6CNFG 0x69 +#define MAX8907C_REG_SEQ7CNFG 0x6A +#define MAX8907C_REG_LDOCTL18 0x72 +#define MAX8907C_REG_LDOSEQCNT18 0x73 +#define MAX8907C_REG_LDO18VOUT 0x74 +#define MAX8907C_REG_BBAT_CNFG 0x78 +#define MAX8907C_REG_CHG_CNTL1 0x7C +#define MAX8907C_REG_CHG_CNTL2 0x7D +#define MAX8907C_REG_CHG_IRQ1 0x7E +#define MAX8907C_REG_CHG_IRQ2 0x7F +#define MAX8907C_REG_CHG_IRQ1_MASK 0x80 +#define MAX8907C_REG_CHG_IRQ2_MASK 0x81 +#define MAX8907C_REG_CHG_STAT 0x82 +#define MAX8907C_REG_WLED_MODE_CNTL 0x84 +#define MAX8907C_REG_ILED_CNTL 0x84 +#define MAX8907C_REG_II1RR 0x8E +#define MAX8907C_REG_II2RR 0x8F +#define MAX8907C_REG_LDOCTL20 0x9C +#define MAX8907C_REG_LDOSEQCNT20 0x9D +#define MAX8907C_REG_LDO20VOUT 0x9E + +/* RTC register */ +#define MAX8907C_REG_RTC_SEC 0x00 +#define MAX8907C_REG_RTC_MIN 0x01 +#define MAX8907C_REG_RTC_HOURS 0x02 +#define MAX8907C_REG_RTC_WEEKDAY 0x03 +#define MAX8907C_REG_RTC_DATE 0x04 +#define MAX8907C_REG_RTC_MONTH 0x05 +#define MAX8907C_REG_RTC_YEAR1 0x06 +#define MAX8907C_REG_RTC_YEAR2 0x07 +#define MAX8907C_REG_ALARM0_SEC 0x08 +#define MAX8907C_REG_ALARM0_MIN 0x09 +#define MAX8907C_REG_ALARM0_HOURS 0x0A +#define MAX8907C_REG_ALARM0_WEEKDAY 0x0B +#define MAX8907C_REG_ALARM0_DATE 0x0C +#define MAX8907C_REG_ALARM0_MONTH 0x0D +#define MAX8907C_REG_ALARM0_YEAR1 0x0E +#define MAX8907C_REG_ALARM0_YEAR2 0x0F +#define MAX8907C_REG_ALARM1_SEC 0x10 +#define MAX8907C_REG_ALARM1_MIN 0x11 +#define MAX8907C_REG_ALARM1_HOURS 0x12 +#define MAX8907C_REG_ALARM1_WEEKDAY 0x13 +#define MAX8907C_REG_ALARM1_DATE 0x14 +#define MAX8907C_REG_ALARM1_MONTH 0x15 +#define MAX8907C_REG_ALARM1_YEAR1 0x16 +#define MAX8907C_REG_ALARM1_YEAR2 0x17 +#define MAX8907C_REG_ALARM0_CNTL 0x18 +#define MAX8907C_REG_ALARM1_CNTL 0x19 +#define MAX8907C_REG_RTC_STATUS 0x1A +#define MAX8907C_REG_RTC_CNTL 0x1B +#define MAX8907C_REG_RTC_IRQ 0x1C +#define MAX8907C_REG_RTC_IRQ_MASK 0x1D +#define MAX8907C_REG_MPL_CNTL 0x1E + +/* ADC and Touch Screen Controller register map */ + +#define MAX8907C_CTL 0 +#define MAX8907C_SEQCNT 1 +#define MAX8907C_VOUT 2 + +/* mask bit fields */ +#define MAX8907C_MASK_LDO_SEQ 0x1C +#define MAX8907C_MASK_LDO_EN 0x01 +#define MAX8907C_MASK_VBBATTCV 0x03 +#define MAX8907C_MASK_OUT5V_VINEN 0x10 +#define MAX8907C_MASK_OUT5V_ENSRC 0x0E +#define MAX8907C_MASK_OUT5V_EN 0x01 + +/* Power off bit in RESET_CNFG reg */ +#define MAX8907C_MASK_POWER_OFF 0x40 + +#define MAX8907C_MASK_PWR_EN 0x80 +#define MAX8907C_MASK_CTL_SEQ 0x1C + +#define MAX8907C_PWR_EN 0x80 +#define MAX8907C_CTL_SEQ 0x04 + +#define MAX8907C_SD_SEQ1 0x02 +#define MAX8907C_SD_SEQ2 0x06 + +#define MAX8907C_DELAY_CNT0 0x00 + +#define MAX8907C_POWER_UP_DELAY_CNT1 0x10 +#define MAX8907C_POWER_UP_DELAY_CNT12 0xC0 + +#define MAX8907C_POWER_DOWN_DELAY_CNT12 0x0C + +#define RTC_I2C_ADDR 0x68 + +/* + * MAX8907B revision requires s/w WAR to connect PWREN input to + * sequencer 2 because of the bug in the silicon. + */ +#define MAX8907B_II2RR_PWREN_WAR (0x12) + +/* Defines common for all supplies PWREN sequencer selection */ +#define MAX8907B_SEQSEL_PWREN_LXX 1 /* SEQ2 (PWREN) */ + +/* IRQ definitions */ +enum { + MAX8907C_IRQ_VCHG_DC_OVP, + MAX8907C_IRQ_VCHG_DC_F, + MAX8907C_IRQ_VCHG_DC_R, + MAX8907C_IRQ_VCHG_THM_OK_R, + MAX8907C_IRQ_VCHG_THM_OK_F, + MAX8907C_IRQ_VCHG_MBATTLOW_F, + MAX8907C_IRQ_VCHG_MBATTLOW_R, + MAX8907C_IRQ_VCHG_RST, + MAX8907C_IRQ_VCHG_DONE, + MAX8907C_IRQ_VCHG_TOPOFF, + MAX8907C_IRQ_VCHG_TMR_FAULT, + MAX8907C_IRQ_GPM_RSTIN, + MAX8907C_IRQ_GPM_MPL, + MAX8907C_IRQ_GPM_SW_3SEC, + MAX8907C_IRQ_GPM_EXTON_F, + MAX8907C_IRQ_GPM_EXTON_R, + MAX8907C_IRQ_GPM_SW_1SEC, + MAX8907C_IRQ_GPM_SW_F, + MAX8907C_IRQ_GPM_SW_R, + MAX8907C_IRQ_GPM_SYSCKEN_F, + MAX8907C_IRQ_GPM_SYSCKEN_R, + MAX8907C_IRQ_RTC_ALARM1, + MAX8907C_IRQ_RTC_ALARM0, + MAX8907C_NR_IRQS, +}; + +struct max8907c { + struct device *dev; + struct mutex io_lock; + struct mutex irq_lock; + struct i2c_client *i2c_power; + struct i2c_client *i2c_rtc; + int irq_base; + int core_irq; + + unsigned char cache_chg[2]; + unsigned char cache_on[2]; + unsigned char cache_rtc; + +}; + +struct max8907c_platform_data { + int num_subdevs; + struct platform_device **subdevs; + int irq_base; + int (*max8907c_setup)(void); + bool use_power_off; +}; + +int max8907c_reg_read(struct i2c_client *i2c, u8 reg); +int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val); +int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val); +int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val); +int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val); + +int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base); +void max8907c_irq_free(struct max8907c *chip); +int max8907c_suspend(struct i2c_client *i2c, pm_message_t state); +int max8907c_resume(struct i2c_client *i2c); +void max8907c_deep_sleep(int enter); +int max8907c_pwr_en_config(void); +int max8907c_pwr_en_attach(void); +#endif diff --git a/include/linux/mfd/ricoh583.h b/include/linux/mfd/ricoh583.h new file mode 100644 index 000000000000..4e38cded0fa5 --- /dev/null +++ b/include/linux/mfd/ricoh583.h @@ -0,0 +1,164 @@ +/* include/linux/mfd/ricoh583.h + * + * Core driver interface to access RICOH583 power management chip. + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_RICOH583_H +#define __LINUX_MFD_RICOH583_H + +#include <linux/rtc.h> +/* RICOH583 IRQ definitions */ +enum { + RICOH583_IRQ_ONKEY, + RICOH583_IRQ_ACOK, + RICOH583_IRQ_LIDOPEN, + RICOH583_IRQ_PREOT, + RICOH583_IRQ_CLKSTP, + RICOH583_IRQ_ONKEY_OFF, + RICOH583_IRQ_WD, + RICOH583_IRQ_EN_PWRREQ1, + RICOH583_IRQ_EN_PWRREQ2, + RICOH583_IRQ_PRE_VINDET, + + RICOH583_IRQ_DC0LIM, + RICOH583_IRQ_DC1LIM, + RICOH583_IRQ_DC2LIM, + RICOH583_IRQ_DC3LIM, + + RICOH583_IRQ_CTC, + RICOH583_IRQ_YALE, + RICOH583_IRQ_DALE, + RICOH583_IRQ_WALE, + + RICOH583_IRQ_AIN1L, + RICOH583_IRQ_AIN2L, + RICOH583_IRQ_AIN3L, + RICOH583_IRQ_VBATL, + RICOH583_IRQ_VIN3L, + RICOH583_IRQ_VIN8L, + RICOH583_IRQ_AIN1H, + RICOH583_IRQ_AIN2H, + RICOH583_IRQ_AIN3H, + RICOH583_IRQ_VBATH, + RICOH583_IRQ_VIN3H, + RICOH583_IRQ_VIN8H, + RICOH583_IRQ_ADCEND, + + RICOH583_IRQ_GPIO0, + RICOH583_IRQ_GPIO1, + RICOH583_IRQ_GPIO2, + RICOH583_IRQ_GPIO3, + RICOH583_IRQ_GPIO4, + RICOH583_IRQ_GPIO5, + RICOH583_IRQ_GPIO6, + RICOH583_IRQ_GPIO7, + RICOH583_NR_IRQS, +}; + +/* Ricoh583 gpio definitions */ +enum { + RICOH583_GPIO0, + RICOH583_GPIO1, + RICOH583_GPIO2, + RICOH583_GPIO3, + RICOH583_GPIO4, + RICOH583_GPIO5, + RICOH583_GPIO6, + RICOH583_GPIO7, + + RICOH583_NR_GPIO, +}; + +enum ricoh583_deepsleep_control_id { + RICOH583_DS_NONE, + RICOH583_DS_DC0, + RICOH583_DS_DC1, + RICOH583_DS_DC2, + RICOH583_DS_DC3, + RICOH583_DS_LDO0, + RICOH583_DS_LDO1, + RICOH583_DS_LDO2, + RICOH583_DS_LDO3, + RICOH583_DS_LDO4, + RICOH583_DS_LDO5, + RICOH583_DS_LDO6, + RICOH583_DS_LDO7, + RICOH583_DS_LDO8, + RICOH583_DS_LDO9, + RICOH583_DS_PSO0, + RICOH583_DS_PSO1, + RICOH583_DS_PSO2, + RICOH583_DS_PSO3, + RICOH583_DS_PSO4, + RICOH583_DS_PSO5, + RICOH583_DS_PSO6, + RICOH583_DS_PSO7, +}; +enum ricoh583_ext_pwrreq_control { + RICOH583_EXT_PWRREQ1_CONTROL = 0x1, + RICOH583_EXT_PWRREQ2_CONTROL = 0x2, +}; + +struct ricoh583_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct ricoh583_rtc_platform_data { + int irq; + struct rtc_time time; +}; + +struct ricoh583_gpio_init_data { + unsigned pulldn_en:1; /* Enable pull down */ + unsigned output_mode_en:1; /* Enable output mode during init */ + unsigned output_val:1; /* Output value if it is in output mode */ + unsigned init_apply:1; /* Apply init data on configuring gpios*/ +}; + +struct ricoh583_platform_data { + int num_subdevs; + struct ricoh583_subdev_info *subdevs; + int gpio_base; + int irq_base; + + struct ricoh583_gpio_init_data *gpio_init_data; + int num_gpioinit_data; + bool enable_shutdown_pin; +}; + +extern int ricoh583_read(struct device *dev, uint8_t reg, uint8_t *val); +extern int ricoh583_bulk_reads(struct device *dev, u8 reg, u8 count, + uint8_t *val); +extern int ricoh583_write(struct device *dev, u8 reg, uint8_t val); +extern int ricoh583_bulk_writes(struct device *dev, u8 reg, u8 count, + uint8_t *val); +extern int ricoh583_set_bits(struct device *dev, u8 reg, uint8_t bit_mask); +extern int ricoh583_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask); +extern int ricoh583_update(struct device *dev, u8 reg, uint8_t val, + uint8_t mask); +extern int ricoh583_ext_power_req_config(struct device *dev, + enum ricoh583_deepsleep_control_id control_id, + enum ricoh583_ext_pwrreq_control ext_pwr_req, + int deepsleep_slot_nr); +extern int ricoh583_power_off(void); + +#endif diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h index 3f43069413e7..109f4da5f223 100644 --- a/include/linux/mfd/tps65090.h +++ b/include/linux/mfd/tps65090.h @@ -78,11 +78,17 @@ struct tps65090 { * DCDC1, DCDC2 and DCDC3. * @gpio: Gpio number if external control is enabled and controlled through * gpio. + * @wait_timeout_us: wait timeout in microseconds; + * >0 : specify minimum wait timeout in us for FETx, will update WTFET[1:0] + * in FETx_CTRL reg; + * 0 : not to update WTFET[1:0] in FETx_CTRL reg for FETx; + * -1 : for non-FETx. */ struct tps65090_regulator_plat_data { struct regulator_init_data *reg_init_data; bool enable_ext_control; int gpio; + int wait_timeout_us; }; struct tps65090_platform_data { diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index 87994542573b..5354b7d3b559 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -13,6 +13,10 @@ #define TPS6586X_SLEW_RATE_SET 0x08 #define TPS6586X_SLEW_RATE_MASK 0x07 +#define SM0_PWM_BIT 0 +#define SM1_PWM_BIT 1 +#define SM2_PWM_BIT 2 + enum { TPS6586X_ID_SYS, TPS6586X_ID_SM_0, @@ -62,8 +66,23 @@ enum { TPS6586X_INT_RTC_ALM2, }; +enum pwm_pfm_mode { + PWM_ONLY, + AUTO_PWM_PFM, + PWM_DEFAULT_VALUE +}; + struct tps6586x_settings { int slew_rate; + /* SM0, SM1 and SM2 have PWM-only and auto PWM/PFM mode */ + enum pwm_pfm_mode sm_pwm_mode; +}; + +enum { + TPS6586X_RTC_CL_SEL_1_5PF = 0x0, + TPS6586X_RTC_CL_SEL_6_5PF = 0x1, + TPS6586X_RTC_CL_SEL_7_5PF = 0x2, + TPS6586X_RTC_CL_SEL_12_5PF = 0x3, }; struct tps6586x_subdev_info { @@ -73,6 +92,20 @@ struct tps6586x_subdev_info { struct device_node *of_node; }; +struct tps6586x_epoch_start { + int year; + int month; + int day; + int hour; + int min; + int sec; +}; + +struct tps6586x_rtc_platform_data { + struct tps6586x_epoch_start start; + int cl_sel; /* internal XTAL capacitance, see TPS6586X_RTC_CL_SEL* */ +}; + struct tps6586x_platform_data { int num_subdevs; struct tps6586x_subdev_info *subdevs; diff --git a/include/linux/mfd/tps6591x.h b/include/linux/mfd/tps6591x.h new file mode 100644 index 000000000000..d0d829fc8aba --- /dev/null +++ b/include/linux/mfd/tps6591x.h @@ -0,0 +1,124 @@ +/* + * include/linux/mfd/tps6591x.c + * Core driver interface for TI TPS6591x PMIC family + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_MFD_TPS6591X_H +#define __LINUX_MFD_TPS6591X_H + +#include <linux/rtc.h> + +enum { + TPS6591X_INT_PWRHOLD_F, + TPS6591X_INT_VMBHI, + TPS6591X_INT_PWRON, + TPS6591X_INT_PWRON_LP, + TPS6591X_INT_PWRHOLD_R, + TPS6591X_INT_HOTDIE, + TPS6591X_INT_RTC_ALARM, + TPS6591X_INT_RTC_PERIOD, + TPS6591X_INT_GPIO0, + TPS6591X_INT_GPIO1, + TPS6591X_INT_GPIO2, + TPS6591X_INT_GPIO3, + TPS6591X_INT_GPIO4, + TPS6591X_INT_GPIO5, + TPS6591X_INT_WTCHDG, + TPS6591X_INT_VMBCH2_H, + TPS6591X_INT_VMBCH2_L, + TPS6591X_INT_PWRDN, + + /* Last entry */ + TPS6591X_INT_NR, +}; + +/* Gpio definitions */ +enum { + TPS6591X_GPIO_GP0 = 0, + TPS6591X_GPIO_GP1 = 1, + TPS6591X_GPIO_GP2 = 2, + TPS6591X_GPIO_GP3 = 3, + TPS6591X_GPIO_GP4 = 4, + TPS6591X_GPIO_GP5 = 5, + TPS6591X_GPIO_GP6 = 6, + TPS6591X_GPIO_GP7 = 7, + TPS6591X_GPIO_GP8 = 8, + + /* Last entry */ + TPS6591X_GPIO_NR, +}; + +struct tps6591x_subdev_info { + int id; + const char *name; + void *platform_data; +}; + +struct tps6591x_rtc_platform_data { + int irq; + struct rtc_time time; +}; + +struct tps6591x_sleep_keepon_data { + /* set 1 to maintain the following on sleep mode */ + unsigned therm_keepon:1; /* themal monitoring */ + unsigned clkout32k_keepon:1; /* CLK32KOUT */ + unsigned vrtc_keepon:1; /* LD0 full load capability */ + unsigned i2chs_keepon:1; /* high speed internal clock */ +}; + +struct tps6591x_gpio_init_data { + unsigned sleep_en:1; /* Enable sleep mode */ + unsigned pulldn_en:1; /* Enable pull down */ + unsigned output_mode_en:1; /* Enable output mode during init */ + unsigned output_val:1; /* Output value if it is in output mode */ + unsigned init_apply:1; /* Apply init data on configuring gpios*/ +}; + +struct tps6591x_platform_data { + int gpio_base; + int irq_base; + + int num_subdevs; + struct tps6591x_subdev_info *subdevs; + + bool dev_slp_en; + struct tps6591x_sleep_keepon_data *slp_keepon; + + struct tps6591x_gpio_init_data *gpio_init_data; + int num_gpioinit_data; + + bool use_power_off; +}; + +/* + * NOTE: the functions below are not intended for use outside + * of the TPS6591X sub-device drivers + */ +extern int tps6591x_write(struct device *dev, int reg, uint8_t val); +extern int tps6591x_writes(struct device *dev, int reg, int len, uint8_t *val); +extern int tps6591x_read(struct device *dev, int reg, uint8_t *val); +extern int tps6591x_reads(struct device *dev, int reg, int len, uint8_t *val); +extern int tps6591x_set_bits(struct device *dev, int reg, uint8_t bit_mask); +extern int tps6591x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); +extern int tps6591x_update(struct device *dev, int reg, uint8_t val, + uint8_t mask); + +#endif /*__LINUX_MFD_TPS6591X_H */ diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h index 2c75c9c9318f..efb921d9bbd3 100644 --- a/include/linux/mfd/tps80031.h +++ b/include/linux/mfd/tps80031.h @@ -25,6 +25,7 @@ #include <linux/device.h> #include <linux/regmap.h> +#include <linux/rtc.h> /* Pull-ups/Pull-downs */ #define TPS80031_CFG_INPUT_PUPD1 0xF0 @@ -434,6 +435,28 @@ enum { #define TPS80031_I2C_ID2_ADDR 0x49 #define TPS80031_I2C_ID3_ADDR 0x4A +enum adc_channel { + BATTERY_TYPE = 0, /* External ADC */ + BATTERY_TEMPERATURE = 1, /* External ADC */ + AUDIO_ACCESSORY = 2, /* External ADC */ + TEMPERATURE_EXTERNAL_DIODE = 3, /* External ADC */ + TEMPERATURE_MEASUREMENT = 4, /* External ADC */ + GENERAL_PURPOSE_1 = 5, /* External ADC */ + GENERAL_PURPOSE_2 = 6, /* External ADC */ + SYSTEM_SUPPLY = 7, /* Internal ADC */ + BACKUP_BATTERY = 8, /* Internal ADC */ + EXTERNAL_CHARGER_INPUT = 9, /* Internal ADC */ + VBUS = 10, /* Internal ADC */ + VBUS_DCDC_OUTPUT_CURRENT = 11, /* Internal ADC */ + DIE_TEMPERATURE_1 = 12, /* Internal ADC */ + DIE_TEMPERATURE_2 = 13, /* Internal ADC */ + USB_ID_LINE = 14, /* Internal ADC */ + TEST_NETWORK_1 = 15, /* Internal ADC */ + TEST_NETWORK_2 = 16, /* Internal ADC */ + BATTERY_CHARGING_CURRENT = 17, /* Internal ADC */ + BATTERY_VOLTAGE = 18, /* Internal ADC */ +}; + enum { TPS80031_REGULATOR_VIO, TPS80031_REGULATOR_SMPS1, @@ -506,6 +529,11 @@ enum tps80031_pupd_settings { TPS80031_PUPD_PULLUP, }; +struct tps80031_rtc_platform_data { + struct rtc_time time; + int msecure_gpio; +}; + struct tps80031 { struct device *dev; unsigned long chip_info; @@ -520,6 +548,11 @@ struct tps80031_pupd_init_data { int setting; }; +struct tps80031_bg_platform_data { + int irq_base; + int battery_present; +}; + /* * struct tps80031_regulator_platform_data - tps80031 regulator platform data. * @@ -634,4 +667,7 @@ static inline int tps80031_irq_get_virq(struct device *dev, int irq) extern int tps80031_ext_power_req_config(struct device *dev, unsigned long ext_ctrl_flag, int preq_bit, int state_reg_add, int trans_reg_add); + +extern int tps80031_gpadc_conversion(int channle_no); + #endif /*__LINUX_MFD_TPS80031_H */ diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index ace9a5f01c64..4a189ba6b128 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -333,6 +333,7 @@ struct mm_struct { void (*unmap_area) (struct mm_struct *mm, unsigned long addr); #endif unsigned long mmap_base; /* base of mmap area */ + unsigned long mmap_legacy_base; /* base of mmap area in bottom-up allocations */ unsigned long task_size; /* size of task vm space */ unsigned long cached_hole_size; /* if non-zero, the largest hole below free_area_cache */ unsigned long free_area_cache; /* first hole of size cached_hole_size or larger */ diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index f31725ba49f3..dba4bd1dc791 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -249,6 +249,7 @@ struct mmc_card { #define MMC_CARD_REMOVED (1<<7) /* card has been removed */ #define MMC_STATE_HIGHSPEED_200 (1<<8) /* card is in HS200 mode */ #define MMC_STATE_DOING_BKOPS (1<<10) /* card is doing BKOPS */ +#define MMC_STATE_NEED_BKOPS (1<<11) /* Card needs to do bkops */ unsigned int quirks; /* card quirks */ #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ @@ -411,11 +412,11 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data) #define mmc_card_hs200(c) ((c)->state & MMC_STATE_HIGHSPEED_200) #define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) #define mmc_card_ddr_mode(c) ((c)->state & MMC_STATE_HIGHSPEED_DDR) -#define mmc_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED) #define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED) #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC) #define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) #define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS) +#define mmc_card_need_bkops(c) ((c)->state & MMC_STATE_NEED_BKOPS) #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) @@ -423,12 +424,13 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data) #define mmc_card_set_hs200(c) ((c)->state |= MMC_STATE_HIGHSPEED_200) #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR) -#define mmc_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED) #define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED) #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC) #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED) #define mmc_card_set_doing_bkops(c) ((c)->state |= MMC_STATE_DOING_BKOPS) #define mmc_card_clr_doing_bkops(c) ((c)->state &= ~MMC_STATE_DOING_BKOPS) +#define mmc_card_set_need_bkops(c) ((c)->state |= MMC_STATE_NEED_BKOPS) +#define mmc_card_clk_need_bkops(c) ((c)->state &= ~MMC_STATE_NEED_BKOPS) /* * Quirk add/remove for MMC products. diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 66b465927602..364a417a475f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -465,6 +465,9 @@ int mmc_card_sleep(struct mmc_host *host); int mmc_card_can_sleep(struct mmc_host *host); int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); +int mmc_speed_class_control(struct mmc_host *host, + unsigned int speed_class_ctrl_arg); + /* Module parameter */ extern bool mmc_assume_removable; diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h index 1ebcf9ba1256..e65bf7c9dab0 100644 --- a/include/linux/mmc/sd.h +++ b/include/linux/mmc/sd.h @@ -19,6 +19,10 @@ #define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ #define SD_SWITCH_VOLTAGE 11 /* ac R1 */ + /* class 2 */ +#define SD_SEND_TUNING_PATTERN 19 /* adtc R1 */ +#define SD_SPEED_CLASS_CONTROL 20 /* ac R1b */ + /* class 10 */ #define SD_SWITCH 6 /* adtc [31:0] See below R1 */ @@ -91,4 +95,13 @@ #define SD_SWITCH_ACCESS_DEF 0 #define SD_SWITCH_ACCESS_HS 1 +/* + * SD_SPEED_CLASS_CONTROL definitions + */ +#define SD_SPEED_CLASS_CONTROL_START_REC 0x0 +#define SD_SPEED_CLASS_CONTROL_CREATE_DIR 0x1 +#define SD_SPEED_CLASS_CONTROL_UPDATE_CI 0x4 + + #endif /* LINUX_MMC_SD_H */ + diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index b838ffc49e4a..6858253fdb96 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -20,73 +20,79 @@ struct sdhci_host { /* Data set by hardware interface driver */ const char *hw_name; /* Hardware bus name */ - - unsigned int quirks; /* Deviations from spec. */ + struct dentry *debugfs_root; + u64 quirks; /* Deviations from spec. */ /* Controller doesn't honor resets unless we touch the clock register */ -#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1ULL<<0) /* Controller has bad caps bits, but really supports DMA */ -#define SDHCI_QUIRK_FORCE_DMA (1<<1) +#define SDHCI_QUIRK_FORCE_DMA (1ULL<<1) /* Controller doesn't like to be reset when there is no card inserted. */ -#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1ULL<<2) /* Controller doesn't like clearing the power reg before a change */ -#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) +#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1ULL<<3) /* Controller has flaky internal state so reset it on each ios change */ -#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) +#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1ULL<<4) /* Controller has an unusable DMA engine */ -#define SDHCI_QUIRK_BROKEN_DMA (1<<5) +#define SDHCI_QUIRK_BROKEN_DMA (1ULL<<5) /* Controller has an unusable ADMA engine */ -#define SDHCI_QUIRK_BROKEN_ADMA (1<<6) +#define SDHCI_QUIRK_BROKEN_ADMA (1ULL<<6) /* Controller can only DMA from 32-bit aligned addresses */ -#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) +#define SDHCI_QUIRK_32BIT_DMA_ADDR (1ULL<<7) /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ -#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1ULL<<8) /* Controller can only ADMA chunks that are a multiple of 32 bits */ -#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) +#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1ULL<<9) /* Controller needs to be reset after each request to stay stable */ -#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1ULL<<10) /* Controller needs voltage and power writes to happen separately */ -#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1ULL<<11) /* Controller provides an incorrect timeout value for transfers */ -#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) +#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1ULL<<12) /* Controller has an issue with buffer bits for small transfers */ -#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) +#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1ULL<<13) /* Controller does not provide transfer-complete interrupt when not busy */ -#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) +#define SDHCI_QUIRK_NO_BUSY_IRQ (1ULL<<14) /* Controller has unreliable card detection */ -#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) +#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1ULL<<15) /* Controller reports inverted write-protect state */ -#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) +#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1ULL<<16) /* Controller has nonstandard clock management */ -#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) +#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1ULL<<17) /* Controller does not like fast PIO transfers */ -#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) +#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1ULL<<18) /* Controller losing signal/interrupt enable states after reset */ -#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) +#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1ULL<<19) /* Controller has to be forced to use block size of 2048 bytes */ -#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) +#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1ULL<<20) /* Controller cannot do multi-block transfers */ -#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) +#define SDHCI_QUIRK_NO_MULTIBLOCK (1ULL<<21) /* Controller can only handle 1-bit data transfers */ -#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) +#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1ULL<<22) /* Controller needs 10ms delay between applying power and clock */ -#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) +#define SDHCI_QUIRK_DELAY_AFTER_POWER (1ULL<<23) /* Controller uses SDCLK instead of TMCLK for data timeouts */ -#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) +#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1ULL<<24) /* Controller reports wrong base clock capability */ -#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) +#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1ULL<<25) /* Controller cannot support End Attribute in NOP ADMA descriptor */ -#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) +#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1ULL<<26) /* Controller is missing device caps. Use caps provided by host */ -#define SDHCI_QUIRK_MISSING_CAPS (1<<27) +#define SDHCI_QUIRK_MISSING_CAPS (1ULL<<27) /* Controller uses Auto CMD12 command to stop the transfer */ -#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) +#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1ULL<<28) /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ -#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) +#define SDHCI_QUIRK_NO_HISPD_BIT (1ULL<<29) /* Controller treats ADMA descriptors with length 0000h incorrectly */ -#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) +#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1ULL<<30) /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ -#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) +#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1ULL<<31) +/* Controller cannot report the line status in present state register */ +#define SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING (1ULL<<32) +/* Controller doesn't follow the standard frequency tuning procedure */ +#define SDHCI_QUIRK_NON_STANDARD_TUNING (1ULL<<33) +/* Controller doesn't calculate max_discard_to */ +#define SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO (1ULL<<34) unsigned int quirks2; /* More deviations from spec. */ @@ -160,6 +166,7 @@ struct sdhci_host { struct tasklet_struct finish_tasklet; struct timer_list timer; /* Timer for timeouts */ + unsigned int card_int_set; /* card int status */ u32 caps; /* Alternative CAPABILITY_0 */ u32 caps1; /* Alternative CAPABILITY_1 */ diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 17446d3c3602..4bc451b93d0f 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -38,8 +38,8 @@ * [8:0] Byte/block count */ -#define R4_18V_PRESENT (1<<24) -#define R4_MEMORY_PRESENT (1 << 27) +#define R4_18V_PRESENT BIT(24) +#define R4_MEMORY_PRESENT BIT(27) /* SDIO status in R5 @@ -139,12 +139,12 @@ #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */ #define SDIO_SPEED_BSS_SHIFT 1 -#define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT) -#define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT) -#define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT) -#define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT) -#define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT) -#define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_BSS_MASK (7 << SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_SDR12 (0 << SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_SDR25 (1 << SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_SDR50 (2 << SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_SDR104 (3 << SDIO_SPEED_BSS_SHIFT) +#define SDIO_SPEED_DDR50 (4 << SDIO_SPEED_BSS_SHIFT) #define SDIO_SPEED_EHS SDIO_SPEED_SDR25 /* Enable High-Speed */ #define SDIO_CCCR_UHS 0x14 @@ -154,9 +154,9 @@ #define SDIO_CCCR_DRIVE_STRENGTH 0x15 #define SDIO_SDTx_MASK 0x07 -#define SDIO_DRIVE_SDTA (1<<0) -#define SDIO_DRIVE_SDTC (1<<1) -#define SDIO_DRIVE_SDTD (1<<2) +#define SDIO_DRIVE_SDTA (1 << 0) +#define SDIO_DRIVE_SDTC (1 << 1) +#define SDIO_DRIVE_SDTD (1 << 2) #define SDIO_DRIVE_DTSx_MASK 0x03 #define SDIO_DRIVE_DTSx_SHIFT 4 #define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT) diff --git a/include/linux/mpu.h b/include/linux/mpu.h new file mode 100644 index 000000000000..1977b38b8c15 --- /dev/null +++ b/include/linux/mpu.h @@ -0,0 +1,367 @@ +/* + $License: + Copyright (C) 2011 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +#ifndef __MPU_H_ +#define __MPU_H_ + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* Number of axes on each sensor */ +#define GYRO_NUM_AXES (3) +#define ACCEL_NUM_AXES (3) +#define COMPASS_NUM_AXES (3) + +struct mpu_read_write { + /* Memory address or register address depending on ioctl */ + __u16 address; + __u16 length; + __u8 *data; +}; + +enum mpuirq_data_type { + MPUIRQ_DATA_TYPE_MPU_IRQ, + MPUIRQ_DATA_TYPE_SLAVE_IRQ, + MPUIRQ_DATA_TYPE_PM_EVENT, + MPUIRQ_DATA_TYPE_NUM_TYPES, +}; + +/* User space PM event notification */ +#define MPU_PM_EVENT_SUSPEND_PREPARE (3) +#define MPU_PM_EVENT_POST_SUSPEND (4) + +struct mpuirq_data { + __u32 interruptcount; + __u64 irqtime; + __u32 data_type; + __s32 data; +}; + +enum ext_slave_config_key { + MPU_SLAVE_CONFIG_ODR_SUSPEND, + MPU_SLAVE_CONFIG_ODR_RESUME, + MPU_SLAVE_CONFIG_FSR_SUSPEND, + MPU_SLAVE_CONFIG_FSR_RESUME, + MPU_SLAVE_CONFIG_MOT_THS, + MPU_SLAVE_CONFIG_NMOT_THS, + MPU_SLAVE_CONFIG_MOT_DUR, + MPU_SLAVE_CONFIG_NMOT_DUR, + MPU_SLAVE_CONFIG_IRQ_SUSPEND, + MPU_SLAVE_CONFIG_IRQ_RESUME, + MPU_SLAVE_WRITE_REGISTERS, + MPU_SLAVE_READ_REGISTERS, + MPU_SLAVE_CONFIG_INTERNAL_REFERENCE, + /* AMI 306 specific config keys */ + MPU_SLAVE_PARAM, + MPU_SLAVE_WINDOW, + MPU_SLAVE_READWINPARAMS, + MPU_SLAVE_SEARCHOFFSET, + /* AKM specific config keys */ + MPU_SLAVE_READ_SCALE, + /* MPU3050 and MPU6050 Keys */ + MPU_SLAVE_INT_CONFIG, + MPU_SLAVE_EXT_SYNC, + MPU_SLAVE_FULL_SCALE, + MPU_SLAVE_LPF, + MPU_SLAVE_CLK_SRC, + MPU_SLAVE_DIVIDER, + MPU_SLAVE_DMP_ENABLE, + MPU_SLAVE_FIFO_ENABLE, + MPU_SLAVE_DMP_CFG1, + MPU_SLAVE_DMP_CFG2, + MPU_SLAVE_TC, + MPU_SLAVE_GYRO, + MPU_SLAVE_ADDR, + MPU_SLAVE_PRODUCT_REVISION, + MPU_SLAVE_SILICON_REVISION, + MPU_SLAVE_PRODUCT_ID, + MPU_SLAVE_GYRO_SENS_TRIM, + MPU_SLAVE_ACCEL_SENS_TRIM, + MPU_SLAVE_RAM, + /* -------------------------- */ + MPU_SLAVE_CONFIG_NUM_CONFIG_KEYS +}; + +/* For the MPU_SLAVE_CONFIG_IRQ_SUSPEND and MPU_SLAVE_CONFIG_IRQ_RESUME */ +enum ext_slave_config_irq_type { + MPU_SLAVE_IRQ_TYPE_NONE, + MPU_SLAVE_IRQ_TYPE_MOTION, + MPU_SLAVE_IRQ_TYPE_DATA_READY, +}; + +/* Structure for the following IOCTS's + * MPU_CONFIG_GYRO + * MPU_CONFIG_ACCEL + * MPU_CONFIG_COMPASS + * MPU_CONFIG_PRESSURE + * MPU_GET_CONFIG_GYRO + * MPU_GET_CONFIG_ACCEL + * MPU_GET_CONFIG_COMPASS + * MPU_GET_CONFIG_PRESSURE + * + * @key one of enum ext_slave_config_key + * @len length of data pointed to by data + * @apply zero if communication with the chip is not necessary, false otherwise + * This flag can be used to select cached data or to refresh cashed data + * cache data to be pushed later or push immediately. If true and the + * slave is on the secondary bus the MPU will first enger bypass mode + * before calling the slaves .config or .get_config funcion + * @data pointer to the data to confgure or get + */ +struct ext_slave_config { + __u8 key; + __u16 len; + __u8 apply; + void *data; +}; + +enum ext_slave_type { + EXT_SLAVE_TYPE_GYROSCOPE, + EXT_SLAVE_TYPE_ACCEL, + EXT_SLAVE_TYPE_COMPASS, + EXT_SLAVE_TYPE_PRESSURE, + /*EXT_SLAVE_TYPE_TEMPERATURE */ + + EXT_SLAVE_NUM_TYPES +}; + +enum ext_slave_id { + ID_INVALID = 0, + + ACCEL_ID_LIS331, + ACCEL_ID_LSM303DLX, + ACCEL_ID_LIS3DH, + ACCEL_ID_KXSD9, + ACCEL_ID_KXTF9, + ACCEL_ID_BMA150, + ACCEL_ID_BMA222, + ACCEL_ID_BMA250, + ACCEL_ID_ADXL34X, + ACCEL_ID_MMA8450, + ACCEL_ID_MMA845X, + ACCEL_ID_MPU6050, + + COMPASS_ID_AK8975, + COMPASS_ID_AK8963, + COMPASS_ID_AK8972, + COMPASS_ID_AMI30X, + COMPASS_ID_AMI306, + COMPASS_ID_YAS529, + COMPASS_ID_YAS530, + COMPASS_ID_HMC5883, + COMPASS_ID_LSM303DLH, + COMPASS_ID_LSM303DLM, + COMPASS_ID_MMC314X, + COMPASS_ID_HSCDTD002B, + COMPASS_ID_HSCDTD004A, + + PRESSURE_ID_BMA085, +}; + +enum ext_slave_endian { + EXT_SLAVE_BIG_ENDIAN, + EXT_SLAVE_LITTLE_ENDIAN, + EXT_SLAVE_FS8_BIG_ENDIAN, + EXT_SLAVE_FS16_BIG_ENDIAN, +}; + +enum ext_slave_bus { + EXT_SLAVE_BUS_INVALID = -1, + EXT_SLAVE_BUS_PRIMARY = 0, + EXT_SLAVE_BUS_SECONDARY = 1 +}; + + +/** + * struct ext_slave_platform_data - Platform data for mpu3050 and mpu6050 + * slave devices + * + * @type: the type of slave device based on the enum ext_slave_type + * definitions. + * @irq: the irq number attached to the slave if any. + * @adapt_num: the I2C adapter number. + * @bus: the bus the slave is attached to: enum ext_slave_bus + * @address: the I2C slave address of the slave device. + * @orientation: the mounting matrix of the device relative to MPU. + * @irq_data: private data for the slave irq handler + * @private_data: additional data, user customizable. Not touched by the MPU + * driver. + * + * The orientation matricies are 3x3 rotation matricies + * that are applied to the data to rotate from the mounting orientation to the + * platform orientation. The values must be one of 0, 1, or -1 and each row and + * column should have exactly 1 non-zero value. + */ +struct ext_slave_platform_data { + __u8 type; + __u32 irq; + __u32 adapt_num; + __u32 bus; + __u8 address; + __s8 orientation[9]; + void *irq_data; + void *private_data; +}; + +struct fix_pnt_range { + __s32 mantissa; + __s32 fraction; +}; + +static inline long range_fixedpoint_to_long_mg(struct fix_pnt_range rng) +{ + return (long)(rng.mantissa * 1000 + rng.fraction / 10); +} + +struct ext_slave_read_trigger { + __u8 reg; + __u8 value; +}; + +/** + * struct ext_slave_descr - Description of the slave device for programming. + * + * @suspend: function pointer to put the device in suspended state + * @resume: function pointer to put the device in running state + * @read: function that reads the device data + * @init: function used to preallocate memory used by the driver + * @exit: function used to free memory allocated for the driver + * @config: function used to configure the device + * @get_config:function used to get the device's configuration + * + * @name: text name of the device + * @type: device type. enum ext_slave_type + * @id: enum ext_slave_id + * @read_reg: starting register address to retrieve data. + * @read_len: length in bytes of the sensor data. Typically 6. + * @endian: byte order of the data. enum ext_slave_endian + * @range: full scale range of the slave ouput: struct fix_pnt_range + * @trigger: If reading data first requires writing a register this is the + * data to write. + * + * Defines the functions and information about the slave the mpu3050 and + * mpu6050 needs to use the slave device. + */ +struct ext_slave_descr { + int (*init) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*exit) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*suspend) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*resume) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata); + int (*read) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + __u8 *data); + int (*config) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + struct ext_slave_config *config); + int (*get_config) (void *mlsl_handle, + struct ext_slave_descr *slave, + struct ext_slave_platform_data *pdata, + struct ext_slave_config *config); + + char *name; + __u8 type; + __u8 id; + __u8 read_reg; + __u8 read_len; + __u8 endian; + struct fix_pnt_range range; + struct ext_slave_read_trigger *trigger; +}; + +/** + * struct mpu_platform_data - Platform data for the mpu driver + * @int_config: Bits [7:3] of the int config register. + * @level_shifter: 0: VLogic, 1: VDD + * @orientation: Orientation matrix of the gyroscope + * + * Contains platform specific information on how to configure the MPU3050 to + * work on this platform. The orientation matricies are 3x3 rotation matricies + * that are applied to the data to rotate from the mounting orientation to the + * platform orientation. The values must be one of 0, 1, or -1 and each row and + * column should have exactly 1 non-zero value. + */ +struct mpu_platform_data { + __u8 int_config; + __u8 level_shifter; + __s8 orientation[GYRO_NUM_AXES * GYRO_NUM_AXES]; +}; + +#define MPU_IOCTL (0x81) /* Magic number for MPU Iocts */ +/* IOCTL commands for /dev/mpu */ + +/*-------------------------------------------------------------------------- + * Deprecated, debugging only + */ +#define MPU_SET_MPU_PLATFORM_DATA \ + _IOWR(MPU_IOCTL, 0x01, struct mpu_platform_data) +#define MPU_SET_EXT_SLAVE_PLATFORM_DATA \ + _IOWR(MPU_IOCTL, 0x01, struct ext_slave_platform_data) +/*--------------------------------------------------------------------------*/ +#define MPU_GET_EXT_SLAVE_PLATFORM_DATA \ + _IOWR(MPU_IOCTL, 0x02, struct ext_slave_platform_data) +#define MPU_GET_MPU_PLATFORM_DATA \ + _IOWR(MPU_IOCTL, 0x02, struct mpu_platform_data) +#define MPU_GET_EXT_SLAVE_DESCR \ + _IOWR(MPU_IOCTL, 0x02, struct ext_slave_descr) + +#define MPU_READ _IOWR(MPU_IOCTL, 0x10, struct mpu_read_write) +#define MPU_WRITE _IOW(MPU_IOCTL, 0x10, struct mpu_read_write) +#define MPU_READ_MEM _IOWR(MPU_IOCTL, 0x11, struct mpu_read_write) +#define MPU_WRITE_MEM _IOW(MPU_IOCTL, 0x11, struct mpu_read_write) +#define MPU_READ_FIFO _IOWR(MPU_IOCTL, 0x12, struct mpu_read_write) +#define MPU_WRITE_FIFO _IOW(MPU_IOCTL, 0x12, struct mpu_read_write) + +#define MPU_READ_COMPASS _IOR(MPU_IOCTL, 0x12, __u8) +#define MPU_READ_ACCEL _IOR(MPU_IOCTL, 0x13, __u8) +#define MPU_READ_PRESSURE _IOR(MPU_IOCTL, 0x14, __u8) + +#define MPU_CONFIG_GYRO _IOW(MPU_IOCTL, 0x20, struct ext_slave_config) +#define MPU_CONFIG_ACCEL _IOW(MPU_IOCTL, 0x21, struct ext_slave_config) +#define MPU_CONFIG_COMPASS _IOW(MPU_IOCTL, 0x22, struct ext_slave_config) +#define MPU_CONFIG_PRESSURE _IOW(MPU_IOCTL, 0x23, struct ext_slave_config) + +#define MPU_GET_CONFIG_GYRO _IOWR(MPU_IOCTL, 0x20, struct ext_slave_config) +#define MPU_GET_CONFIG_ACCEL _IOWR(MPU_IOCTL, 0x21, struct ext_slave_config) +#define MPU_GET_CONFIG_COMPASS _IOWR(MPU_IOCTL, 0x22, struct ext_slave_config) +#define MPU_GET_CONFIG_PRESSURE _IOWR(MPU_IOCTL, 0x23, struct ext_slave_config) + +#define MPU_SUSPEND _IOW(MPU_IOCTL, 0x30, __u32) +#define MPU_RESUME _IOW(MPU_IOCTL, 0x31, __u32) +/* Userspace PM Event response */ +#define MPU_PM_EVENT_HANDLED _IO(MPU_IOCTL, 0x32) + +#define MPU_GET_REQUESTED_SENSORS _IOR(MPU_IOCTL, 0x40, __u8) +#define MPU_SET_REQUESTED_SENSORS _IOW(MPU_IOCTL, 0x40, __u8) +#define MPU_GET_IGNORE_SYSTEM_SUSPEND _IOR(MPU_IOCTL, 0x41, __u8) +#define MPU_SET_IGNORE_SYSTEM_SUSPEND _IOW(MPU_IOCTL, 0x41, __u8) +#define MPU_GET_MLDL_STATUS _IOR(MPU_IOCTL, 0x42, __u8) +#define MPU_GET_I2C_SLAVES_ENABLED _IOR(MPU_IOCTL, 0x43, __u8) + + +#endif /* __MPU_H_ */ diff --git a/include/linux/mpu3050.h b/include/linux/mpu3050.h new file mode 100644 index 000000000000..a8dcd5a9473f --- /dev/null +++ b/include/linux/mpu3050.h @@ -0,0 +1,255 @@ +/* + $License: + Copyright (C) 2010 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +#ifndef __MPU3050_H_ +#define __MPU3050_H_ + +#ifdef __KERNEL__ +#include <linux/types.h> +#endif + +#ifdef M_HW +#error MPU6000 build including MPU3050 header +#endif + +#define MPU_NAME "mpu3050" +#define DEFAULT_MPU_SLAVEADDR 0x68 + +/*==== MPU REGISTER SET ====*/ +enum mpu_register { + MPUREG_WHO_AM_I = 0, /* 00 0x00 */ + MPUREG_PRODUCT_ID, /* 01 0x01 */ + MPUREG_02_RSVD, /* 02 0x02 */ + MPUREG_03_RSVD, /* 03 0x03 */ + MPUREG_04_RSVD, /* 04 0x04 */ + MPUREG_XG_OFFS_TC, /* 05 0x05 */ + MPUREG_06_RSVD, /* 06 0x06 */ + MPUREG_07_RSVD, /* 07 0x07 */ + MPUREG_YG_OFFS_TC, /* 08 0x08 */ + MPUREG_09_RSVD, /* 09 0x09 */ + MPUREG_0A_RSVD, /* 10 0x0a */ + MPUREG_ZG_OFFS_TC, /* 11 0x0b */ + MPUREG_X_OFFS_USRH, /* 12 0x0c */ + MPUREG_X_OFFS_USRL, /* 13 0x0d */ + MPUREG_Y_OFFS_USRH, /* 14 0x0e */ + MPUREG_Y_OFFS_USRL, /* 15 0x0f */ + MPUREG_Z_OFFS_USRH, /* 16 0x10 */ + MPUREG_Z_OFFS_USRL, /* 17 0x11 */ + MPUREG_FIFO_EN1, /* 18 0x12 */ + MPUREG_FIFO_EN2, /* 19 0x13 */ + MPUREG_AUX_SLV_ADDR, /* 20 0x14 */ + MPUREG_SMPLRT_DIV, /* 21 0x15 */ + MPUREG_DLPF_FS_SYNC, /* 22 0x16 */ + MPUREG_INT_CFG, /* 23 0x17 */ + MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */ + MPUREG_19_RSVD, /* 25 0x19 */ + MPUREG_INT_STATUS, /* 26 0x1a */ + MPUREG_TEMP_OUT_H, /* 27 0x1b */ + MPUREG_TEMP_OUT_L, /* 28 0x1c */ + MPUREG_GYRO_XOUT_H, /* 29 0x1d */ + MPUREG_GYRO_XOUT_L, /* 30 0x1e */ + MPUREG_GYRO_YOUT_H, /* 31 0x1f */ + MPUREG_GYRO_YOUT_L, /* 32 0x20 */ + MPUREG_GYRO_ZOUT_H, /* 33 0x21 */ + MPUREG_GYRO_ZOUT_L, /* 34 0x22 */ + MPUREG_23_RSVD, /* 35 0x23 */ + MPUREG_24_RSVD, /* 36 0x24 */ + MPUREG_25_RSVD, /* 37 0x25 */ + MPUREG_26_RSVD, /* 38 0x26 */ + MPUREG_27_RSVD, /* 39 0x27 */ + MPUREG_28_RSVD, /* 40 0x28 */ + MPUREG_29_RSVD, /* 41 0x29 */ + MPUREG_2A_RSVD, /* 42 0x2a */ + MPUREG_2B_RSVD, /* 43 0x2b */ + MPUREG_2C_RSVD, /* 44 0x2c */ + MPUREG_2D_RSVD, /* 45 0x2d */ + MPUREG_2E_RSVD, /* 46 0x2e */ + MPUREG_2F_RSVD, /* 47 0x2f */ + MPUREG_30_RSVD, /* 48 0x30 */ + MPUREG_31_RSVD, /* 49 0x31 */ + MPUREG_32_RSVD, /* 50 0x32 */ + MPUREG_33_RSVD, /* 51 0x33 */ + MPUREG_34_RSVD, /* 52 0x34 */ + MPUREG_DMP_CFG_1, /* 53 0x35 */ + MPUREG_DMP_CFG_2, /* 54 0x36 */ + MPUREG_BANK_SEL, /* 55 0x37 */ + MPUREG_MEM_START_ADDR, /* 56 0x38 */ + MPUREG_MEM_R_W, /* 57 0x39 */ + MPUREG_FIFO_COUNTH, /* 58 0x3a */ + MPUREG_FIFO_COUNTL, /* 59 0x3b */ + MPUREG_FIFO_R_W, /* 60 0x3c */ + MPUREG_USER_CTRL, /* 61 0x3d */ + MPUREG_PWR_MGM, /* 62 0x3e */ + MPUREG_3F_RSVD, /* 63 0x3f */ + NUM_OF_MPU_REGISTERS /* 64 0x40 */ +}; + +/*==== BITS FOR MPU ====*/ + +/*---- MPU 'FIFO_EN1' register (12) ----*/ +#define BIT_TEMP_OUT 0x80 +#define BIT_GYRO_XOUT 0x40 +#define BIT_GYRO_YOUT 0x20 +#define BIT_GYRO_ZOUT 0x10 +#define BIT_ACCEL_XOUT 0x08 +#define BIT_ACCEL_YOUT 0x04 +#define BIT_ACCEL_ZOUT 0x02 +#define BIT_AUX_1OUT 0x01 +/*---- MPU 'FIFO_EN2' register (13) ----*/ +#define BIT_AUX_2OUT 0x02 +#define BIT_AUX_3OUT 0x01 +/*---- MPU 'DLPF_FS_SYNC' register (16) ----*/ +#define BITS_EXT_SYNC_NONE 0x00 +#define BITS_EXT_SYNC_TEMP 0x20 +#define BITS_EXT_SYNC_GYROX 0x40 +#define BITS_EXT_SYNC_GYROY 0x60 +#define BITS_EXT_SYNC_GYROZ 0x80 +#define BITS_EXT_SYNC_ACCELX 0xA0 +#define BITS_EXT_SYNC_ACCELY 0xC0 +#define BITS_EXT_SYNC_ACCELZ 0xE0 +#define BITS_EXT_SYNC_MASK 0xE0 +#define BITS_FS_250DPS 0x00 +#define BITS_FS_500DPS 0x08 +#define BITS_FS_1000DPS 0x10 +#define BITS_FS_2000DPS 0x18 +#define BITS_FS_MASK 0x18 +#define BITS_DLPF_CFG_256HZ_NOLPF2 0x00 +#define BITS_DLPF_CFG_188HZ 0x01 +#define BITS_DLPF_CFG_98HZ 0x02 +#define BITS_DLPF_CFG_42HZ 0x03 +#define BITS_DLPF_CFG_20HZ 0x04 +#define BITS_DLPF_CFG_10HZ 0x05 +#define BITS_DLPF_CFG_5HZ 0x06 +#define BITS_DLPF_CFG_2100HZ_NOLPF 0x07 +#define BITS_DLPF_CFG_MASK 0x07 +/*---- MPU 'INT_CFG' register (17) ----*/ +#define BIT_ACTL 0x80 +#define BIT_ACTL_LOW 0x80 +#define BIT_ACTL_HIGH 0x00 +#define BIT_OPEN 0x40 +#define BIT_OPEN_DRAIN 0x40 +#define BIT_PUSH_PULL 0x00 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_INT_PULSE_WIDTH_50US 0x00 +#define BIT_INT_ANYRD_2CLEAR 0x10 +#define BIT_INT_STAT_READ_2CLEAR 0x00 +#define BIT_MPU_RDY_EN 0x04 +#define BIT_DMP_INT_EN 0x02 +#define BIT_RAW_RDY_EN 0x01 +/*---- MPU 'INT_STATUS' register (1A) ----*/ +#define BIT_INT_STATUS_FIFO_OVERLOW 0x80 +#define BIT_MPU_RDY 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_RDY 0x01 +/*---- MPU 'BANK_SEL' register (37) ----*/ +#define BIT_PRFTCH_EN 0x20 +#define BIT_CFG_USER_BANK 0x10 +#define BITS_MEM_SEL 0x0f +/*---- MPU 'USER_CTRL' register (3D) ----*/ +#define BIT_DMP_EN 0x80 +#define BIT_FIFO_EN 0x40 +#define BIT_AUX_IF_EN 0x20 +#define BIT_AUX_RD_LENG 0x10 +#define BIT_AUX_IF_RST 0x08 +#define BIT_DMP_RST 0x04 +#define BIT_FIFO_RST 0x02 +#define BIT_GYRO_RST 0x01 +/*---- MPU 'PWR_MGM' register (3E) ----*/ +#define BIT_H_RESET 0x80 +#define BIT_SLEEP 0x40 +#define BIT_STBY_XG 0x20 +#define BIT_STBY_YG 0x10 +#define BIT_STBY_ZG 0x08 +#define BITS_CLKSEL 0x07 + +/*---- MPU Silicon Revision ----*/ +#define MPU_SILICON_REV_A4 1 /* MPU A4 Device */ +#define MPU_SILICON_REV_B1 2 /* MPU B1 Device */ +#define MPU_SILICON_REV_B4 3 /* MPU B4 Device */ +#define MPU_SILICON_REV_B6 4 /* MPU B6 Device */ + +/*---- MPU Memory ----*/ +#define MPU_MEM_BANK_SIZE (256) +#define FIFO_HW_SIZE (512) + +enum MPU_MEMORY_BANKS { + MPU_MEM_RAM_BANK_0 = 0, + MPU_MEM_RAM_BANK_1, + MPU_MEM_RAM_BANK_2, + MPU_MEM_RAM_BANK_3, + MPU_MEM_NUM_RAM_BANKS, + MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS, + /* This one is always last */ + MPU_MEM_NUM_BANKS +}; + +#define MPU_NUM_AXES (3) + +/*---- structure containing control variables used by MLDL ----*/ +/*---- MPU clock source settings ----*/ +/*---- MPU filter selections ----*/ +enum mpu_filter { + MPU_FILTER_256HZ_NOLPF2 = 0, + MPU_FILTER_188HZ, + MPU_FILTER_98HZ, + MPU_FILTER_42HZ, + MPU_FILTER_20HZ, + MPU_FILTER_10HZ, + MPU_FILTER_5HZ, + MPU_FILTER_2100HZ_NOLPF, + NUM_MPU_FILTER +}; + +enum mpu_fullscale { + MPU_FS_250DPS = 0, + MPU_FS_500DPS, + MPU_FS_1000DPS, + MPU_FS_2000DPS, + NUM_MPU_FS +}; + +enum mpu_clock_sel { + MPU_CLK_SEL_INTERNAL = 0, + MPU_CLK_SEL_PLLGYROX, + MPU_CLK_SEL_PLLGYROY, + MPU_CLK_SEL_PLLGYROZ, + MPU_CLK_SEL_PLLEXT32K, + MPU_CLK_SEL_PLLEXT19M, + MPU_CLK_SEL_RESERVED, + MPU_CLK_SEL_STOP, + NUM_CLK_SEL +}; + +enum mpu_ext_sync { + MPU_EXT_SYNC_NONE = 0, + MPU_EXT_SYNC_TEMP, + MPU_EXT_SYNC_GYROX, + MPU_EXT_SYNC_GYROY, + MPU_EXT_SYNC_GYROZ, + MPU_EXT_SYNC_ACCELX, + MPU_EXT_SYNC_ACCELY, + MPU_EXT_SYNC_ACCELZ, + NUM_MPU_EXT_SYNC +}; + +#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \ + ((ext_sync << 5) | (full_scale << 3) | lpf) + +#endif /* __MPU3050_H_ */ diff --git a/include/linux/mpu6000.h b/include/linux/mpu6000.h new file mode 100644 index 000000000000..5a63c8f07b70 --- /dev/null +++ b/include/linux/mpu6000.h @@ -0,0 +1,406 @@ +/* + $License: + Copyright (C) 2010 InvenSense Corporation, All Rights Reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. + $ + */ + +/** + * @defgroup + * @brief + * + * @{ + * @file mpu6000.h + * @brief + */ + +#ifndef __MPU6000_H_ +#define __MPU6000_H_ + +#define MPU_NAME "mpu6000" +#define DEFAULT_MPU_SLAVEADDR 0x68 + +/*==== M_HW REGISTER SET ====*/ +enum { + MPUREG_XG_OFFS_TC = 0, /* 0x00 */ + MPUREG_YG_OFFS_TC, /* 0x00 */ + MPUREG_ZG_OFFS_TC, /* 0x00 */ + MPUREG_X_FINE_GAIN, /* 0x00 */ + MPUREG_Y_FINE_GAIN, /* 0x00 */ + MPUREG_Z_FINE_GAIN, /* 0x00 */ + MPUREG_XA_OFFS_H, /* 0x00 */ + MPUREG_XA_OFFS_L_TC, /* 0x00 */ + MPUREG_YA_OFFS_H, /* 0x00 */ + MPUREG_YA_OFFS_L_TC, /* 0x00 */ + MPUREG_ZA_OFFS_H, /* 0x00 */ + MPUREG_ZA_OFFS_L_TC, /* 0xB */ + MPUREG_0C_RSVD, /* 0x00 */ + MPUREG_0D_RSVD, /* 0x00 */ + MPUREG_0E_RSVD, /* 0x00 */ + MPUREG_0F_RSVD, /* 0x00 */ + MPUREG_10_RSVD, /* 0x00 */ + MPUREG_11_RSVD, /* 0x00 */ + MPUREG_12_RSVD, /* 0x00 */ + MPUREG_XG_OFFS_USRH, /* 0x00 */ + MPUREG_XG_OFFS_USRL, /* 0x00 */ + MPUREG_YG_OFFS_USRH, /* 0x00 */ + MPUREG_YG_OFFS_USRL, /* 0x00 */ + MPUREG_ZG_OFFS_USRH, /* 0x00 */ + MPUREG_ZG_OFFS_USRL, /* 0x00 */ + MPUREG_SMPLRT_DIV, /* 0x19 */ + MPUREG_CONFIG, /* 0x1A ==> DLPF_FS_SYNC */ + MPUREG_GYRO_CONFIG, /* 0x00 */ + MPUREG_ACCEL_CONFIG, /* 0x00 */ + MPUREG_ACCEL_FF_THR, /* 0x00 */ + MPUREG_ACCEL_FF_DUR, /* 0x00 */ + MPUREG_ACCEL_MOT_THR, /* 0x00 */ + MPUREG_ACCEL_MOT_DUR, /* 0x00 */ + MPUREG_ACCEL_ZRMOT_THR, /* 0x00 */ + MPUREG_ACCEL_ZRMOT_DUR, /* 0x00 */ + MPUREG_FIFO_EN, /* 0x23 */ + MPUREG_I2C_MST_CTRL, /* 0x00 */ + MPUREG_I2C_SLV0_ADDR, /* 0x25 */ + MPUREG_I2C_SLV0_REG, /* 0x00 */ + MPUREG_I2C_SLV0_CTRL, /* 0x00 */ + MPUREG_I2C_SLV1_ADDR, /* 0x28 */ + MPUREG_I2C_SLV1_REG_PASSWORD, /* 0x00 */ + MPUREG_I2C_SLV1_CTRL, /* 0x00 */ + MPUREG_I2C_SLV2_ADDR, /* 0x2B */ + MPUREG_I2C_SLV2_REG, /* 0x00 */ + MPUREG_I2C_SLV2_CTRL, /* 0x00 */ + MPUREG_I2C_SLV3_ADDR, /* 0x2E */ + MPUREG_I2C_SLV3_REG, /* 0x00 */ + MPUREG_I2C_SLV3_CTRL, /* 0x00 */ + MPUREG_I2C_SLV4_ADDR, /* 0x31 */ + MPUREG_I2C_SLV4_REG, /* 0x00 */ + MPUREG_I2C_SLV4_DO, /* 0x00 */ + MPUREG_I2C_SLV4_CTRL, /* 0x00 */ + MPUREG_I2C_SLV4_DI, /* 0x00 */ + MPUREG_I2C_MST_STATUS, /* 0x36 */ + MPUREG_INT_PIN_CFG, /* 0x37 ==> -* INT_CFG */ + MPUREG_INT_ENABLE, /* 0x38 ==> / */ + MPUREG_DMP_INT_STATUS, /* 0x39 */ + MPUREG_INT_STATUS, /* 0x3A */ + MPUREG_ACCEL_XOUT_H, /* 0x3B */ + MPUREG_ACCEL_XOUT_L, /* 0x00 */ + MPUREG_ACCEL_YOUT_H, /* 0x00 */ + MPUREG_ACCEL_YOUT_L, /* 0x00 */ + MPUREG_ACCEL_ZOUT_H, /* 0x00 */ + MPUREG_ACCEL_ZOUT_L, /* 0x00 */ + MPUREG_TEMP_OUT_H, /* 0x41 */ + MPUREG_TEMP_OUT_L, /* 0x00 */ + MPUREG_GYRO_XOUT_H, /* 0x43 */ + MPUREG_GYRO_XOUT_L, /* 0x00 */ + MPUREG_GYRO_YOUT_H, /* 0x00 */ + MPUREG_GYRO_YOUT_L, /* 0x00 */ + MPUREG_GYRO_ZOUT_H, /* 0x00 */ + MPUREG_GYRO_ZOUT_L, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_00, /* 0x49 */ + MPUREG_EXT_SLV_SENS_DATA_01, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_02, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_03, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_04, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_05, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_06, /* 0x4F */ + MPUREG_EXT_SLV_SENS_DATA_07, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_08, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_09, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_10, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_11, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_12, /* 0x55 */ + MPUREG_EXT_SLV_SENS_DATA_13, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_14, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_15, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_16, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_17, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_18, /* 0x5B */ + MPUREG_EXT_SLV_SENS_DATA_19, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_20, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_21, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_22, /* 0x00 */ + MPUREG_EXT_SLV_SENS_DATA_23, /* 0x00 */ + ACCEL_INTEL_STATUS, /* 0x61 */ + MPUREG_62_RSVD, /* 0x00 */ + MPUREG_63_RSVD, /* 0x00 */ + MPUREG_64_RSVD, /* 0x00 */ + MPUREG_65_RSVD, /* 0x00 */ + MPUREG_66_RSVD, /* 0x00 */ + MPUREG_67_RSVD, /* 0x00 */ + SIGNAL_PATH_RESET, /* 0x68 */ + ACCEL_INTEL_CTRL, /* 0x69 */ + MPUREG_USER_CTRL, /* 0x6A */ + MPUREG_PWR_MGMT_1, /* 0x6B */ + MPUREG_PWR_MGMT_2, /* 0x00 */ + MPUREG_BANK_SEL, /* 0x6D */ + MPUREG_MEM_START_ADDR, /* 0x6E */ + MPUREG_MEM_R_W, /* 0x6F */ + MPUREG_PRGM_STRT_ADDRH, /* 0x00 */ + MPUREG_PRGM_STRT_ADDRL, /* 0x00 */ + MPUREG_FIFO_COUNTH, /* 0x72 */ + MPUREG_FIFO_COUNTL, /* 0x00 */ + MPUREG_FIFO_R_W, /* 0x74 */ + MPUREG_WHOAMI, /* 0x75,117 */ + + NUM_OF_MPU_REGISTERS /* = 0x76,118 */ +}; + +/*==== M_HW MEMORY ====*/ +enum MPU_MEMORY_BANKS { + MEM_RAM_BANK_0 = 0, + MEM_RAM_BANK_1, + MEM_RAM_BANK_2, + MEM_RAM_BANK_3, + MEM_RAM_BANK_4, + MEM_RAM_BANK_5, + MEM_RAM_BANK_6, + MEM_RAM_BANK_7, + MEM_RAM_BANK_8, + MEM_RAM_BANK_9, + MEM_RAM_BANK_10, + MEM_RAM_BANK_11, + MPU_MEM_NUM_RAM_BANKS, + MPU_MEM_OTP_BANK_0 = 16 +}; + + +/*==== M_HW parameters ====*/ + +#define NUM_REGS (NUM_OF_MPU_REGISTERS) +#define START_SENS_REGS (0x3B) +#define NUM_SENS_REGS (0x60-START_SENS_REGS+1) + +/*---- MPU Memory ----*/ +#define NUM_BANKS (MPU_MEM_NUM_RAM_BANKS) +#define BANK_SIZE (256) +#define MEM_SIZE (NUM_BANKS*BANK_SIZE) +#define MPU_MEM_BANK_SIZE (BANK_SIZE) /*alternative name */ + +#define FIFO_HW_SIZE (1024) + +#define NUM_EXT_SLAVES (4) + + +/*==== BITS FOR M_HW ====*/ + +/*---- M_HW 'FIFO_EN' register (23) ----*/ +#define BIT_TEMP_OUT 0x80 +#define BIT_GYRO_XOUT 0x40 +#define BIT_GYRO_YOUT 0x20 +#define BIT_GYRO_ZOUT 0x10 +#define BIT_ACCEL 0x08 +#define BIT_SLV_2 0x04 +#define BIT_SLV_1 0x02 +#define BIT_SLV_0 0x01 +/*---- M_HW 'CONFIG' register (1A) ----*/ +/*NONE 0xC0 */ +#define BITS_EXT_SYNC_SET 0x38 +#define BITS_DLPF_CFG 0x07 +/*---- M_HW 'GYRO_CONFIG' register (1B) ----*/ +/* voluntarily modified label from BITS_FS_SEL to + * BITS_GYRO_FS_SEL to avoid confusion with MPU + */ +#define BITS_GYRO_FS_SEL 0x18 +/*NONE 0x07 */ +/*---- M_HW 'ACCEL_CONFIG' register (1C) ----*/ +#define BITS_ACCEL_FS_SEL 0x18 +#define BITS_ACCEL_HPF 0x07 +/*---- M_HW 'I2C_MST_CTRL' register (24) ----*/ +#define BIT_MULT_MST_DIS 0x80 +#define BIT_WAIT_FOR_ES 0x40 +#define BIT_I2C_MST_VDDIO 0x20 +/*NONE 0x10 */ +#define BITS_I2C_MST_CLK 0x0F +/*---- M_HW 'I2C_SLV?_CTRL' register (27,2A,2D,30) ----*/ +#define BIT_SLV_ENABLE 0x80 +#define BIT_SLV_BYTE_SW 0x40 +/*NONE 0x20 */ +#define BIT_SLV_GRP 0x10 +#define BITS_SLV_LENG 0x0F +/*---- M_HW 'I2C_SLV4_ADDR' register (31) ----*/ +#define BIT_I2C_SLV4_RNW 0x80 +/*---- M_HW 'I2C_SLV4_CTRL' register (34) ----*/ +#define BIT_I2C_SLV4_EN 0x80 +#define BIT_SLV4_DONE_INT_EN 0x40 +/*NONE 0x3F */ +/*---- M_HW 'I2C_MST_STATUS' register (36) ----*/ +#define BIT_PASSTHROUGH 0x80 +#define BIT_I2C_SLV4_DONE 0x40 +#define BIT_I2C_LOST_ARB 0x20 +#define BIT_I2C_SLV4_NACK 0x10 +#define BIT_I2C_SLV3_NACK 0x08 +#define BIT_I2C_SLV2_NACK 0x04 +#define BIT_I2C_SLV1_NACK 0x02 +#define BIT_I2C_SLV0_NACK 0x01 +/*---- M_HW 'INT_PIN_CFG' register (37) ----*/ +#define BIT_ACTL 0x80 +#define BIT_ACTL_LOW 0x80 +#define BIT_ACTL_HIGH 0x00 +#define BIT_OPEN 0x40 +#define BIT_LATCH_INT_EN 0x20 +#define BIT_INT_ANYRD_2CLEAR 0x10 +#define BIT_ACTL_FSYNC 0x08 +#define BIT_FSYNC_INT_EN 0x04 +#define BIT_BYPASS_EN 0x02 +#define BIT_CLKOUT_EN 0x01 +/*---- M_HW 'INT_ENABLE' register (38) ----*/ +#define BIT_FF_EN 0x80 +#define BIT_MOT_EN 0x40 +#define BIT_ZMOT_EN 0x20 +#define BIT_FIFO_OVERFLOW_EN 0x10 +#define BIT_I2C_MST_INT_EN 0x08 +#define BIT_PLL_RDY_EN 0x04 +#define BIT_DMP_INT_EN 0x02 +#define BIT_RAW_RDY_EN 0x01 +/*---- M_HW 'DMP_INT_STATUS' register (39) ----*/ +/*NONE 0x80 */ +/*NONE 0x40 */ +#define BIT_DMP_INT_5 0x20 +#define BIT_DMP_INT_4 0x10 +#define BIT_DMP_INT_3 0x08 +#define BIT_DMP_INT_2 0x04 +#define BIT_DMP_INT_1 0x02 +#define BIT_DMP_INT_0 0x01 +/*---- M_HW 'INT_STATUS' register (3A) ----*/ +#define BIT_FF_INT 0x80 +#define BIT_MOT_INT 0x40 +#define BIT_ZMOT_INT 0x20 +#define BIT_FIFO_OVERFLOW_INT 0x10 +#define BIT_I2C_MST_INT 0x08 +#define BIT_PLL_RDY_INT 0x04 +#define BIT_DMP_INT 0x02 +#define BIT_RAW_DATA_RDY_INT 0x01 +/*---- M_HW 'BANK_SEL' register (6D) ----*/ +#define BIT_PRFTCH_EN 0x40 +#define BIT_CFG_USER_BANK 0x20 +#define BITS_MEM_SEL 0x1f +/*---- M_HW 'USER_CTRL' register (6A) ----*/ +#define BIT_DMP_EN 0x80 +#define BIT_FIFO_EN 0x40 +#define BIT_I2C_MST_EN 0x20 +#define BIT_I2C_IF_DIS 0x10 +#define BIT_DMP_RST 0x08 +#define BIT_FIFO_RST 0x04 +#define BIT_I2C_MST_RST 0x02 +#define BIT_SIG_COND_RST 0x01 +/*---- M_HW 'PWR_MGMT_1' register (6B) ----*/ +#define BIT_H_RESET 0x80 +#define BITS_PWRSEL 0x70 +#define BIT_WKUP_INT 0x08 +#define BITS_CLKSEL 0x07 +/*---- M_HW 'PWR_MGMT_2' register (6C) ----*/ +#define BITS_LPA_WAKE_CTRL 0xC0 +#define BIT_STBY_XA 0x20 +#define BIT_STBY_YA 0x10 +#define BIT_STBY_ZA 0x08 +#define BIT_STBY_XG 0x04 +#define BIT_STBY_YG 0x02 +#define BIT_STBY_ZG 0x01 + +/* although it has 6, this refers to the gyros */ +#define MPU_NUM_AXES (3) + +#define ACCEL_MOT_THR_LSB (32) /* mg */ +#define ACCEL_MOT_DUR_LSB (1) +#define ACCEL_ZRMOT_THR_LSB_CONVERSION(mg) ((mg *1000)/255) +#define ACCEL_ZRMOT_DUR_LSB (64) + +/*----------------------------------------------------------------------------*/ +/*---- Alternative names to take care of conflicts with current mpu3050.h ----*/ +/*----------------------------------------------------------------------------*/ + +/*-- registers --*/ +#define MPUREG_DLPF_FS_SYNC MPUREG_CONFIG /* 0x1A */ + +#define MPUREG_PRODUCT_ID MPUREG_WHOAMI /* 0x75 HACK!*/ +#define MPUREG_PWR_MGM MPUREG_PWR_MGMT_1 /* 0x6B */ +#define MPUREG_FIFO_EN1 MPUREG_FIFO_EN /* 0x23 */ +#define MPUREG_DMP_CFG_1 MPUREG_PRGM_STRT_ADDRH /* 0x70 */ +#define MPUREG_DMP_CFG_2 MPUREG_PRGM_STRT_ADDRL /* 0x71 */ +#define MPUREG_INT_CFG MPUREG_INT_ENABLE /* 0x38 */ +#define MPUREG_X_OFFS_USRH MPUREG_XG_OFFS_USRH /* 0x13 */ +#define MPUREG_WHO_AM_I MPUREG_WHOAMI /* 0x75 */ +#define MPUREG_23_RSVD MPUREG_EXT_SLV_SENS_DATA_00 /* 0x49 */ +#define MPUREG_AUX_SLV_ADDR MPUREG_I2C_SLV0_ADDR /* 0x25 */ +#define MPUREG_ACCEL_BURST_ADDR MPUREG_I2C_SLV0_REG /* 0x26 */ + +/*-- bits --*/ +/* 'USER_CTRL' register */ +#define BIT_AUX_IF_EN BIT_I2C_MST_EN +#define BIT_AUX_RD_LENG BIT_I2C_MST_EN +#define BIT_IME_IF_RST BIT_I2C_MST_RST +#define BIT_GYRO_RST BIT_SIG_COND_RST +/* 'INT_ENABLE' register */ +#define BIT_RAW_RDY BIT_RAW_DATA_RDY_INT +#define BIT_MPU_RDY_EN BIT_PLL_RDY_EN +/* 'INT_STATUS' register */ +#define BIT_INT_STATUS_FIFO_OVERLOW BIT_FIFO_OVERFLOW_INT + + + +/*---- M_HW Silicon Revisions ----*/ +#define MPU_SILICON_REV_A1 1 /* M_HW A1 Device */ +#define MPU_SILICON_REV_B1 2 /* M_HW B1 Device */ + +/*---- structure containing control variables used by MLDL ----*/ +/*---- MPU clock source settings ----*/ +/*---- MPU filter selections ----*/ +enum mpu_filter { + MPU_FILTER_256HZ_NOLPF2 = 0, + MPU_FILTER_188HZ, + MPU_FILTER_98HZ, + MPU_FILTER_42HZ, + MPU_FILTER_20HZ, + MPU_FILTER_10HZ, + MPU_FILTER_5HZ, + MPU_FILTER_2100HZ_NOLPF, + NUM_MPU_FILTER +}; + +enum mpu_fullscale { + MPU_FS_250DPS = 0, + MPU_FS_500DPS, + MPU_FS_1000DPS, + MPU_FS_2000DPS, + NUM_MPU_FS +}; + +enum mpu_clock_sel { + MPU_CLK_SEL_INTERNAL = 0, + MPU_CLK_SEL_PLLGYROX, + MPU_CLK_SEL_PLLGYROY, + MPU_CLK_SEL_PLLGYROZ, + MPU_CLK_SEL_PLLEXT32K, + MPU_CLK_SEL_PLLEXT19M, + MPU_CLK_SEL_RESERVED, + MPU_CLK_SEL_STOP, + NUM_CLK_SEL +}; + +enum mpu_ext_sync { + MPU_EXT_SYNC_NONE = 0, + MPU_EXT_SYNC_TEMP, + MPU_EXT_SYNC_GYROX, + MPU_EXT_SYNC_GYROY, + MPU_EXT_SYNC_GYROZ, + MPU_EXT_SYNC_ACCELX, + MPU_EXT_SYNC_ACCELY, + MPU_EXT_SYNC_ACCELZ, + NUM_MPU_EXT_SYNC +}; + +#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \ + ((ext_sync << 5) | (full_scale << 3) | lpf) + +#endif /* __IMU6000_H_ */ diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h index e93837f647de..79ac1e0a7993 100644 --- a/include/linux/mtd/blktrans.h +++ b/include/linux/mtd/blktrans.h @@ -38,7 +38,7 @@ struct mtd_blktrans_dev { struct mutex lock; int devnum; bool bg_stop; - unsigned long size; + unsigned long long size; int readonly; int open; struct kref ref; @@ -61,11 +61,11 @@ struct mtd_blktrans_ops { /* Access functions */ int (*readsect)(struct mtd_blktrans_dev *dev, - unsigned long block, char *buffer); + unsigned long long block, char *buffer); int (*writesect)(struct mtd_blktrans_dev *dev, - unsigned long block, char *buffer); + unsigned long long block, char *buffer); int (*discard)(struct mtd_blktrans_dev *dev, - unsigned long block, unsigned nr_blocks); + unsigned long long block, unsigned nr_blocks); void (*background)(struct mtd_blktrans_dev *dev); /* Block layer ioctls */ diff --git a/include/linux/nbd.h b/include/linux/nbd.h index 4871170a04a0..ae4981ebd18e 100644 --- a/include/linux/nbd.h +++ b/include/linux/nbd.h @@ -41,6 +41,7 @@ struct nbd_device { u64 bytesize; pid_t pid; /* pid of nbd-client, if attached */ int xmit_timeout; + int disconnect; /* a disconnect has been requested by user */ }; #endif diff --git a/include/linux/nct1008.h b/include/linux/nct1008.h new file mode 100644 index 000000000000..9227f4ad82f4 --- /dev/null +++ b/include/linux/nct1008.h @@ -0,0 +1,103 @@ +/* + * include/linux/nct1008.h + * + * NCT1008, temperature monitoring device from ON Semiconductors + * + * Copyright (c) 2010, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_NCT1008_H +#define _LINUX_NCT1008_H + +#include <linux/types.h> + +#include <mach/edp.h> + +#define MAX_ZONES 16 + +struct nct1008_data; + +enum nct1008_chip { NCT1008, NCT72 }; + +struct nct1008_platform_data { + bool supported_hwrev; + bool ext_range; + u8 conv_rate; + u8 offset; + u8 hysteresis; + s8 shutdown_ext_limit; + s8 shutdown_local_limit; + s8 throttling_ext_limit; + s8 thermal_zones[MAX_ZONES]; + u8 thermal_zones_sz; + void (*alarm_fn)(bool raised); + void (*probe_callback)(struct nct1008_data *); +}; + +struct nct1008_data { + struct workqueue_struct *workqueue; + struct work_struct work; + struct i2c_client *client; + struct nct1008_platform_data plat_data; + struct mutex mutex; + struct dentry *dent; + u8 config; + s8 *limits; + u8 limits_sz; + enum nct1008_chip chip; + void (*alarm_fn)(bool raised); + struct regulator *nct_reg; + long current_lo_limit; + long current_hi_limit; + int conv_period_ms; + + void (*alert_func)(void *); + void *alert_data; +}; + +#ifdef CONFIG_SENSORS_NCT1008 +int nct1008_thermal_get_temp(struct nct1008_data *data, long *temp); +int nct1008_thermal_get_temp_low(struct nct1008_data *data, long *temp); +int nct1008_thermal_set_limits(struct nct1008_data *data, + long lo_limit_milli, + long hi_limit_milli); +int nct1008_thermal_set_alert(struct nct1008_data *data, + void (*alert_func)(void *), + void *alert_data); +int nct1008_thermal_set_shutdown_temp(struct nct1008_data *data, + long shutdown_temp); +#else +static inline int nct1008_thermal_get_temp(struct nct1008_data *data, + long *temp) +{ return -EINVAL; } +static inline int nct1008_thermal_get_temp_low(struct nct1008_data *data, + long *temp) +{ return -EINVAL; } +static inline int nct1008_thermal_set_limits(struct nct1008_data *data, + long lo_limit_milli, + long hi_limit_milli) +{ return -EINVAL; } +static inline int nct1008_thermal_set_alert(struct nct1008_data *data, + void (*alert_func)(void *), + void *alert_data) +{ return -EINVAL; } +static inline int nct1008_thermal_set_shutdown_temp(struct nct1008_data *data, + long shutdown_temp) +{ return -EINVAL; } +#endif + +#endif /* _LINUX_NCT1008_H */ diff --git a/include/linux/nfc/bcm2079x.h b/include/linux/nfc/bcm2079x.h new file mode 100644 index 000000000000..359a00839325 --- /dev/null +++ b/include/linux/nfc/bcm2079x.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Broadcom Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _BCM2079X_H +#define _BCM2079X_H + +#define BCMNFC_MAGIC 0xFA + +/* + * BCMNFC power control via ioctl + * BCMNFC_POWER_CTL(0): power off + * BCMNFC_POWER_CTL(1): power on + * BCMNFC_WAKE_CTL(0): wake off + * BCMNFC_WAKE_CTL(1): wake on + */ +#define BCMNFC_POWER_CTL _IO(BCMNFC_MAGIC, 0x01) +#define BCMNFC_CHANGE_ADDR _IO(BCMNFC_MAGIC, 0x02) +#define BCMNFC_READ_FULL_PACKET _IO(BCMNFC_MAGIC, 0x03) +#define BCMNFC_SET_WAKE_ACTIVE_STATE _IO(BCMNFC_MAGIC, 0x04) +#define BCMNFC_WAKE_CTL _IO(BCMNFC_MAGIC, 0x05) +#define BCMNFC_READ_MULTI_PACKETS _IO(BCMNFC_MAGIC, 0x06) + +struct bcm2079x_platform_data { + unsigned int irq_gpio; + unsigned int en_gpio; + int wake_gpio; +}; + +#endif diff --git a/include/linux/nfc/pn544.h b/include/linux/nfc/pn544.h new file mode 100644 index 000000000000..9285000dbb46 --- /dev/null +++ b/include/linux/nfc/pn544.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2010 Trusted Logic S.A. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define PN544_MAGIC 0xE9 + +/* + * PN544 power control via ioctl + * PN544_SET_PWR(0): power off + * PN544_SET_PWR(1): power on + * PN544_SET_PWR(2): reset and power on with firmware download enabled + */ +#define PN544_SET_PWR _IOW(PN544_MAGIC, 0x01, unsigned int) + +struct pn544_i2c_platform_data { + unsigned int irq_gpio; + unsigned int ven_gpio; + unsigned int firm_gpio; +}; diff --git a/include/linux/nvhost.h b/include/linux/nvhost.h new file mode 100644 index 000000000000..ba1dc824bf5b --- /dev/null +++ b/include/linux/nvhost.h @@ -0,0 +1,197 @@ +/* + * include/linux/nvhost.h + * + * Tegra graphics host driver + * + * Copyright (c) 2009-2013, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_H +#define __LINUX_NVHOST_H + +#include <linux/device.h> +#include <linux/types.h> +#include <linux/devfreq.h> +#include <linux/platform_device.h> + +struct nvhost_master; +struct nvhost_hwctx; +struct nvhost_device_power_attr; +struct mem_mgr; + +#define NVHOST_MODULE_MAX_CLOCKS 3 +#define NVHOST_MODULE_MAX_POWERGATE_IDS 2 +#define NVHOST_MODULE_MAX_SYNCPTS 8 +#define NVHOST_MODULE_MAX_WAITBASES 3 +#define NVHOST_MODULE_MAX_MODMUTEXES 5 +#define NVHOST_MODULE_MAX_IORESOURCE_MEM 3 +#define NVHOST_MODULE_NO_POWERGATE_IDS .powergate_ids = {-1, -1} +#define NVHOST_DEFAULT_CLOCKGATE_DELAY .clockgate_delay = 25 +#define NVHOST_NAME_SIZE 24 +#define NVSYNCPT_INVALID (-1) + +/* FIXME: + * Sync point ids are now split into 2 files. + * 1 if this one and other is in + * drivers/video/tegra/host/host1x/host1x_syncpt.h + * So if someone decides to add new sync point in future + * please check both the header files + */ +#define NVSYNCPT_DISP0_D (5) +#define NVSYNCPT_DISP0_H (6) +#define NVSYNCPT_DISP1_H (7) +#define NVSYNCPT_DISP0_A (8) +#define NVSYNCPT_DISP1_A (9) +#define NVSYNCPT_AVP_0 (10) +#define NVSYNCPT_DISP0_B (20) +#define NVSYNCPT_DISP1_B (21) +#define NVSYNCPT_DISP0_C (24) +#define NVSYNCPT_DISP1_C (25) +#define NVSYNCPT_VBLANK0 (26) +#define NVSYNCPT_VBLANK1 (27) +#define NVSYNCPT_DSI (31) + +enum nvhost_power_sysfs_attributes { + NVHOST_POWER_SYSFS_ATTRIB_CLOCKGATE_DELAY = 0, + NVHOST_POWER_SYSFS_ATTRIB_POWERGATE_DELAY, + NVHOST_POWER_SYSFS_ATTRIB_REFCOUNT, + NVHOST_POWER_SYSFS_ATTRIB_MAX +}; + +struct nvhost_clock { + char *name; + unsigned long default_rate; + u32 moduleid; + int reset; + unsigned long devfreq_rate; +}; + +enum nvhost_device_powerstate_t { + NVHOST_POWER_STATE_DEINIT, + NVHOST_POWER_STATE_RUNNING, + NVHOST_POWER_STATE_CLOCKGATED, + NVHOST_POWER_STATE_POWERGATED +}; + +struct nvhost_device_data { + int version; /* ip version number of device */ + int id; /* Separates clients of same hw */ + int index; /* Hardware channel number */ + void __iomem *aperture[NVHOST_MODULE_MAX_IORESOURCE_MEM]; + + u32 syncpts[NVHOST_MODULE_MAX_SYNCPTS]; + u32 waitbases[NVHOST_MODULE_MAX_WAITBASES]; + u32 modulemutexes[NVHOST_MODULE_MAX_MODMUTEXES]; + u32 moduleid; /* Module id for user space API */ + + u32 class; /* Device class */ + bool exclusive; /* True if only one user at a time */ + bool keepalive; /* Do not power gate when opened */ + bool waitbasesync; /* Force sync of wait bases */ + bool powerup_reset; /* Do a reset after power un-gating */ + bool serialize; /* Serialize submits in the channel */ + + int powergate_ids[NVHOST_MODULE_MAX_POWERGATE_IDS]; + bool can_powergate; /* True if module can be power gated */ + int clockgate_delay;/* Delay before clock gated */ + int powergate_delay;/* Delay before power gated */ + struct nvhost_clock clocks[NVHOST_MODULE_MAX_CLOCKS];/* Clock names */ + + struct delayed_work powerstate_down;/* Power state management */ + int num_clks; /* Number of clocks opened for dev */ + struct clk *clk[NVHOST_MODULE_MAX_CLOCKS]; + struct mutex lock; /* Power management lock */ + int powerstate; /* Current power state */ + int refcount; /* Number of tasks active */ + wait_queue_head_t idle_wq; /* Work queue for idle */ + struct list_head client_list; /* List of clients and rate requests */ + + struct nvhost_channel *channel; /* Channel assigned for the module */ + struct kobject *power_kobj; /* kobject to hold power sysfs entries */ + struct nvhost_device_power_attr *power_attrib; /* sysfs attributes */ + struct devfreq *power_manager; /* Device power management */ + struct dentry *debugfs; /* debugfs directory */ + + void *private_data; /* private platform data */ + struct platform_device *pdev; /* owner platform_device */ + + /* Finalize power on. Can be used for context restore. */ + void (*finalize_poweron)(struct platform_device *dev); + + /* Device is busy. */ + void (*busy)(struct platform_device *); + + /* Device is idle. */ + void (*idle)(struct platform_device *); + + /* Device is going to be suspended */ + void (*suspend_ndev)(struct platform_device *); + + /* Device is initialized */ + void (*init)(struct platform_device *dev); + + /* Device is de-initialized. */ + void (*deinit)(struct platform_device *dev); + + /* Preparing for power off. Used for context save. */ + int (*prepare_poweroff)(struct platform_device *dev); + + /* Allocates a context handler for the device */ + struct nvhost_hwctx_handler *(*alloc_hwctx_handler)(u32 syncpt, + u32 waitbase, struct nvhost_channel *ch); + + /* Clock gating callbacks */ + int (*prepare_clockoff)(struct platform_device *dev); + void (*finalize_clockon)(struct platform_device *dev); + + /* Read module register into memory */ + int (*read_reg)(struct platform_device *dev, + struct nvhost_channel *ch, + struct nvhost_hwctx *hwctx, + u32 offset, + u32 *value); +}; + +struct nvhost_devfreq_ext_stat { + int busy; + unsigned long max_freq; + unsigned long min_freq; +}; + +struct nvhost_device_power_attr { + struct platform_device *ndev; + struct kobj_attribute power_attr[NVHOST_POWER_SYSFS_ATTRIB_MAX]; +}; + +void nvhost_device_writel(struct platform_device *dev, u32 r, u32 v); +u32 nvhost_device_readl(struct platform_device *dev, u32 r); + +/* public host1x power management APIs */ +bool nvhost_module_powered_ext(struct platform_device *dev); +void nvhost_module_busy_ext(struct platform_device *dev); +void nvhost_module_idle_ext(struct platform_device *dev); + +/* public host1x sync-point management APIs */ +u32 nvhost_syncpt_incr_max_ext(struct platform_device *dev, u32 id, u32 incrs); +void nvhost_syncpt_cpu_incr_ext(struct platform_device *dev, u32 id); +u32 nvhost_syncpt_read_ext(struct platform_device *dev, u32 id); +int nvhost_syncpt_wait_timeout_ext(struct platform_device *dev, u32 id, u32 thresh, + u32 timeout, u32 *value); + +void nvhost_scale3d_set_throughput_hint(int hint); + +#endif diff --git a/include/linux/nvhost_ioctl.h b/include/linux/nvhost_ioctl.h new file mode 100644 index 000000000000..6395c28d3166 --- /dev/null +++ b/include/linux/nvhost_ioctl.h @@ -0,0 +1,298 @@ +/* + * include/linux/nvhost_ioctl.h + * + * Tegra graphics host driver + * + * Copyright (c) 2009-2013, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_IOCTL_H +#define __LINUX_NVHOST_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#if !defined(__KERNEL__) +#define __user +#endif + +#define NVHOST_INVALID_SYNCPOINT 0xFFFFFFFF +#define NVHOST_NO_TIMEOUT (-1) +#define NVHOST_NO_CONTEXT 0x0 +#define NVHOST_IOCTL_MAGIC 'H' +#define NVHOST_PRIORITY_LOW 50 +#define NVHOST_PRIORITY_MEDIUM 100 +#define NVHOST_PRIORITY_HIGH 150 + +#define NVHOST_TIMEOUT_FLAG_DISABLE_DUMP 0 + +/* version 0 header (used with write() submit interface) */ +struct nvhost_submit_hdr { + __u32 syncpt_id; + __u32 syncpt_incrs; + __u32 num_cmdbufs; + __u32 num_relocs; +}; + +#define NVHOST_SUBMIT_VERSION_V0 0x0 +#define NVHOST_SUBMIT_VERSION_V1 0x1 +#define NVHOST_SUBMIT_VERSION_V2 0x2 +#define NVHOST_SUBMIT_VERSION_MAX_SUPPORTED NVHOST_SUBMIT_VERSION_V2 + +/* version 1 header (used with ioctl() submit interface) */ +struct nvhost_submit_hdr_ext { + __u32 syncpt_id; /* version 0 fields */ + __u32 syncpt_incrs; + __u32 num_cmdbufs; + __u32 num_relocs; + __u32 submit_version; /* version 1 fields */ + __u32 num_waitchks; + __u32 waitchk_mask; + __u32 pad[5]; /* future expansion */ +}; + +struct nvhost_cmdbuf { + __u32 mem; + __u32 offset; + __u32 words; +}; + +struct nvhost_reloc { + __u32 cmdbuf_mem; + __u32 cmdbuf_offset; + __u32 target; + __u32 target_offset; +}; + +struct nvhost_reloc_shift { + __u32 shift; +}; + +struct nvhost_waitchk { + __u32 mem; + __u32 offset; + __u32 syncpt_id; + __u32 thresh; +}; + +struct nvhost_syncpt_incr { + __u32 syncpt_id; + __u32 syncpt_incrs; +}; + +struct nvhost_get_param_args { + __u32 value; +}; + +struct nvhost_get_param_arg { + __u32 param; + __u32 value; +}; + +struct nvhost_set_nvmap_fd_args { + __u32 fd; +}; + +struct nvhost_read_3d_reg_args { + __u32 offset; + __u32 value; +}; + +enum nvhost_clk_attr { + NVHOST_CLOCK = 0, + NVHOST_BW, +}; + +/* + * moduleid[15:0] => module id + * moduleid[24:31] => nvhost_clk_attr + */ +#define NVHOST_MODULE_ID_BIT_POS 0 +#define NVHOST_MODULE_ID_BIT_WIDTH 16 +#define NVHOST_CLOCK_ATTR_BIT_POS 24 +#define NVHOST_CLOCK_ATTR_BIT_WIDTH 8 +struct nvhost_clk_rate_args { + __u32 rate; + __u32 moduleid; +}; + +struct nvhost_set_timeout_args { + __u32 timeout; +}; + +struct nvhost_set_timeout_ex_args { + __u32 timeout; + __u32 flags; +}; + +struct nvhost_set_priority_args { + __u32 priority; +}; + +struct nvhost_ctrl_module_regrdwr_args { + __u32 id; + __u32 num_offsets; + __u32 block_size; + __u32 *offsets; + __u32 *values; + __u32 write; +}; + +struct nvhost_submit_args { + __u32 submit_version; + __u32 num_syncpt_incrs; + __u32 num_cmdbufs; + __u32 num_relocs; + __u32 num_waitchks; + __u32 timeout; + struct nvhost_syncpt_incr *syncpt_incrs; + struct nvhost_cmdbuf *cmdbufs; + struct nvhost_reloc *relocs; + struct nvhost_reloc_shift *reloc_shifts; + struct nvhost_waitchk *waitchks; + + __u32 pad[5]; /* future expansion */ + __u32 fence; /* Return value */ +}; + +struct nvhost_set_ctxswitch_args { + __u32 num_cmdbufs_save; + __u32 num_save_incrs; + struct nvhost_syncpt_incr *save_incrs; + __u32 *save_waitbases; + struct nvhost_cmdbuf *cmdbuf_save; + __u32 num_cmdbufs_restore; + __u32 num_restore_incrs; + struct nvhost_syncpt_incr *restore_incrs; + __u32 *restore_waitbases; + struct nvhost_cmdbuf *cmdbuf_restore; + __u32 num_relocs; + struct nvhost_reloc *relocs; + struct nvhost_reloc_shift *reloc_shifts; + + __u32 pad; +}; + +#define NVHOST_IOCTL_CHANNEL_FLUSH \ + _IOR(NVHOST_IOCTL_MAGIC, 1, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS \ + _IOR(NVHOST_IOCTL_MAGIC, 2, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_WAITBASES \ + _IOR(NVHOST_IOCTL_MAGIC, 3, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEXES \ + _IOR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD \ + _IOW(NVHOST_IOCTL_MAGIC, 5, struct nvhost_set_nvmap_fd_args) +#define NVHOST_IOCTL_CHANNEL_NULL_KICKOFF \ + _IOR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SUBMIT_EXT \ + _IOW(NVHOST_IOCTL_MAGIC, 7, struct nvhost_submit_hdr_ext) +#define NVHOST_IOCTL_CHANNEL_READ_3D_REG \ + _IOWR(NVHOST_IOCTL_MAGIC, 8, struct nvhost_read_3d_reg_args) +#define NVHOST_IOCTL_CHANNEL_GET_CLK_RATE \ + _IOR(NVHOST_IOCTL_MAGIC, 9, struct nvhost_clk_rate_args) +#define NVHOST_IOCTL_CHANNEL_SET_CLK_RATE \ + _IOW(NVHOST_IOCTL_MAGIC, 10, struct nvhost_clk_rate_args) +#define NVHOST_IOCTL_CHANNEL_SET_TIMEOUT \ + _IOW(NVHOST_IOCTL_MAGIC, 11, struct nvhost_set_timeout_args) +#define NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT \ + _IOR(NVHOST_IOCTL_MAGIC, 12, struct nvhost_get_param_args) +#define NVHOST_IOCTL_CHANNEL_SET_PRIORITY \ + _IOW(NVHOST_IOCTL_MAGIC, 13, struct nvhost_set_priority_args) +#define NVHOST_IOCTL_CHANNEL_MODULE_REGRDWR \ + _IOWR(NVHOST_IOCTL_MAGIC, 14, struct nvhost_ctrl_module_regrdwr_args) +#define NVHOST_IOCTL_CHANNEL_SUBMIT \ + _IOWR(NVHOST_IOCTL_MAGIC, 15, struct nvhost_submit_args) +#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT \ + _IOWR(NVHOST_IOCTL_MAGIC, 16, struct nvhost_get_param_arg) +#define NVHOST_IOCTL_CHANNEL_GET_WAITBASE \ + _IOWR(NVHOST_IOCTL_MAGIC, 17, struct nvhost_get_param_arg) +#define NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX \ + _IOWR(NVHOST_IOCTL_MAGIC, 18, struct nvhost_set_timeout_ex_args) +#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEX \ + _IOWR(NVHOST_IOCTL_MAGIC, 23, struct nvhost_get_param_arg) +#define NVHOST_IOCTL_CHANNEL_SET_CTXSWITCH \ + _IOWR(NVHOST_IOCTL_MAGIC, 25, struct nvhost_set_ctxswitch_args) +#define NVHOST_IOCTL_CHANNEL_LAST \ + _IOC_NR(NVHOST_IOCTL_CHANNEL_SET_CTXSWITCH) +#define NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvhost_submit_args) + +struct nvhost_ctrl_syncpt_read_args { + __u32 id; + __u32 value; +}; + +struct nvhost_ctrl_syncpt_incr_args { + __u32 id; +}; + +struct nvhost_ctrl_syncpt_wait_args { + __u32 id; + __u32 thresh; + __s32 timeout; +}; + +struct nvhost_ctrl_syncpt_waitex_args { + __u32 id; + __u32 thresh; + __s32 timeout; + __u32 value; +}; + +struct nvhost_ctrl_module_mutex_args { + __u32 id; + __u32 lock; +}; + +enum nvhost_module_id { + NVHOST_MODULE_NONE = -1, + NVHOST_MODULE_DISPLAY_A = 0, + NVHOST_MODULE_DISPLAY_B, + NVHOST_MODULE_VI, + NVHOST_MODULE_ISP, + NVHOST_MODULE_MPE, + NVHOST_MODULE_MSENC, + NVHOST_MODULE_TSEC, +}; + +#define NVHOST_IOCTL_CTRL_SYNCPT_READ \ + _IOWR(NVHOST_IOCTL_MAGIC, 1, struct nvhost_ctrl_syncpt_read_args) +#define NVHOST_IOCTL_CTRL_SYNCPT_INCR \ + _IOW(NVHOST_IOCTL_MAGIC, 2, struct nvhost_ctrl_syncpt_incr_args) +#define NVHOST_IOCTL_CTRL_SYNCPT_WAIT \ + _IOW(NVHOST_IOCTL_MAGIC, 3, struct nvhost_ctrl_syncpt_wait_args) + +#define NVHOST_IOCTL_CTRL_MODULE_MUTEX \ + _IOWR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_ctrl_module_mutex_args) +#define NVHOST_IOCTL_CTRL_MODULE_REGRDWR \ + _IOWR(NVHOST_IOCTL_MAGIC, 5, struct nvhost_ctrl_module_regrdwr_args) + +#define NVHOST_IOCTL_CTRL_SYNCPT_WAITEX \ + _IOWR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_ctrl_syncpt_waitex_args) + +#define NVHOST_IOCTL_CTRL_GET_VERSION \ + _IOR(NVHOST_IOCTL_MAGIC, 7, struct nvhost_get_param_args) + +#define NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX \ + _IOWR(NVHOST_IOCTL_MAGIC, 8, struct nvhost_ctrl_syncpt_read_args) + +#define NVHOST_IOCTL_CTRL_LAST \ + _IOC_NR(NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX) +#define NVHOST_IOCTL_CTRL_MAX_ARG_SIZE \ + sizeof(struct nvhost_ctrl_module_regrdwr_args) + +#endif diff --git a/include/linux/nvmap.h b/include/linux/nvmap.h new file mode 100644 index 000000000000..12949e70b248 --- /dev/null +++ b/include/linux/nvmap.h @@ -0,0 +1,179 @@ +/* + * include/linux/nvmap.h + * + * structure declarations for nvmem and nvmap user-space ioctls + * + * Copyright (c) 2009-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/ioctl.h> +#include <linux/file.h> +#include <linux/rbtree.h> +#include <linux/dma-buf.h> + +#if !defined(__KERNEL__) +#define __user +#endif + +#ifndef _LINUX_NVMAP_H +#define _LINUX_NVMAP_H + +#define NVMAP_HEAP_SYSMEM (1ul<<31) +#define NVMAP_HEAP_IOVMM (1ul<<30) + +/* common carveout heaps */ +#define NVMAP_HEAP_CARVEOUT_IRAM (1ul<<29) +#define NVMAP_HEAP_CARVEOUT_VPR (1ul<<28) +#define NVMAP_HEAP_CARVEOUT_TSEC (1ul<<27) +#define NVMAP_HEAP_CARVEOUT_GENERIC (1ul<<0) + +#define NVMAP_HEAP_CARVEOUT_MASK (NVMAP_HEAP_IOVMM - 1) + +/* allocation flags */ +#define NVMAP_HANDLE_UNCACHEABLE (0x0ul << 0) +#define NVMAP_HANDLE_WRITE_COMBINE (0x1ul << 0) +#define NVMAP_HANDLE_INNER_CACHEABLE (0x2ul << 0) +#define NVMAP_HANDLE_CACHEABLE (0x3ul << 0) +#define NVMAP_HANDLE_CACHE_FLAG (0x3ul << 0) + +#define NVMAP_HANDLE_SECURE (0x1ul << 2) +#define NVMAP_HANDLE_ZEROED_PAGES (0x1ul << 3) + +#if defined(__KERNEL__) + +#if defined(CONFIG_TEGRA_NVMAP) +struct nvmap_handle; +struct nvmap_client; +struct nvmap_device; + +#define nvmap_ref_to_handle(_ref) (*(struct nvmap_handle **)(_ref)) +/* Convert User space handle to Kernel. */ +#define nvmap_convert_handle_u2k(h) (h) + +/* handle_ref objects are client-local references to an nvmap_handle; + * they are distinct objects so that handles can be unpinned and + * unreferenced the correct number of times when a client abnormally + * terminates */ +struct nvmap_handle_ref { + struct nvmap_handle *handle; + struct rb_node node; + atomic_t dupes; /* number of times to free on file close */ + atomic_t pin; /* number of times to unpin on free */ +}; + +#elif defined(CONFIG_ION_TEGRA) +/* For Ion Mem Manager support through nvmap_* API's. */ +#include "../../../../../drivers/gpu/ion/ion_priv.h" +#define nvmap_client ion_client +#define nvmap_device ion_device +#define nvmap_handle ion_handle +#define nvmap_handle_ref ion_handle +#define nvmap_ref_to_handle(_ref) (struct ion_handle *)_ref +/* Convert User space handle to Kernel. */ +#define nvmap_convert_handle_u2k(h) ({ \ + if ((u32)h >= TASK_SIZE) { \ + pr_err("Invalid user space handle."); \ + BUG(); \ + } \ + (*((u32 *)h)); }) + +#endif /* CONFIG_ION_TEGRA */ + +#define nvmap_id_to_handle(_id) ((struct nvmap_handle *)(_id)) + +struct nvmap_client *nvmap_create_client(struct nvmap_device *dev, + const char *name); + +struct nvmap_handle_ref *nvmap_alloc(struct nvmap_client *client, size_t size, + size_t align, unsigned int flags, + unsigned int heap_mask); + +phys_addr_t _nvmap_get_addr_from_id(u32 id); + +void nvmap_free(struct nvmap_client *client, struct nvmap_handle_ref *r); + +void _nvmap_free(struct nvmap_client *client, struct nvmap_handle_ref *r); + +void *nvmap_mmap(struct nvmap_handle_ref *r); + +void nvmap_munmap(struct nvmap_handle_ref *r, void *addr); + +void *nvmap_kmap(struct nvmap_handle_ref *r, unsigned int pagenum); + +void nvmap_kunmap(struct nvmap_handle_ref *r, unsigned int pagenum, + void *addr); + +struct nvmap_client *nvmap_client_get_file(int fd); + +struct nvmap_client *nvmap_client_get(struct nvmap_client *client); + +void nvmap_client_put(struct nvmap_client *c); + +phys_addr_t nvmap_pin(struct nvmap_client *c, struct nvmap_handle_ref *r); +phys_addr_t _nvmap_pin(struct nvmap_client *c, struct nvmap_handle_ref *r); + + +phys_addr_t nvmap_handle_address(struct nvmap_client *c, unsigned long id); + +void nvmap_unpin(struct nvmap_client *client, struct nvmap_handle_ref *r); + +void nvmap_unpin_handles(struct nvmap_client *client, + struct nvmap_handle **h, int nr); + +struct nvmap_handle_ref *nvmap_duplicate_handle_id(struct nvmap_client *client, + unsigned long id); +struct nvmap_handle_ref *_nvmap_duplicate_handle_id(struct nvmap_client *client, + unsigned long id); + +int nvmap_pin_array(struct nvmap_client *client, + unsigned long *ids, + long unsigned id_type_mask, + long unsigned id_type, + int nr, + struct nvmap_handle **unique_arr, + struct nvmap_handle_ref **unique_arr_refs); + + +struct nvmap_platform_carveout { + const char *name; + unsigned int usage_mask; + phys_addr_t base; + size_t size; + size_t buddy_size; +}; + +struct nvmap_platform_data { + const struct nvmap_platform_carveout *carveouts; + unsigned int nr_carveouts; +}; + +extern struct nvmap_device *nvmap_dev; + +#ifdef CONFIG_DMA_SHARED_BUFFER +/* dma-buf exporter */ +struct dma_buf *nvmap_share_dmabuf(struct nvmap_client *client, u32 id); +#else +static inline struct dma_buf *nvmap_share_dmabuf(struct nvmap_client *client, + u32 id) +{ + return NULL; +} +#endif /* !CONFIG_DMA_SHARED_BUFFER */ + +#endif /* __KERNEL__ */ + +#endif /* _LINUX_NVMAP_H */ diff --git a/include/linux/platform_data/ina230.h b/include/linux/platform_data/ina230.h new file mode 100644 index 000000000000..8fb86bdf4473 --- /dev/null +++ b/include/linux/platform_data/ina230.h @@ -0,0 +1,39 @@ +/* + * include/linux/platform_data/ina230.h + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _INA230_H +#define _INA230_H + +#include <linux/types.h> + +#define INA3221_RAIL_NAME_SIZE 32 + +struct ina230_platform_data { + const char rail_name[INA3221_RAIL_NAME_SIZE]; + s32 current_threshold; + s32 resistor; + s32 min_cores_online; + u32 calibration_data; + u32 power_lsb; + u16 divisor; + u32 shunt_resistor; + u32 precision_multiplier; +}; + +#endif /* _INA230_H */ diff --git a/include/linux/platform_data/mmc-sdhci-tegra.h b/include/linux/platform_data/mmc-sdhci-tegra.h new file mode 100644 index 000000000000..46bcf8e60f52 --- /dev/null +++ b/include/linux/platform_data/mmc-sdhci-tegra.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2009 Palm, Inc. + * Author: Yvonne Yip <y@palm.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __PLATFORM_DATA_TEGRA_SDHCI_H +#define __PLATFORM_DATA_TEGRA_SDHCI_H + +#include <linux/mmc/host.h> +#include <asm/mach/mmc.h> + +/* + * MMC_OCR_1V8_MASK will be used in board sdhci file + * Example for cardhu it will be used in board-cardhu-sdhci.c + * for built_in = 0 devices enabling ocr_mask to MMC_OCR_1V8_MASK + * sets the voltage to 1.8V + */ +#define MMC_OCR_1V8_MASK 0x00000008 +#define MMC_OCR_2V8_MASK 0x00010000 + +/* uhs mask can be used to mask any of the UHS modes support */ +#define MMC_UHS_MASK_SDR25 1 +#define MMC_UHS_MASK_SDR50 2 +#define MMC_UHS_MASK_DDR50 4 +#define MMC_UHS_MASK_SDR104 8 + +struct tegra_sdhci_platform_data { + int cd_gpio; + int wp_gpio; + int power_gpio; + int is_8bit; + int pm_flags; + int pm_caps; + unsigned int max_clk_limit; + unsigned int ddr_clk_limit; + unsigned int trim_delay; + unsigned int uhs_mask; + unsigned int base_clk; + struct mmc_platform_data mmc_data; +}; + +#endif diff --git a/include/linux/platform_data/pwm_fan.h b/include/linux/platform_data/pwm_fan.h new file mode 100644 index 000000000000..8bc5b4e94f16 --- /dev/null +++ b/include/linux/platform_data/pwm_fan.h @@ -0,0 +1,37 @@ +/* + * include/linux/platform_data/pwm_fan.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _PWM_FAN_H_ +#define _PWM_FAN_H_ + +#define MAX_ACTIVE_STATES 10 + +struct pwm_fan_platform_data { + int active_steps; + int active_rpm[MAX_ACTIVE_STATES]; + int active_pwm[MAX_ACTIVE_STATES]; + int active_rru[MAX_ACTIVE_STATES]; + int active_rrd[MAX_ACTIVE_STATES]; + int pwm_cap; + int pwm_period; + int active_temps[MAX_ACTIVE_STATES]; + int pwm_id; + int step_time; + int precision_multiplier; +}; +#endif diff --git a/include/linux/platform_data/tegra30_emc.h b/include/linux/platform_data/tegra30_emc.h new file mode 100644 index 000000000000..f005755153b8 --- /dev/null +++ b/include/linux/platform_data/tegra30_emc.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2011 Google, Inc. + * Copyright (C) 2011 NVIDIA Corporation + * + * Author: + * Colin Cross <ccross@android.com> + * Olof Johansson <olof@lixom.net> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA_EMC_H_ +#define __TEGRA_EMC_H_ + +#define TEGRA_EMC_NUM_REGS 110 + +struct tegra30_emc_table { + u8 rev; + unsigned long rate; + + /* unconditionally updated in one burst shot */ + u32 burst_regs[TEGRA_EMC_NUM_REGS]; + + /* updated separately under some conditions */ + u32 emc_zcal_cnt_long; + u32 emc_acal_interval; + u32 emc_periodic_qrst; + u32 emc_mode_reset; + u32 emc_mode_1; + u32 emc_mode_2; + u32 emc_dsr; + int emc_min_mv; +}; + +struct tegra30_emc_pdata { + int num_tables; + const struct tegra30_emc_table *tables; +}; + +#endif diff --git a/include/linux/platform_data/tegra_bpc_mgmt.h b/include/linux/platform_data/tegra_bpc_mgmt.h new file mode 100644 index 000000000000..bdd4862d63a3 --- /dev/null +++ b/include/linux/platform_data/tegra_bpc_mgmt.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2010-2011 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA_BPC_MGMT_H +#define __TEGRA_BPC_MGMT_H +#include <linux/cpumask.h> + +struct tegra_bpc_mgmt_platform_data { + int gpio_trigger; + struct cpumask affinity_mask; + int bpc_mgmt_timeout; +}; + +#endif /*__TEGRA_BPC_MGMT_H*/ diff --git a/include/linux/platform_data/tegra_emc.h b/include/linux/platform_data/tegra_emc.h index df67505e98f8..aaf8ac34f839 100644 --- a/include/linux/platform_data/tegra_emc.h +++ b/include/linux/platform_data/tegra_emc.h @@ -26,9 +26,20 @@ struct tegra_emc_table { u32 regs[TEGRA_EMC_NUM_REGS]; }; -struct tegra_emc_pdata { +struct tegra_emc_chip { + const char *description; + int mem_manufacturer_id; /* LPDDR2 MR5 or -1 to ignore */ + int mem_revision_id1; /* LPDDR2 MR6 or -1 to ignore */ + int mem_revision_id2; /* LPDDR2 MR7 or -1 to ignore */ + int mem_pid; /* LPDDR2 MR8 or -1 to ignore */ + int num_tables; struct tegra_emc_table *tables; }; +struct tegra_emc_pdata { + int num_chips; + struct tegra_emc_chip *chips; +}; + #endif diff --git a/include/linux/platform_data/tegra_nor.h b/include/linux/platform_data/tegra_nor.h new file mode 100644 index 000000000000..78105c32ae27 --- /dev/null +++ b/include/linux/platform_data/tegra_nor.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2010-2013, NVIDIA Corporation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * include/linux/platform_data/tegra_nor.h + * + * Author: + * Raghavendra V K <rvk@nvidia.com> + * + */ + +#ifndef __MACH_TEGRA_NOR_PDATA_H +#define __MACH_TEGRA_NOR_PDATA_H + +#include <asm/mach/flash.h> + +typedef enum { + NorMuxMode_ADNonMux, + NorMuxMode_ADMux, +} NorMuxMode; + +typedef enum { + NorPageLength_Unsupported, + NorPageLength_4Word, + NorPageLength_8Word, + NorPageLength_16Word, +} NorPageLength; + +typedef enum { + NorBurstLength_CntBurst, + NorBurstLength_8Word, + NorBurstLength_16Word, + NorBurstLength_32Word, +} NorBurstLength; + +typedef enum { + NorReadMode_Async, + NorReadMode_Page, + NorReadMode_Burst, +} NorReadMode; + +typedef enum { + NorReadyActive_WithData, + NorReadyActive_BeforeData, +} NorReadyActive; + +/* Signal values*/ +enum SIGNAL { + LOW, + HIGH +}; + +/* Mapping of CS and signal*/ +struct gpio_state { + char *label; + int gpio_num; /* GPIO number which is CS*/ + enum SIGNAL value; /* Signal value of CS pin to set */ +}; + +enum CS { + CS_0, + CS_1, + CS_2, + CS_3, + CS_4, + CS_5, + CS_6, + CS_7 +}; + +/* All params required for map_info passed*/ +struct cs_info { + enum CS cs; + struct gpio_state gpio_cs; + int num_cs_gpio; + void __iomem *virt; /* Virtual address of chip select window */ + resource_size_t phys; /* Physical address of chip select window */ + unsigned int size; /* size of chip select window */ +}; +struct tegra_nor_chip_parms { + struct { + uint32_t timing0; + uint32_t timing1; + } timing_default, timing_read; + NorMuxMode MuxMode; + NorReadMode ReadMode; + NorPageLength PageLength; + NorBurstLength BurstLength; + NorReadyActive ReadyActive; + unsigned int BusWidth; + struct cs_info csinfo; +}; +struct flash_info { + struct cs_info *cs; + unsigned int num_chips; +}; + +/* Container having cs_info and number of such mappings*/ +struct gpio_addr { + int gpio_num; /* GPIO number of address line */ + int line_num; /* address line number starting from 0 */ +}; + +struct gpio_addr_info { + struct gpio_addr *addr; + unsigned int num_gpios; +}; + +struct tegra_nor_platform_data { + struct tegra_nor_chip_parms chip_parms; + struct flash_platform_data flash; + struct flash_info info; + struct gpio_addr_info addr; +}; + +#endif /* __MACH_TEGRA_NOR_PDATA_H */ diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h index 66c673fef408..f075b9cb8985 100644 --- a/include/linux/platform_data/tegra_usb.h +++ b/include/linux/platform_data/tegra_usb.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2011 NVIDIA Corporation. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,18 +16,134 @@ #ifndef _TEGRA_USB_H_ #define _TEGRA_USB_H_ -enum tegra_usb_operating_modes { - TEGRA_USB_DEVICE, - TEGRA_USB_HOST, - TEGRA_USB_OTG, +/** + * defines operation mode of the USB controller + */ +enum tegra_usb_operation_mode { + TEGRA_USB_OPMODE_DEVICE, + TEGRA_USB_OPMODE_HOST, +}; + +/** + * defines the various phy interface mode supported by controller + */ +enum tegra_usb_phy_interface { + TEGRA_USB_PHY_INTF_UTMI = 0, + TEGRA_USB_PHY_INTF_ULPI_LINK = 1, + TEGRA_USB_PHY_INTF_ULPI_NULL = 2, + TEGRA_USB_PHY_INTF_HSIC = 3, + TEGRA_USB_PHY_INTF_ICUSB = 4, +}; + +/** + * configuration structure for setting up utmi phy + */ +struct tegra_utmi_config { + u8 hssync_start_delay; + u8 elastic_limit; + u8 idle_wait_delay; + u8 term_range_adj; + u8 xcvr_setup; + u8 xcvr_lsfslew; + u8 xcvr_lsrslew; + signed char xcvr_setup_offset; + u8 xcvr_use_lsb; + u8 xcvr_use_fuses; +}; + +/** + * configuration structure for setting up ulpi phy + */ +struct tegra_ulpi_config { + u8 shadow_clk_delay; + u8 clock_out_delay; + u8 data_trimmer; + u8 stpdirnxt_trimmer; + u8 dir_trimmer; + const char *clk; +}; + +/** + * configuration structure for setting up hsic phy + */ +struct tegra_hsic_config { + u8 sync_start_delay; + u8 idle_wait_delay; + u8 term_range_adj; + u8 elastic_underrun_limit; + u8 elastic_overrun_limit; +}; + +/** + * Platform specific operations that will be controlled + * during the phy operations. + */ +struct tegra_usb_phy_platform_ops { + void (*open)(void); + void (*init)(void); + void (*pre_suspend)(void); + void (*post_suspend)(void); + void (*pre_resume)(void); + void (*post_resume)(void); + void (*pre_phy_off)(void); + void (*post_phy_off)(void); + void (*pre_phy_on)(void); + void (*post_phy_on)(void); + void (*port_power)(void); + void (*close)(void); +}; + +/** + * defines structure for platform dependent device parameters + */ +struct tegra_usb_dev_mode_data { + int vbus_pmu_irq; + int vbus_gpio; + bool charging_supported; + bool remote_wakeup_supported; }; -struct tegra_ehci_platform_data { - enum tegra_usb_operating_modes operating_mode; - /* power down the phy on bus suspend */ - int power_down_on_bus_suspend; - void *phy_config; +/** + * defines structure for platform dependent host parameters + */ +struct tegra_usb_host_mode_data { int vbus_gpio; + const char *vbus_reg; + bool hot_plug; + bool remote_wakeup_supported; + bool power_off_on_suspend; +}; + +/** + * defines structure for usb platform data + */ +struct tegra_usb_platform_data { + bool port_otg; + bool has_hostpc; + bool builtin_host_disabled; + enum tegra_usb_phy_interface phy_intf; + enum tegra_usb_operation_mode op_mode; + + union { + struct tegra_usb_dev_mode_data dev; + struct tegra_usb_host_mode_data host; + } u_data; + + union { + struct tegra_utmi_config utmi; + struct tegra_ulpi_config ulpi; + struct tegra_hsic_config hsic; + } u_cfg; + + struct tegra_usb_phy_platform_ops *ops; +}; + +/** + * defines structure for platform dependent OTG parameters + */ +struct tegra_usb_otg_data { + struct platform_device *ehci_device; + struct tegra_usb_platform_data *ehci_pdata; }; #endif /* _TEGRA_USB_H_ */ diff --git a/include/linux/pm_qos.h b/include/linux/pm_qos.h index 5a95013905c8..fa11e5648959 100644 --- a/include/linux/pm_qos.h +++ b/include/linux/pm_qos.h @@ -15,6 +15,10 @@ enum { PM_QOS_CPU_DMA_LATENCY, PM_QOS_NETWORK_LATENCY, PM_QOS_NETWORK_THROUGHPUT, + PM_QOS_MIN_ONLINE_CPUS, + PM_QOS_MAX_ONLINE_CPUS, + PM_QOS_CPU_FREQ_MIN, + PM_QOS_CPU_FREQ_MAX, /* insert new class ID */ PM_QOS_NUM_CLASSES, @@ -32,6 +36,10 @@ enum pm_qos_flags_status { #define PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) #define PM_QOS_NETWORK_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) #define PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE 0 +#define PM_QOS_MIN_ONLINE_CPUS_DEFAULT_VALUE 0 +#define PM_QOS_MAX_ONLINE_CPUS_DEFAULT_VALUE LONG_MAX +#define PM_QOS_CPU_FREQ_MIN_DEFAULT_VALUE 0 +#define PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE LONG_MAX #define PM_QOS_DEV_LAT_DEFAULT_VALUE 0 #define PM_QOS_FLAG_NO_POWER_OFF (1 << 0) diff --git a/include/linux/power/max8907c-charger.h b/include/linux/power/max8907c-charger.h new file mode 100644 index 000000000000..2cebad768b0d --- /dev/null +++ b/include/linux/power/max8907c-charger.h @@ -0,0 +1,64 @@ +/* linux/power/max8907c-charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MAX8907C_CHARGER_H +#define __LINUX_MAX8907C_CHARGER_H + +/* interrupt */ +#define MAX8907C_VCHG_OVP (1 << 0) +#define MAX8907C_VCHG_F (1 << 1) +#define MAX8907C_VCHG_R (1 << 2) +#define MAX8907C_THM_OK_R (1 << 8) +#define MAX8907C_THM_OK_F (1 << 9) +#define MAX8907C_MBATTLOW_F (1 << 10) +#define MAX8907C_MBATTLOW_R (1 << 11) +#define MAX8907C_CHG_RST (1 << 12) +#define MAX8907C_CHG_DONE (1 << 13) +#define MAX8907C_CHG_TOPOFF (1 << 14) +#define MAX8907C_CHK_TMR_FAULT (1 << 15) + +enum max8907c_charger_topoff_threshold { + MAX8907C_TOPOFF_5PERCENT = 0x00, + MAX8907C_TOPOFF_10PERCENT = 0x01, + MAX8907C_TOPOFF_15PERCENT = 0x02, + MAX8907C_TOPOFF_20PERCENT = 0x03, +}; + +enum max8907c_charger_restart_hysteresis { + MAX8907C_RESTART_100MV = 0x00, + MAX8907C_RESTART_150MV = 0x01, + MAX8907C_RESTART_200MV = 0x02, + MAX8907C_RESTART_FLOAT = 0x03, +}; + +enum max8907c_fast_charging_current { + MAX8907C_FASTCHARGE_90MA = 0x00, + MAX8907C_FASTCHARGE_300MA = 0x01, + MAX8907C_FASTCHARGE_460MA = 0x02, + MAX8907C_FASTCHARGE_600MA = 0x03, + MAX8907C_FASTCHARGE_700MA = 0x04, + MAX8907C_FASTCHARGE_800MA = 0x05, + MAX8907C_FASTCHARGE_900MA = 0x06, + MAX8907C_FASTCHARGE_1000MA = 0x07, +}; + +enum max8907c_fast_charger_time { + MAX8907C_FCHARGE_TM_8H = 0x00, + MAX8907C_FCHARGE_TM_12H = 0x01, + MAX8907C_FCHARGE_TM_16H = 0x02, + MAX8907C_FCHARGE_TM_OFF = 0x03, +}; + +struct max8907c_charger_pdata { + int irq; + enum max8907c_charger_topoff_threshold topoff_threshold; + enum max8907c_charger_restart_hysteresis restart_hysteresis; + enum max8907c_charger_restart_hysteresis fast_charging_current; + enum max8907c_fast_charger_time fast_charger_time; +}; + +#endif diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 02d84e24b7c2..f91bb416122d 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -15,6 +15,7 @@ #include <linux/list.h> #include <linux/rbtree.h> +#include <linux/err.h> struct module; struct device; diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index 145022a83085..a098c91abf0a 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -2,6 +2,7 @@ * consumer.h -- SoC Regulator consumer support. * * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. + * Copyright (C) 2012 NVIDIA Corporation * * Author: Liam Girdwood <lrg@slimlogic.co.uk> * @@ -93,6 +94,10 @@ struct notifier_block; * FORCE_DISABLE Regulator forcibly shut down by software. * VOLTAGE_CHANGE Regulator voltage changed. * DISABLE Regulator was disabled. + * PRE_ENABLE Regulator is to be enabled + * POST_ENABLE Regulator was enabled + * OUT_PRECHANGE Regulator is enabled and its voltage is to be changed + * OUT_POSTCHANGE Regulator is enabled and its voltage was changed * * NOTE: These events can be OR'ed together when passed into handler. */ @@ -105,6 +110,10 @@ struct notifier_block; #define REGULATOR_EVENT_FORCE_DISABLE 0x20 #define REGULATOR_EVENT_VOLTAGE_CHANGE 0x40 #define REGULATOR_EVENT_DISABLE 0x80 +#define REGULATOR_EVENT_PRE_ENABLE 0x100 +#define REGULATOR_EVENT_POST_ENABLE 0x200 +#define REGULATOR_EVENT_OUT_PRECHANGE 0x400 +#define REGULATOR_EVENT_OUT_POSTCHANGE 0x800 struct regulator; @@ -216,6 +225,13 @@ devm_regulator_get(struct device *dev, const char *id) return NULL; } +static inline struct regulator *__must_check regulator_get_exclusive( + struct device *dev, const char *id) +{ + /* See comment for regulator_get() stub, above */ + return NULL; +} + static inline void regulator_put(struct regulator *regulator) { } @@ -245,6 +261,11 @@ static inline int regulator_disable_deferred(struct regulator *regulator, return 0; } +static inline int regulator_force_disable(struct regulator *regulator) +{ + return 0; +} + static inline int regulator_is_enabled(struct regulator *regulator) { return 1; @@ -286,12 +307,35 @@ static inline void regulator_bulk_free(int num_consumers, { } +static inline int regulator_count_voltages(struct regulator *regulator) +{ + return 0; +} + +static inline int regulator_list_voltage(struct regulator *regulator, + unsigned selector) +{ + return 0; +} + +static inline int regulator_is_supported_voltage(struct regulator *regulator, + int min_uV, int max_uV) +{ + return 0; +} + static inline int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV) { return 0; } +static inline int regulator_set_voltage_time(struct regulator *regulator, + int old_uV, int new_uV) +{ + return 0; +} + static inline int regulator_get_voltage(struct regulator *regulator) { return -EINVAL; @@ -303,6 +347,11 @@ static inline int regulator_is_supported_voltage(struct regulator *regulator, return 0; } +static inline int regulator_sync_voltage(struct regulator *regulator) +{ + return 0; +} + static inline int regulator_set_current_limit(struct regulator *regulator, int min_uA, int max_uA) { diff --git a/include/linux/regulator/max77663-regulator.h b/include/linux/regulator/max77663-regulator.h new file mode 100644 index 000000000000..f5beed5b30d5 --- /dev/null +++ b/include/linux/regulator/max77663-regulator.h @@ -0,0 +1,129 @@ +/* + * include/linux/regulator/max77663-regulator.h + * Maxim LDO and Buck regulators driver + * + * Copyright 2011-2012 Maxim Integrated Products, Inc. + * Copyright (C) 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_REGULATOR_MAX77663_REGULATOR_H__ +#define __LINUX_REGULATOR_MAX77663_REGULATOR_H__ + +#include <linux/regulator/machine.h> + +#define max77663_rails(_name) "max77663_"#_name + +enum max77663_regulator_id { + MAX77663_REGULATOR_ID_SD0, + MAX77663_REGULATOR_ID_DVSSD0, + MAX77663_REGULATOR_ID_SD1, + MAX77663_REGULATOR_ID_DVSSD1, + MAX77663_REGULATOR_ID_SD2, + MAX77663_REGULATOR_ID_SD3, + MAX77663_REGULATOR_ID_SD4, + MAX77663_REGULATOR_ID_LDO0, + MAX77663_REGULATOR_ID_LDO1, + MAX77663_REGULATOR_ID_LDO2, + MAX77663_REGULATOR_ID_LDO3, + MAX77663_REGULATOR_ID_LDO4, + MAX77663_REGULATOR_ID_LDO5, + MAX77663_REGULATOR_ID_LDO6, + MAX77663_REGULATOR_ID_LDO7, + MAX77663_REGULATOR_ID_LDO8, + MAX77663_REGULATOR_ID_NR, +}; + +/* FPS Power Up/Down Period */ +enum max77663_regulator_fps_power_period { + FPS_POWER_PERIOD_0, + FPS_POWER_PERIOD_1, + FPS_POWER_PERIOD_2, + FPS_POWER_PERIOD_3, + FPS_POWER_PERIOD_4, + FPS_POWER_PERIOD_5, + FPS_POWER_PERIOD_6, + FPS_POWER_PERIOD_7, + FPS_POWER_PERIOD_DEF = -1, +}; + +/* FPS Time Period */ +enum max77663_regulator_fps_time_period { + FPS_TIME_PERIOD_20US, + FPS_TIME_PERIOD_40US, + FPS_TIME_PERIOD_80US, + FPS_TIME_PERIOD_160US, + FPS_TIME_PERIOD_320US, + FPS_TIME_PERIOD_640US, + FPS_TIME_PERIOD_1280US, + FPS_TIME_PERIOD_2560US, + FPS_TIME_PERIOD_DEF = -1, +}; + +/* FPS Enable Source */ +enum max77663_regulator_fps_en_src { + FPS_EN_SRC_EN0, + FPS_EN_SRC_EN1, + FPS_EN_SRC_SW, + FPS_EN_SRC_RSVD, +}; + +/* FPS Source */ +enum max77663_regulator_fps_src { + FPS_SRC_0, + FPS_SRC_1, + FPS_SRC_2, + FPS_SRC_NONE, + FPS_SRC_DEF = -1, +}; + +/* + * Flags + */ +/* SD0 is controlled by EN2 */ +#define EN2_CTRL_SD0 0x01 + +/* SD Slew Rate */ +#define SD_SLEW_RATE_SLOWEST 0x02 /* 13.75mV/us */ +#define SD_SLEW_RATE_SLOW 0x04 /* 27.50mV/us */ +#define SD_SLEW_RATE_FAST 0x08 /* 55.00mV/us */ +#define SD_SLEW_RATE_FASTEST 0x10 /* 100.00mV/us */ +#define SD_SLEW_RATE_MASK 0x1E + +/* SD Forced PWM Mode */ +#define SD_FORCED_PWM_MODE 0x20 + +/* SD Failling Slew Rate Active-Discharge Mode */ +#define SD_FSRADE_DISABLE 0x40 + +/* Group Low-Power Mode */ +#define GLPM_ENABLE 0x80 + +/* Tracking for LDO4 */ +#define LDO4_EN_TRACKING 0x100 + +struct max77663_regulator_fps_cfg { + enum max77663_regulator_fps_src src; + enum max77663_regulator_fps_en_src en_src; + enum max77663_regulator_fps_time_period time_period; +}; + +struct max77663_regulator_platform_data { + struct regulator_init_data *reg_init_data; + int id; + enum max77663_regulator_fps_src fps_src; + enum max77663_regulator_fps_power_period fps_pu_period; + enum max77663_regulator_fps_power_period fps_pd_period; + + int num_fps_cfgs; + struct max77663_regulator_fps_cfg *fps_cfgs; + + unsigned int flags; +}; + +#endif /* __LINUX_REGULATOR_MAX77663_REGULATOR_H__ */ diff --git a/include/linux/regulator/max8907c-regulator.h b/include/linux/regulator/max8907c-regulator.h new file mode 100644 index 000000000000..4d071b9644e8 --- /dev/null +++ b/include/linux/regulator/max8907c-regulator.h @@ -0,0 +1,54 @@ +/* linux/regulator/max8907c-regulator.h + * + * Functions to access MAX8907C power management chip. + * + * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_REGULATOR_MAX8907C_H +#define __LINUX_REGULATOR_MAX8907C_H + +/* IDs */ +#define MAX8907C_SD1 0 +#define MAX8907C_SD2 1 +#define MAX8907C_SD3 2 +#define MAX8907C_LDO1 3 +#define MAX8907C_LDO2 4 +#define MAX8907C_LDO3 5 +#define MAX8907C_LDO4 6 +#define MAX8907C_LDO5 7 +#define MAX8907C_LDO6 8 +#define MAX8907C_LDO7 9 +#define MAX8907C_LDO8 10 +#define MAX8907C_LDO9 11 +#define MAX8907C_LDO10 12 +#define MAX8907C_LDO11 13 +#define MAX8907C_LDO12 14 +#define MAX8907C_LDO13 15 +#define MAX8907C_LDO14 16 +#define MAX8907C_LDO15 17 +#define MAX8907C_LDO16 18 +#define MAX8907C_LDO17 19 +#define MAX8907C_LDO18 20 +#define MAX8907C_LDO19 21 +#define MAX8907C_LDO20 22 +#define MAX8907C_OUT5V 23 +#define MAX8907C_OUT33V 24 +#define MAX8907C_BBAT 25 +#define MAX8907C_SDBY 26 +#define MAX8907C_VRTC 27 +#define MAX8907C_WLED 27 + +/* + * struct max8907c_chip_regulator_data - max8907c chip regulator data. + * + * @enable_time_us: microseconds delay required after enabling rail regulator. + */ +struct max8907c_chip_regulator_data { + int enable_time_us; +}; +#endif diff --git a/include/linux/regulator/ricoh583-regulator.h b/include/linux/regulator/ricoh583-regulator.h new file mode 100644 index 000000000000..39fdb9e56e05 --- /dev/null +++ b/include/linux/regulator/ricoh583-regulator.h @@ -0,0 +1,63 @@ +/* + * linux/regulator/ricoh583-regulator.h + * + * Interface for regulator driver for RICOH583 power management chip. + * + * Copyright (C) 2011 NVIDIA Corporation + * + * Copyright (C) 2011 RICOH COMPANY,LTD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_REGULATOR_RICOH583_H +#define __LINUX_REGULATOR_RICOH583_H + +#include <linux/regulator/machine.h> + + +#define ricoh583_rails(_name) "RICOH583_"#_name + +/* RICHOH Regulator IDs */ +enum regulator_id { + RICOH583_ID_DC0, + RICOH583_ID_DC1, + RICOH583_ID_DC2, + RICOH583_ID_DC3, + RICOH583_ID_LDO0, + RICOH583_ID_LDO1, + RICOH583_ID_LDO2, + RICOH583_ID_LDO3, + RICOH583_ID_LDO4, + RICOH583_ID_LDO5, + RICOH583_ID_LDO6, + RICOH583_ID_LDO7, + RICOH583_ID_LDO8, + RICOH583_ID_LDO9, +}; + +struct ricoh583_regulator_platform_data { + struct regulator_init_data regulator; + int init_uV; + unsigned init_enable:1; + unsigned init_apply:1; + int deepsleep_uV; + int deepsleep_slots; + unsigned long ext_pwr_req; + unsigned long flags; +}; + +#endif diff --git a/include/linux/regulator/tps6238x0-regulator.h b/include/linux/regulator/tps6238x0-regulator.h new file mode 100644 index 000000000000..d7c4edc5b101 --- /dev/null +++ b/include/linux/regulator/tps6238x0-regulator.h @@ -0,0 +1,46 @@ +/* + * tps6238x0-regulator.h -- TI TPS623850/TPS623860/TPS623870 + * + * Interface for regulator driver for TI TPS623850/TPS623860/TPS623870 + * Processor core supply + * + * Copyright (C) 2012 NVIDIA Corporation + + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_REGULATOR_TPS6238X0_H +#define __LINUX_REGULATOR_TPS6238X0_H + +/* + * struct tps6238x0_regulator_platform_data - tps62360 regulator platform data. + * + * @init_data: The regulator init data. + * @en_internal_pulldn: internal pull down enable or not. + * @vsel_gpio: Gpio number for vsel. It should be -1 if this is tied with + * fixed logic. + * @vsel_def_state: Default state of vsel. 1 if it is high else 0. + */ +struct tps6238x0_regulator_platform_data { + struct regulator_init_data *init_data; + bool en_internal_pulldn; + int vsel_gpio; + int vsel_def_state; +}; + +#endif /* __LINUX_REGULATOR_TPS6238X0_H */ diff --git a/include/linux/regulator/tps6591x-regulator.h b/include/linux/regulator/tps6591x-regulator.h new file mode 100644 index 000000000000..b749bd7d8881 --- /dev/null +++ b/include/linux/regulator/tps6591x-regulator.h @@ -0,0 +1,78 @@ +/* + * include/linux/regulator/tps6591x-regulator.h + * + * Interface for regulator driver for TI TPS6591x PMIC family + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __REGULATOR_TPS6591X_H +#define __REGULATOR_TPS6591X_H + +#include <linux/regulator/machine.h> + +#define tps6591x_rails(_name) "tps6591x_"#_name + +enum { + TPS6591X_ID_VIO, + TPS6591X_ID_VDD_1, + TPS6591X_ID_VDD_2, + TPS6591X_ID_VDDCTRL, + TPS6591X_ID_LDO_1, + TPS6591X_ID_LDO_2, + TPS6591X_ID_LDO_3, + TPS6591X_ID_LDO_4, + TPS6591X_ID_LDO_5, + TPS6591X_ID_LDO_6, + TPS6591X_ID_LDO_7, + TPS6591X_ID_LDO_8, +}; + +enum tps6591x_ext_control { + EXT_CTRL_NONE = 0x0, + EXT_CTRL_EN1, + EXT_CTRL_EN2, + EXT_CTRL_SLEEP_OFF, +}; + +enum tps6591x_config_flags { + LDO_LOW_POWER_ON_SUSPEND = 0x1, + LDO4_TRACKING_EN = 0x2, +}; + +/* + * struct tps6591x_regulator_platform_data - tps6591x regulator platform data. + * + * @regulator: The regulator init data. + * @init_uV: initial micro volts which need to be set. + * @init_enable: Enable or do not enable the rails during initialization. + * @init_apply: Init parameter applied or not. + * @slew_rate_uV_per_us: Slew rate microvolt per microsec. + */ + +struct tps6591x_regulator_platform_data { + struct regulator_init_data regulator; + int init_uV; + unsigned init_enable:1; + unsigned init_apply:1; + enum tps6591x_ext_control ectrl; + int slew_rate_uV_per_us; + unsigned int flags; +}; + +#endif /* __REGULATOR_TPS6591X_H */ diff --git a/include/linux/rmi.h b/include/linux/rmi.h new file mode 100644 index 000000000000..84e121d936ac --- /dev/null +++ b/include/linux/rmi.h @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2011 Synaptics Incorporated + * Copyright (c) 2011 Unixphere + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _RMI_H +#define _RMI_H +#include <linux/kernel.h> +#include <linux/lockdep.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/cdev.h> +#include <linux/mutex.h> +#include <linux/stat.h> +#include <linux/wait.h> +#include <linux/list.h> +#include <linux/interrupt.h> + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include <linux/earlysuspend.h> +#endif + +#ifdef CONFIG_TOUCHSCREEN_SYN_RMI4_SPI + +#define CONFIG_RMI4_BUS +#define CONFIG_RMI4_SPI +#define CONFIG_RMI4_GENERIC +#define CONFIG_RMI4_F09 +#define CONFIG_RMI4_F11 +#define CONFIG_RMI4_F19 +#define CONFIG_RMI4_F34 +#define CONFIG_RMI4_F54 +#define CONFIG_RMI4_DEV + +#endif + +// #define SYNAPTICS_SENSOR_POLL 1 + +/* Permissions for sysfs attributes. Since the permissions policy will change + * on a global basis in the future, rather than edit all sysfs attrs everywhere + * in the driver (and risk screwing that up in the process), we use this handy + * set of #defines. That way when we change the policy for sysfs permissions, + * we only need to change them here. + */ +#define RMI_RO_ATTR S_IRUGO +#define RMI_RW_ATTR (S_IRUGO | S_IWUGO) +#define RMI_WO_ATTR S_IWUGO + +#define PDT_START_SCAN_LOCATION 0x00e9 + +enum rmi_irq_polarity { + RMI_IRQ_ACTIVE_LOW = 0, + RMI_IRQ_ACTIVE_HIGH = 1 +}; + +/** + * struct rmi_f11_axis_alignmen - target axis alignment + * @swap_axes: set to TRUE if desired to swap x- and y-axis + * @flip_x: set to TRUE if desired to flip direction on x-axis + * @flip_y: set to TRUE if desired to flip direction on y-axis + */ +struct rmi_f11_2d_axis_alignment { + bool swap_axes; + bool flip_x; + bool flip_y; + int clip_X_low; + int clip_Y_low; + int clip_X_high; + int clip_Y_high; + int offset_X; + int offset_Y; + int rel_report_enabled; +}; + +/** + * RMI F11 - function control register parameters + * Each register that has a specific bit-field setup has an accompanied + * register definition so that the setting can be chosen as a one-word + * register setting or per-bit setting. + */ +union rmi_f11_2d_ctrl0 { + struct { + u8 reporting_mode:3; + u8 abs_pos_filt:1; + u8 rel_pos_filt:1; + u8 rel_ballistics:1; + u8 dribble:1; + u8 report_beyond_clip:1; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl1 { + struct { + u8 palm_detect_thres:4; + u8 motion_sensitivity:2; + u8 man_track_en:1; + u8 man_tracked_finger:1; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl2__3 { + struct { + u8 delta_x_threshold:8; + u8 delta_y_threshold:8; + }; + u8 regs[2]; +}; + +union rmi_f11_2d_ctrl4 { + struct { + u8 velocity:8; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl5 { + struct { + u8 acceleration:8; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl6__7 { + struct { + u16 sensor_max_x_pos:12; + }; + u8 regs[2]; +}; + +union rmi_f11_2d_ctrl8__9 { + struct { + u16 sensor_max_y_pos:12; + }; + u8 regs[2]; +}; + +union rmi_f11_2d_ctrl10 { + struct { + u8 single_tap_int_enable:1; + u8 tap_n_hold_int_enable:1; + u8 double_tap_int_enable:1; + u8 early_tap_int_enable:1; + u8 flick_int_enable:1; + u8 press_int_enable:1; + u8 pinch_int_enable:1; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl11 { + struct { + u8 palm_detect_int_enable:1; + u8 rotate_int_enable:1; + u8 touch_shape_int_enable:1; + u8 scroll_zone_int_enable:1; + u8 multi_finger_scroll_int_enable:1; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl12 { + struct { + u8 sensor_map:7; + u8 xy_sel:1; + }; + u8 reg; +}; + +union rmi_f11_2d_ctrl14 { + struct { + u8 sens_adjustment:5; + u8 hyst_adjustment:3; + }; + u8 reg; +}; + +/* The configuation is controlled as per register which means that if a register + * is allocated for ctrl configuration one must make sure that all the bits are + * set accordingly for that particular register. + */ +struct rmi_f11_2d_ctrl { + union rmi_f11_2d_ctrl0 *ctrl0; + union rmi_f11_2d_ctrl1 *ctrl1; + union rmi_f11_2d_ctrl2__3 *ctrl2__3; + union rmi_f11_2d_ctrl4 *ctrl4; + union rmi_f11_2d_ctrl5 *ctrl5; + union rmi_f11_2d_ctrl6__7 *ctrl6__7; + union rmi_f11_2d_ctrl8__9 *ctrl8__9; + union rmi_f11_2d_ctrl10 *ctrl10; + union rmi_f11_2d_ctrl11 *ctrl11; + union rmi_f11_2d_ctrl12 *ctrl12; + u8 ctrl12_size; + union rmi_f11_2d_ctrl14 *ctrl14; + u8 *ctrl15; + u8 *ctrl16; + u8 *ctrl17; + u8 *ctrl18; + u8 *ctrl19; +}; + +struct rmi_f19_button_map { + unsigned char nbuttons; + unsigned char *map; +}; + +struct rmi_device_platform_data_spi { + int block_delay_us; + int split_read_block_delay_us; + int read_delay_us; + int write_delay_us; + int split_read_byte_delay_us; + int pre_delay_us; + int post_delay_us; + + void *cs_assert_data; + int (*cs_assert) (const void *cs_assert_data, const bool assert); +}; + +struct rmi_device_platform_data { + char *driver_name; + + int irq; + enum rmi_irq_polarity irq_polarity; + int (*gpio_config)(void *gpio_data, bool configure); + + struct rmi_device_platform_data_spi spi_data; + + /* function handler pdata */ + struct rmi_f11_2d_ctrl *f11_ctrl; + struct rmi_f11_2d_axis_alignment axis_align; + struct rmi_f19_button_map *button_map; + +#ifdef CONFIG_PM + void *pm_data; + int (*pre_suspend) (const void *pm_data); + int (*post_resume) (const void *pm_data); +#endif +}; + +/** + * struct rmi_function_descriptor - RMI function base addresses + * @query_base_addr: The RMI Query base address + * @command_base_addr: The RMI Command base address + * @control_base_addr: The RMI Control base address + * @data_base_addr: The RMI Data base address + * @interrupt_source_count: The number of irqs this RMI function needs + * @function_number: The RMI function number + * + * This struct is used when iterating the Page Description Table. The addresses + * are 16-bit values to include the current page address. + * + */ +struct rmi_function_descriptor { + u16 query_base_addr; + u16 command_base_addr; + u16 control_base_addr; + u16 data_base_addr; + u8 interrupt_source_count; + u8 function_number; + u8 function_version; +}; + +struct rmi_function_container; +struct rmi_device; + +/** + * struct rmi_function_handler - an RMI function handler + * @func: The RMI function number + * @init: Callback for RMI function init + * @attention: Callback for RMI function attention + * @suspend: Callback for function suspend, returns 0 for success. + * @resume: Callback for RMI function resume, returns 0 for success. + * @remove: Callback for RMI function removal + * + * This struct describes the interface of an RMI function. These are + * registered to the bus using the rmi_register_function_driver() call. + * + */ +struct rmi_function_handler { + int func; + int (*init)(struct rmi_function_container *fc); + int (*attention)(struct rmi_function_container *fc, u8 *irq_bits); +#ifdef CONFIG_PM + int (*suspend)(struct rmi_function_container *fc); + int (*resume)(struct rmi_function_container *fc); +#endif + void (*remove)(struct rmi_function_container *fc); +}; + +/** + * struct rmi_function_device - represent an RMI function device + * @dev: The device created + * + * The RMI function device implements the "psuedo" device that represents + * an RMI4 function like function 0x11, function 0x34, etc. and is really + * a placeholder to be able to create sysfs attributes for each function + * in order to facilitate communication between user code and RMI4 functions. + * + */ +struct rmi_function_device { + struct device dev; +}; + +/** + * struct rmi_function_container - an element in a function handler list + * @list: The list + * @fd: The function descriptor of the RMI function + * @rmi_dev: Pointer to the RMI device associated with this function container + * @fh: The callbacks connected to this function + * @num_of_irqs: The number of irqs needed by this function + * @irq_pos: The position in the irq bitfield this function holds + * @data: Private data pointer + * + */ +struct rmi_function_container { + struct list_head list; + + struct rmi_function_descriptor fd; + struct rmi_device *rmi_dev; + struct rmi_function_handler *fh; + struct device dev; + + int num_of_irqs; + int irq_pos; + u8 *irq_mask; + + void *data; +}; +#define to_rmi_function_container(d) \ + container_of(d, struct rmi_function_container, dev); +#define to_rmi_function_device(d) \ + container_of(d, struct rmi_function_device, dev); + + +#ifdef CONFIG_RMI4_DEV + +#define RMI_CHAR_DEV_TMPBUF_SZ 128 +#define RMI_REG_ADDR_PAGE_SELECT 0xFF + +struct rmi_char_dev { + /* mutex for file operation*/ + struct mutex mutex_file_op; + /* main char dev structure */ + struct cdev main_dev; + + /* register address for RMI protocol */ + /* filp->f_pos */ + + /* pointer to the corresponding phys device info for this sensor */ + /* The phys device has the pointers to read, write, etc. */ + struct rmi_phys_device *phys; + /* reference count */ + int ref_count; +}; + +int rmi_char_dev_register(struct rmi_phys_device *phys); +void rmi_char_dev_unregister(struct rmi_phys_device *phys); + +#endif /*CONFIG_RMI4_DEV*/ + + + +/** + * struct rmi_driver - represents an RMI driver + * @driver: Device driver model driver + * @probe: Callback for device probe + * @remove: Callback for device removal + * @shutdown: Callback for device shutdown + * @irq_handler: Callback for handling irqs + * @fh_add: Callback for function handler add + * @fh_remove: Callback for function handler remove + * @get_func_irq_mask: Callback for calculating interrupt mask + * @store_irq_mask: Callback for storing and replacing interrupt mask + * @restore_irq_mask: Callback for restoring previously stored interrupt mask + * @data: Private data pointer + * + * The RMI driver implements a driver on the RMI bus. + * + */ +struct rmi_driver { + struct device_driver driver; + + int (*probe)(struct rmi_device *rmi_dev); + int (*remove)(struct rmi_device *rmi_dev); + void (*shutdown)(struct rmi_device *rmi_dev); + int (*irq_handler)(struct rmi_device *rmi_dev, int irq); + void (*fh_add)(struct rmi_device *rmi_dev, + struct rmi_function_handler *fh); + void (*fh_remove)(struct rmi_device *rmi_dev, + struct rmi_function_handler *fh); + u8* (*get_func_irq_mask)(struct rmi_device *rmi_dev, + struct rmi_function_container *fc); + int (*store_irq_mask)(struct rmi_device *rmi_dev, u8* new_interupts); + int (*restore_irq_mask)(struct rmi_device *rmi_dev); + void *data; +}; +#define to_rmi_driver(d) \ + container_of(d, struct rmi_driver, driver); + +/** struct rmi_phys_info - diagnostic information about the RMI physical + * device, used in the phys sysfs file. + * @proto String indicating the protocol being used. + * @tx_count Number of transmit operations. + * @tx_bytes Number of bytes transmitted. + * @tx_errs Number of errors encountered during transmit operations. + * @rx_count Number of receive operations. + * @rx_bytes Number of bytes received. + * @rx_errs Number of errors encountered during receive operations. + * @att_count Number of times ATTN assertions have been handled. + */ +struct rmi_phys_info { + char *proto; + long tx_count; + long tx_bytes; + long tx_errs; + long rx_count; + long rx_bytes; + long rx_errs; + long attn_count; +}; + +/** + * struct rmi_phys_device - represent an RMI physical device + * @dev: Pointer to the communication device, e.g. i2c or spi + * @rmi_dev: Pointer to the RMI device + * @write: Callback for write + * @write_block: Callback for writing a block of data + * @read: Callback for read + * @read_block: Callback for reading a block of data + * @data: Private data pointer + * + * The RMI physical device implements the glue between different communication + * buses such as I2C and SPI. + * + */ +struct rmi_phys_device { + struct device *dev; + struct rmi_device *rmi_dev; + + int (*write)(struct rmi_phys_device *phys, u16 addr, u8 data); + int (*write_block)(struct rmi_phys_device *phys, u16 addr, u8 *buf, + int len); + int (*read)(struct rmi_phys_device *phys, u16 addr, u8 *buf); + int (*read_block)(struct rmi_phys_device *phys, u16 addr, u8 *buf, + int len); + + int (*enable_device) (struct rmi_phys_device *phys); + void (*disable_device) (struct rmi_phys_device *phys); + + void *data; + + struct rmi_phys_info info; + +#ifdef CONFIG_RMI4_DEV + /* pointer to attention char device and char device */ + struct rmi_char_dev *char_dev; + struct class *rmi_char_device_class; +#endif /*CONFIG_RMI4_DEV*/ +}; + +/** + * struct rmi_device - represents an RMI device + * @dev: The device created for the RMI bus + * @driver: Pointer to associated driver + * @phys: Pointer to the physical interface + * @early_suspend_handler: Pointers to early_suspend and late_resume, if + * configured. + * + * This structs represent an RMI device. + * + */ +struct rmi_device { + struct device dev; + + struct rmi_driver *driver; + struct rmi_phys_device *phys; + +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend_handler; +#endif +}; +#define to_rmi_device(d) container_of(d, struct rmi_device, dev); +#define to_rmi_platform_data(d) ((d)->phys->dev->platform_data); + +static inline void rmi_set_driverdata(struct rmi_device *d, void *data) +{ + dev_set_drvdata(&d->dev, data); +} + +static inline void *rmi_get_driverdata(struct rmi_device *d) +{ + return dev_get_drvdata(&d->dev); +} + +/** + * rmi_read - RMI read byte + * @d: Pointer to an RMI device + * @addr: The address to read from + * @buf: The read buffer + * + * Reads a byte of data using the underlaying physical protocol in to buf. It + * returns zero or a negative error code. + */ +static inline int rmi_read(struct rmi_device *d, u16 addr, u8 *buf) +{ + return d->phys->read(d->phys, addr, buf); +} + +/** + * rmi_read_block - RMI read block + * @d: Pointer to an RMI device + * @addr: The start address to read from + * @buf: The read buffer + * @len: Length of the read buffer + * + * Reads a block of byte data using the underlaying physical protocol in to buf. + * It returns the amount of bytes read or a negative error code. + */ +static inline int rmi_read_block(struct rmi_device *d, u16 addr, u8 *buf, + int len) +{ + return d->phys->read_block(d->phys, addr, buf, len); +} + +/** + * rmi_write - RMI write byte + * @d: Pointer to an RMI device + * @addr: The address to write to + * @data: The data to write + * + * Writes a byte from buf using the underlaying physical protocol. It + * returns zero or a negative error code. + */ +static inline int rmi_write(struct rmi_device *d, u16 addr, u8 data) +{ + return d->phys->write(d->phys, addr, data); +} + +/** + * rmi_write_block - RMI write block + * @d: Pointer to an RMI device + * @addr: The start address to write to + * @buf: The write buffer + * @len: Length of the write buffer + * + * Writes a block of byte data from buf using the underlaying physical protocol. + * It returns the amount of bytes written or a negative error code. + */ +static inline int rmi_write_block(struct rmi_device *d, u16 addr, u8 *buf, + int len) +{ + return d->phys->write_block(d->phys, addr, buf, len); +} + +/** + * rmi_register_driver - register rmi driver + * @driver: the driver to register + * + * This function registers an RMI driver to the RMI bus. + */ +int rmi_register_driver(struct rmi_driver *driver); + +/** + * rmi_unregister_driver - unregister rmi driver + * @driver: the driver to unregister + * + * This function unregisters an RMI driver to the RMI bus. + */ +void rmi_unregister_driver(struct rmi_driver *driver); + +/** + * rmi_register_phys_device - register a physical device connection + * @phys: the physical driver to register + * + * This function registers a physical driver to the RMI bus. These drivers + * provide a communication layer for the drivers connected to the bus, e.g. + * I2C, SPI and so on. + */ +int rmi_register_phys_device(struct rmi_phys_device *phys); + +/** + * rmi_unregister_phys_device - unregister a physical device connection + * @phys: the physical driver to unregister + * + * This function unregisters a physical driver from the RMI bus. + */ +void rmi_unregister_phys_device(struct rmi_phys_device *phys); + +/** + * rmi_register_function_driver - register an RMI function driver + * @fh: the function handler to register + * + * This function registers support for a new RMI function to the bus. All + * drivers on the bus will be notified of the presence of the new function + * driver. + */ +int rmi_register_function_driver(struct rmi_function_handler *fh); + +/** + * rmi_unregister_function_driver - unregister an RMI function driver + * @fh: the function handler to unregister + * + * This function unregisters a RMI function from the RMI bus. All drivers on + * the bus will be notified of the removal of a function driver. + */ +void rmi_unregister_function_driver(struct rmi_function_handler *fh); + +/** + * rmi_get_function_handler - get a pointer to specified RMI function + * @id: the RMI function id + * + * This function gets the specified RMI function handler from the list of + * supported functions. + */ +struct rmi_function_handler *rmi_get_function_handler(int id); + +/* Utility routine to handle writes to read-only attributes. Hopefully + * this will never happen, but if the user does something stupid, we + * don't want to accept it quietly. + */ +ssize_t rmi_store_error(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +/* Utility routine to handle reads to write-only attributes. Hopefully + * this will never happen, but if the user does something stupid, we + * don't want to accept it quietly. + */ +ssize_t rmi_show_error(struct device *dev, + struct device_attribute *attr, + char *buf); + +/* utility function for bit access of u8*'s */ +void u8_set_bit(u8 *target, int pos); +void u8_clear_bit(u8 *target, int pos); +bool u8_is_set(u8 *target, int pos); +bool u8_is_any_set(u8 *target, int size); +void u8_or(u8 *dest, u8* target1, u8* target2, int size); +void u8_and(u8 *dest, u8* target1, u8* target2, int size); +#endif diff --git a/include/linux/smb349-charger.h b/include/linux/smb349-charger.h new file mode 100644 index 000000000000..089f3976dbbe --- /dev/null +++ b/include/linux/smb349-charger.h @@ -0,0 +1,80 @@ +/* + * include/linux/smb349-charger.h + * + * Battery charger driver interface for Summit SMB349 + * + * Copyright (C) 2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_SMB349_CHARGER_H +#define __LINUX_SMB349_CHARGER_H + +#include <linux/regulator/machine.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/usb/otg.h> + +struct smb349_charger_platform_data { + int regulator_id; + int max_charge_volt_mV; + int max_charge_current_mA; + int charging_term_current_mA; + int num_consumer_supplies; + struct regulator_consumer_supply *consumer_supplies; +}; + +enum charging_states { + idle, + progress, + completed, + stopped, +}; + +enum charger_type { + NONE, + AC, + USB, +}; + +typedef void (*charging_callback_t)(enum charging_states state, +enum charger_type chrg_type, void *args); + +struct smb349_charger { + struct i2c_client *client; + struct device *dev; + void *charger_cb_data; + enum charging_states state; + enum charger_type chrg_type; + charging_callback_t charger_cb; + + struct regulator_dev *rdev; + struct regulator_desc reg_desc; + struct regulator_init_data reg_init_data; +}; + +int smb349_battery_online(void); +typedef void (*callback_t)(enum usb_otg_state to, + enum usb_otg_state from, void *args); +/* + * Register callback function for the client. + * Used by fuel-gauge driver to get battery charging properties. + */ +extern int register_callback(charging_callback_t cb, void *args); +extern int register_otg_callback(callback_t cb, void *args); +extern int update_charger_status(void); + +#endif /*__LINUX_SMB349_CHARGER_H */ diff --git a/include/linux/spi-tegra.h b/include/linux/spi-tegra.h new file mode 100644 index 000000000000..89f6bb3adb96 --- /dev/null +++ b/include/linux/spi-tegra.h @@ -0,0 +1,52 @@ +/* + * include/linux/spi-tegra.c + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_SPI_TEGRA_H +#define _LINUX_SPI_TEGRA_H + +#include <linux/clk.h> + +struct spi_clk_parent { + const char *name; + struct clk *parent_clk; + unsigned long fixed_clk_rate; +}; + +struct tegra_spi_platform_data { + bool is_dma_based; + int max_dma_buffer; + bool is_clkon_always; + unsigned int max_rate; + struct spi_clk_parent *parent_clk_list; + int parent_clk_count; +}; + +/* Controller data from device to pass some info like + * hw based chip select can be used or not and if yes + * then CS hold and setup time. */ +struct tegra_spi_device_controller_data { + bool is_hw_based_cs; + int cs_setup_clk_count; + int cs_hold_clk_count; + int rx_clk_tap_delay; + int tx_clk_tap_delay; +}; + +#endif /* _LINUX_SPI_TEGRA_H */ diff --git a/include/linux/spi/rm31080a_ts.h b/include/linux/spi/rm31080a_ts.h new file mode 100644 index 000000000000..13323a6f2ec9 --- /dev/null +++ b/include/linux/spi/rm31080a_ts.h @@ -0,0 +1,44 @@ +#ifndef _RM31080A_TS_H_ +#define _RM31080A_TS_H_ + +#define ENABLE_RAW_DATA_QUEUE + +#define RM_IOCTL_REPORT_POINT 0x1001 +#define RM_IOCTL_SET_HAL_PID 0x1002 +#define RM_IOCTL_INIT_START 0x1003 +#define RM_IOCTL_INIT_END 0x1004 +#define RM_IOCTL_FINISH_CALC 0x1005 +#define RM_IOCTL_SCRIBER_CTRL 0x1006 +#define RM_IOCTL_READ_RAW_DATA 0x1007 +#define RM_IOCTL_AUTOSCAN_CTRL 0x1008 +#define RM_IOCTL_NOISE_CHECK 0x1009 +#define RM_IOCTL_GET_PARAMETER 0x100A +#define RM_IOCTL_SET_PARAMETER 0x100B + +#define RM_INPUT_RESOLUTION_X 4096 +#define RM_INPUT_RESOLUTION_Y 4096 + +#define RM_TS_SIGNAL 44 +#define RM_TS_MAX_POINTS 16 + +#define RM_SIGNAL_INTR 0x00000001 +#define RM_SIGNAL_SUSPEND 0x00000002 +#define RM_SIGNAL_RESUME 0x00000003 + +typedef struct { + unsigned char ucTouchCount; + unsigned char ucID[RM_TS_MAX_POINTS]; + unsigned short usX[RM_TS_MAX_POINTS]; + unsigned short usY[RM_TS_MAX_POINTS]; + unsigned short usZ[RM_TS_MAX_POINTS]; +} rm_touch_event; + + +struct rm_spi_ts_platform_data{ + int gpio_reset; + int x_size; + int y_size; + unsigned char* config; +}; + +#endif //_RM31080A_TS_H_ diff --git a/include/linux/spi/spi-tegra.h b/include/linux/spi/spi-tegra.h new file mode 100644 index 000000000000..c0413827ed6a --- /dev/null +++ b/include/linux/spi/spi-tegra.h @@ -0,0 +1,42 @@ +/* + * spi-tegra.h: SPI interface for Nvidia Tegra20 SLINK controller. + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_SPI_TEGRA_H +#define _LINUX_SPI_TEGRA_H + +struct tegra_spi_platform_data { + int dma_req_sel; + unsigned int spi_max_frequency; +}; + +/* + * Controller data from device to pass some info like + * hw based chip select can be used or not and if yes + * then CS hold and setup time. + */ +struct tegra_spi_device_controller_data { + bool is_hw_based_cs; + int cs_setup_clk_count; + int cs_hold_clk_count; + int rx_clk_tap_delay; + int tx_clk_tap_delay; +}; + +#endif /* _LINUX_SPI_TEGRA_H */ diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index 84ca436b76c2..9faf0f49199f 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -130,6 +130,7 @@ struct rpc_task_setup { #define RPC_TASK_SOFTCONN 0x0400 /* Fail if can't connect */ #define RPC_TASK_SENT 0x0800 /* message was sent */ #define RPC_TASK_TIMEOUT 0x1000 /* fail with ETIMEDOUT on timeout */ +#define RPC_TASK_NOCONNECT 0x2000 /* return ENOTCONN if not connected */ #define RPC_IS_ASYNC(t) ((t)->tk_flags & RPC_TASK_ASYNC) #define RPC_IS_SWAPPER(t) ((t)->tk_flags & RPC_TASK_SWAPPER) diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 4147d700a293..84662ecc7b51 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -802,9 +802,14 @@ asmlinkage long sys_vfork(void); asmlinkage long sys_clone(unsigned long, unsigned long, int __user *, int, int __user *); #else +#ifdef CONFIG_CLONE_BACKWARDS3 +asmlinkage long sys_clone(unsigned long, unsigned long, int, int __user *, + int __user *, int); +#else asmlinkage long sys_clone(unsigned long, unsigned long, int __user *, int __user *, int); #endif +#endif asmlinkage long sys_execve(const char __user *filename, const char __user *const __user *argv, diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h deleted file mode 100644 index 55c29a8d5015..000000000000 --- a/include/linux/tegra-powergate.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2010 Google, Inc - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_POWERGATE_H_ -#define _MACH_TEGRA_POWERGATE_H_ - -struct clk; - -#define TEGRA_POWERGATE_CPU 0 -#define TEGRA_POWERGATE_3D 1 -#define TEGRA_POWERGATE_VENC 2 -#define TEGRA_POWERGATE_PCIE 3 -#define TEGRA_POWERGATE_VDEC 4 -#define TEGRA_POWERGATE_L2 5 -#define TEGRA_POWERGATE_MPE 6 -#define TEGRA_POWERGATE_HEG 7 -#define TEGRA_POWERGATE_SATA 8 -#define TEGRA_POWERGATE_CPU1 9 -#define TEGRA_POWERGATE_CPU2 10 -#define TEGRA_POWERGATE_CPU3 11 -#define TEGRA_POWERGATE_CELP 12 -#define TEGRA_POWERGATE_3D1 13 - -#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU -#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D - -int tegra_powergate_is_powered(int id); -int tegra_powergate_power_on(int id); -int tegra_powergate_power_off(int id); -int tegra_powergate_remove_clamping(int id); - -/* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk); - -#endif /* _MACH_TEGRA_POWERGATE_H_ */ diff --git a/include/linux/tegra_audio.h b/include/linux/tegra_audio.h new file mode 100644 index 000000000000..ddc9c93498a0 --- /dev/null +++ b/include/linux/tegra_audio.h @@ -0,0 +1,87 @@ +/* include/linux/tegra_audio.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Iliyan Malchev <malchev@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _TEGRA_AUDIO_H +#define _TEGRA_AUDIO_H + +#include <linux/ioctl.h> + +#define TEGRA_AUDIO_MAGIC 't' + +#define TEGRA_AUDIO_IN_START _IO(TEGRA_AUDIO_MAGIC, 0) +#define TEGRA_AUDIO_IN_STOP _IO(TEGRA_AUDIO_MAGIC, 1) + +struct tegra_audio_in_config { + int rate; + int stereo; +}; + +struct dam_srate { + unsigned int in_sample_rate; + unsigned int out_sample_rate; + unsigned int audio_bits; + unsigned int client_bits; + unsigned int audio_channels; + unsigned int client_channels; + unsigned int apbif_chan; +}; + +#define TEGRA_AUDIO_IN_SET_CONFIG _IOW(TEGRA_AUDIO_MAGIC, 2, \ + const struct tegra_audio_in_config *) +#define TEGRA_AUDIO_IN_GET_CONFIG _IOR(TEGRA_AUDIO_MAGIC, 3, \ + struct tegra_audio_in_config *) + +#define TEGRA_AUDIO_IN_SET_NUM_BUFS _IOW(TEGRA_AUDIO_MAGIC, 4, \ + const unsigned int *) +#define TEGRA_AUDIO_IN_GET_NUM_BUFS _IOW(TEGRA_AUDIO_MAGIC, 5, \ + unsigned int *) +#define TEGRA_AUDIO_OUT_SET_NUM_BUFS _IOW(TEGRA_AUDIO_MAGIC, 6, \ + const unsigned int *) +#define TEGRA_AUDIO_OUT_GET_NUM_BUFS _IOW(TEGRA_AUDIO_MAGIC, 7, \ + unsigned int *) + +#define TEGRA_AUDIO_OUT_FLUSH _IO(TEGRA_AUDIO_MAGIC, 10) + +#define TEGRA_AUDIO_BIT_FORMAT_DEFAULT 0 +#define TEGRA_AUDIO_BIT_FORMAT_DSP 1 +#define TEGRA_AUDIO_SET_BIT_FORMAT _IOW(TEGRA_AUDIO_MAGIC, 11, \ + const unsigned int *) +#define TEGRA_AUDIO_GET_BIT_FORMAT _IOR(TEGRA_AUDIO_MAGIC, 12, \ + unsigned int *) + +#define DAM_SRC_START _IOW(TEGRA_AUDIO_MAGIC, 13, struct dam_srate *) +#define DAM_SRC_STOP _IO(TEGRA_AUDIO_MAGIC, 14) +#define DAM_MIXING_START _IOW(TEGRA_AUDIO_MAGIC, 15, struct dam_srate *) +#define DAM_MIXING_STOP _IO(TEGRA_AUDIO_MAGIC, 16) +#define DAM_SET_MIXING_FLAG _IO(TEGRA_AUDIO_MAGIC, 17) + +#define I2S_START _IOW(TEGRA_AUDIO_MAGIC, 15, struct i2s_pcm_format *) +#define I2S_STOP _IOW(TEGRA_AUDIO_MAGIC, 16, struct i2s_pcm_format *) +#define I2S_LOOPBACK _IOW(TEGRA_AUDIO_MAGIC, 17, unsigned int *) +#define I2S_MODE_I2S _IOW(TEGRA_AUDIO_MAGIC, 18, unsigned int *) + +#ifdef CONFIG_SND_SOC_TEGRA +extern bool tegra_is_voice_call_active(void); +#else +static inline bool tegra_is_voice_call_active() +{ + return false; +} +#endif + +#endif/*_CPCAP_AUDIO_H*/ diff --git a/include/linux/tegra_avp.h b/include/linux/tegra_avp.h new file mode 100644 index 000000000000..9dc92f821368 --- /dev/null +++ b/include/linux/tegra_avp.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2010 Google, Inc. + * Author: Dima Zavin <dima@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_AVP_H +#define __LINUX_TEGRA_AVP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define TEGRA_AVP_LIB_MAX_NAME 32 +#define TEGRA_AVP_LIB_MAX_ARGS 220 /* DO NOT CHANGE THIS! */ + +struct tegra_avp_lib { + char name[TEGRA_AVP_LIB_MAX_NAME]; + void __user *args; + size_t args_len; + int greedy; + unsigned long handle; +}; + +struct tegra_avp_platform_data { + unsigned long emc_clk_rate; +}; +#define TEGRA_AVP_IOCTL_MAGIC 'r' + +#define TEGRA_AVP_IOCTL_LOAD_LIB _IOWR(TEGRA_AVP_IOCTL_MAGIC, 0x40, struct tegra_avp_lib) +#define TEGRA_AVP_IOCTL_UNLOAD_LIB _IOW(TEGRA_AVP_IOCTL_MAGIC, 0x41, unsigned long) + +#define TEGRA_AVP_IOCTL_MIN_NR _IOC_NR(TEGRA_AVP_IOCTL_LOAD_LIB) +#define TEGRA_AVP_IOCTL_MAX_NR _IOC_NR(TEGRA_AVP_IOCTL_UNLOAD_LIB) + +#endif diff --git a/include/linux/tegra_caif.h b/include/linux/tegra_caif.h new file mode 100644 index 000000000000..fed67499defc --- /dev/null +++ b/include/linux/tegra_caif.h @@ -0,0 +1,34 @@ +/* include/linux/tegra_caif.h + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _TEGRA_CAIF_H_ +#define _TEGRA_CAIF_H_ + +/* The GPIO details needed by the rainbow caif */ +struct tegra_caif_platform_data { + int reset; + int power; + int awr; + int cwr; + int spi_int; + int spi_ss; +}; + +#endif /* _TEGRA_CAIF_H_ */ + diff --git a/include/linux/tegra_mediaserver.h b/include/linux/tegra_mediaserver.h new file mode 100644 index 000000000000..f28473baf63e --- /dev/null +++ b/include/linux/tegra_mediaserver.h @@ -0,0 +1,112 @@ +/* include/linux/tegra_mediaserver.h + * + * Media Server driver for NVIDIA Tegra SoCs + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + + +#ifndef _TEGRA_MEDIASERVER_H +#define _TEGRA_MEDIASERVER_H + +#include <linux/ioctl.h> + +#define TEGRA_MEDIASERVER_MAGIC 'm' +#define TEGRA_MEDIASERVER_IOCTL_ALLOC \ + _IOWR(TEGRA_MEDIASERVER_MAGIC, 0x40, \ + union tegra_mediaserver_alloc_info) + +enum tegra_mediaserver_resource_type { + TEGRA_MEDIASERVER_RESOURCE_BLOCK = 0, + TEGRA_MEDIASERVER_RESOURCE_IRAM, +}; + +enum tegra_mediaserver_block_type { + TEGRA_MEDIASERVER_BLOCK_AUDDEC = 0, + TEGRA_MEDIASERVER_BLOCK_VIDDEC, +}; + +enum tegra_mediaserver_iram_type { + TEGRA_MEDIASERVER_IRAM_SCRATCH = 0, + TEGRA_MEDIASERVER_IRAM_SHARED, +}; + + +struct tegra_mediaserver_block_info { + int nvmm_block_handle; + int avp_block_handle; + int avp_block_library_handle; + int service_handle; + int service_library_handle; +}; + +struct tegra_mediaserver_iram_info { + unsigned long rm_handle; + int physical_address; +}; + +union tegra_mediaserver_alloc_info { + struct { + int tegra_mediaserver_resource_type; + + union { + struct tegra_mediaserver_block_info block; + + struct { + int tegra_mediaserver_iram_type; + int alignment; + size_t size; + } iram; + } u; + } in; + + struct { + union { + struct { + int count; + } block; + + struct tegra_mediaserver_iram_info iram; + } u; + } out; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_FREE \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x41, union tegra_mediaserver_free_info) + +union tegra_mediaserver_free_info { + struct { + int tegra_mediaserver_resource_type; + + union { + int nvmm_block_handle; + int iram_rm_handle; + } u; + } in; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_UPDATE_BLOCK_INFO \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x45, \ + union tegra_mediaserver_update_block_info) + +union tegra_mediaserver_update_block_info { + struct tegra_mediaserver_block_info in; +}; +#endif + diff --git a/include/linux/tegra_nvavp.h b/include/linux/tegra_nvavp.h new file mode 100644 index 000000000000..250eee379de9 --- /dev/null +++ b/include/linux/tegra_nvavp.h @@ -0,0 +1,100 @@ +/* + * include/linux/tegra_nvavp.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __LINUX_TEGRA_NVAVP_H +#define __LINUX_TEGRA_NVAVP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define NVAVP_MAX_RELOCATION_COUNT 64 + +/* avp submit flags */ +#define NVAVP_FLAG_NONE 0x00000000 +#define NVAVP_UCODE_EXT 0x00000001 /*use external ucode provided */ + +enum { + NVAVP_MODULE_ID_AVP = 2, + NVAVP_MODULE_ID_VCP = 3, + NVAVP_MODULE_ID_BSEA = 27, + NVAVP_MODULE_ID_VDE = 28, + NVAVP_MODULE_ID_MPE = 29, + NVAVP_MODULE_ID_EMC = 75, +}; + +struct nvavp_cmdbuf { + __u32 mem; + __u32 offset; + __u32 words; +}; + +struct nvavp_reloc { + __u32 cmdbuf_mem; + __u32 cmdbuf_offset; + __u32 target; + __u32 target_offset; +}; + +struct nvavp_syncpt { + __u32 id; + __u32 value; +}; + +struct nvavp_pushbuffer_submit_hdr { + struct nvavp_cmdbuf cmdbuf; + struct nvavp_reloc *relocs; + __u32 num_relocs; + struct nvavp_syncpt *syncpt; + __u32 flags; +}; + +struct nvavp_set_nvmap_fd_args { + __u32 fd; +}; + +struct nvavp_clock_args { + __u32 id; + __u32 rate; +}; + +enum nvavp_clock_stay_on_state { + NVAVP_CLOCK_STAY_ON_DISABLED = 0, + NVAVP_CLOCK_STAY_ON_ENABLED +}; + +struct nvavp_clock_stay_on_state_args { + enum nvavp_clock_stay_on_state state; +}; + +#define NVAVP_IOCTL_MAGIC 'n' + +#define NVAVP_IOCTL_SET_NVMAP_FD _IOW(NVAVP_IOCTL_MAGIC, 0x60, \ + struct nvavp_set_nvmap_fd_args) +#define NVAVP_IOCTL_GET_SYNCPOINT_ID _IOR(NVAVP_IOCTL_MAGIC, 0x61, \ + __u32) +#define NVAVP_IOCTL_PUSH_BUFFER_SUBMIT _IOWR(NVAVP_IOCTL_MAGIC, 0x63, \ + struct nvavp_pushbuffer_submit_hdr) +#define NVAVP_IOCTL_SET_CLOCK _IOWR(NVAVP_IOCTL_MAGIC, 0x64, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_GET_CLOCK _IOR(NVAVP_IOCTL_MAGIC, 0x65, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_WAKE_AVP _IOR(NVAVP_IOCTL_MAGIC, 0x66, \ + __u32) +#define NVAVP_IOCTL_FORCE_CLOCK_STAY_ON _IOW(NVAVP_IOCTL_MAGIC, 0x67, \ + struct nvavp_clock_stay_on_state_args) +#define NVAVP_IOCTL_ENABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x68, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x69, \ + struct nvavp_clock_args) + +#define NVAVP_IOCTL_MIN_NR _IOC_NR(NVAVP_IOCTL_SET_NVMAP_FD) +#define NVAVP_IOCTL_MAX_NR _IOC_NR(NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS) + +#endif /* __LINUX_TEGRA_NVAVP_H */ diff --git a/include/linux/tegra_pwm_bl.h b/include/linux/tegra_pwm_bl.h new file mode 100644 index 000000000000..3ed5e8a3c0a9 --- /dev/null +++ b/include/linux/tegra_pwm_bl.h @@ -0,0 +1,30 @@ +/* Tegra PWM backlight data * + * + * Copyright (C) 2011 NVIDIA Corporation + * Author: Renuka Apte <rapte@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef TEGRA_PWM_BL_H +#define TEGRA_PWM_BL_H + +#include <linux/backlight.h> + +struct platform_tegra_pwm_backlight_data { + int which_dc; + int which_pwm; + int gpio_conf_to_sfio; + unsigned int dft_brightness; + unsigned int max_brightness; + unsigned int period; + unsigned int clk_div; + unsigned int clk_select; + int (*notify)(struct device *dev, int brightness); + int (*check_fb)(struct device *dev, struct fb_info *info); +}; + +#endif /* TERGA_PWM_BL_H */ diff --git a/include/linux/tegra_rpc.h b/include/linux/tegra_rpc.h new file mode 100644 index 000000000000..16e6367cf569 --- /dev/null +++ b/include/linux/tegra_rpc.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Dima Zavin <dima@android.com> + * + * Based on original code from NVIDIA, and a partial rewrite by: + * Gary King <gking@nvidia.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_RPC_H +#define __LINUX_TEGRA_RPC_H + +#define TEGRA_RPC_MAX_MSG_LEN 256 + +/* Note: the actual size of the name in the protocol message is 16 bytes, + * but that is because the name there is not NUL terminated, only NUL + * padded. */ +#define TEGRA_RPC_MAX_NAME_LEN 17 + +struct tegra_rpc_port_desc { + char name[TEGRA_RPC_MAX_NAME_LEN]; + int notify_fd; /* fd representing a trpc_sema to signal when a + * message has been received */ +}; + +#define TEGRA_RPC_IOCTL_MAGIC 'r' + +#define TEGRA_RPC_IOCTL_PORT_CREATE _IOW(TEGRA_RPC_IOCTL_MAGIC, 0x20, struct tegra_rpc_port_desc) +#define TEGRA_RPC_IOCTL_PORT_GET_NAME _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x21, char *) +#define TEGRA_RPC_IOCTL_PORT_CONNECT _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x22, long) +#define TEGRA_RPC_IOCTL_PORT_LISTEN _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x23, long) + +#define TEGRA_RPC_IOCTL_MIN_NR _IOC_NR(TEGRA_RPC_IOCTL_PORT_CREATE) +#define TEGRA_RPC_IOCTL_MAX_NR _IOC_NR(TEGRA_RPC_IOCTL_PORT_LISTEN) + +#endif diff --git a/include/linux/tegra_sema.h b/include/linux/tegra_sema.h new file mode 100644 index 000000000000..7b423b6cb5c4 --- /dev/null +++ b/include/linux/tegra_sema.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Dima Zavin <dima@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_SEMA_H +#define __LINUX_TEGRA_SEMA_H + +/* this shares the magic with the tegra RPC and AVP drivers. + * See include/linux/tegra_avp.h and include/linux/tegra_rpc.h */ +#define TEGRA_SEMA_IOCTL_MAGIC 'r' + +/* If IOCTL_WAIT is interrupted by a signal and the timeout was not -1, + * then the value pointed to by the argument will be updated with the amount + * of time remaining for the wait. */ +#define TEGRA_SEMA_IOCTL_WAIT _IOW(TEGRA_SEMA_IOCTL_MAGIC, 0x30, long *) +#define TEGRA_SEMA_IOCTL_SIGNAL _IO(TEGRA_SEMA_IOCTL_MAGIC, 0x31) + +#define TEGRA_SEMA_IOCTL_MIN_NR _IOC_NR(TEGRA_SEMA_IOCTL_WAIT) +#define TEGRA_SEMA_IOCTL_MAX_NR _IOC_NR(TEGRA_SEMA_IOCTL_SIGNAL) + +#endif diff --git a/include/linux/tegra_snor.h b/include/linux/tegra_snor.h new file mode 100644 index 000000000000..e47b82d49fc6 --- /dev/null +++ b/include/linux/tegra_snor.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. + * + * Author: + * Bharath H S <bhs@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * include/linux/tegra_snor.h + * + * MTD mapping driver for the internal SNOR controller in Tegra SoCs + * + */ +#define __BITMASK0(len) (BIT(len) - 1) +#define REG_FIELD(val, start, len) (((val) & __BITMASK0(len)) << (start)) +#define REG_GET_FIELD(val, start, len) (((val) >> (start)) & __BITMASK0(len)) + +/* tegra gmi registers... */ +#define TEGRA_SNOR_CONFIG_REG 0x00 +#define TEGRA_SNOR_NOR_ADDR_PTR_REG 0x08 +#define TEGRA_SNOR_AHB_ADDR_PTR_REG 0x0C +#define TEGRA_SNOR_TIMING0_REG 0x10 +#define TEGRA_SNOR_TIMING1_REG 0x14 +#define TEGRA_SNOR_DMA_CFG_REG 0x20 + +/* config register */ +#define TEGRA_SNOR_CONFIG_GO BIT(31) +#define TEGRA_SNOR_CONFIG_WORDWIDE BIT(30) +#define TEGRA_SNOR_CONFIG_DEVICE_TYPE BIT(29) +#define TEGRA_SNOR_CONFIG_MUX_MODE BIT(28) +#define TEGRA_SNOR_CONFIG_BURST_LEN(val) REG_FIELD((val), 26, 2) +#define TEGRA_SNOR_CONFIG_RDY_ACTIVE BIT(24) +#define TEGRA_SNOR_CONFIG_RDY_POLARITY BIT(23) +#define TEGRA_SNOR_CONFIG_ADV_POLARITY BIT(22) +#define TEGRA_SNOR_CONFIG_OE_WE_POLARITY BIT(21) +#define TEGRA_SNOR_CONFIG_CS_POLARITY BIT(20) +#define TEGRA_SNOR_CONFIG_NOR_DPD BIT(19) +#define TEGRA_SNOR_CONFIG_WP BIT(15) +#define TEGRA_SNOR_CONFIG_PAGE_SZ(val) REG_FIELD((val), 8, 2) +#define TEGRA_SNOR_CONFIG_MST_ENB BIT(7) +#define TEGRA_SNOR_CONFIG_SNOR_CS(val) REG_FIELD((val), 4, 3) +#define TEGRA_SNOR_CONFIG_CE_LAST REG_FIELD(3) +#define TEGRA_SNOR_CONFIG_CE_FIRST REG_FIELD(2) +#define TEGRA_SNOR_CONFIG_DEVICE_MODE(val) REG_FIELD((val), 0, 2) + +/* dma config register */ +#define TEGRA_SNOR_DMA_CFG_GO BIT(31) +#define TEGRA_SNOR_DMA_CFG_BSY BIT(30) +#define TEGRA_SNOR_DMA_CFG_DIR BIT(29) +#define TEGRA_SNOR_DMA_CFG_INT_ENB BIT(28) +#define TEGRA_SNOR_DMA_CFG_INT_STA BIT(27) +#define TEGRA_SNOR_DMA_CFG_BRST_SZ(val) REG_FIELD((val), 24, 3) +#define TEGRA_SNOR_DMA_CFG_WRD_CNT(val) REG_FIELD((val), 2, 14) + +/* timing 0 register */ +#define TEGRA_SNOR_TIMING0_PG_RDY(val) REG_FIELD((val), 28, 4) +#define TEGRA_SNOR_TIMING0_PG_SEQ(val) REG_FIELD((val), 20, 4) +#define TEGRA_SNOR_TIMING0_MUX(val) REG_FIELD((val), 12, 4) +#define TEGRA_SNOR_TIMING0_HOLD(val) REG_FIELD((val), 8, 4) +#define TEGRA_SNOR_TIMING0_ADV(val) REG_FIELD((val), 4, 4) +#define TEGRA_SNOR_TIMING0_CE(val) REG_FIELD((val), 0, 4) + +/* timing 1 register */ +#define TEGRA_SNOR_TIMING1_WE(val) REG_FIELD((val), 16, 8) +#define TEGRA_SNOR_TIMING1_OE(val) REG_FIELD((val), 8, 8) +#define TEGRA_SNOR_TIMING1_WAIT(val) REG_FIELD((val), 0, 8) + +/* SNOR DMA supports 2^14 AHB (32-bit words) + * Maximum data in one transfer = 2^16 bytes + */ +#define TEGRA_SNOR_DMA_LIMIT 0x10000 +#define TEGRA_SNOR_DMA_LIMIT_WORDS (TEGRA_SNOR_DMA_LIMIT >> 2) + +/* Even if BW is 1 MB/s, maximum time to + * transfer SNOR_DMA_LIMIT bytes is 66 ms + */ +#define TEGRA_SNOR_DMA_TIMEOUT_MS 67 + +#define SNOR_CONFIG_MASK 0xFFFFFF8F +#define SNOR_WINDOW_SIZE 0x07FFFFFF diff --git a/include/linux/tegra_spdif.h b/include/linux/tegra_spdif.h new file mode 100644 index 000000000000..8d7f6457a0d1 --- /dev/null +++ b/include/linux/tegra_spdif.h @@ -0,0 +1,56 @@ +/* include/linux/tegra_spdif.h + * + * SPDIF audio driver for NVIDIA Tegra SoCs + * + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _TEGRA_SPDIF_H +#define _TEGRA_SPDIF_H + +#include <linux/ioctl.h> + +#define TEGRA_SPDIF_MAGIC 's' + + + +struct tegra_audio_buf_config { + unsigned size; /* order */ + unsigned threshold; /* order */ + unsigned chunk; /* order */ +}; + + + +#define TEGRA_AUDIO_OUT_SET_BUF_CONFIG _IOW(TEGRA_SPDIF_MAGIC, 0, \ + const struct tegra_audio_buf_config *) +#define TEGRA_AUDIO_OUT_GET_BUF_CONFIG _IOR(TEGRA_SPDIF_MAGIC, 1, \ + struct tegra_audio_buf_config *) + +#define TEGRA_AUDIO_OUT_GET_ERROR_COUNT _IOR(TEGRA_SPDIF_MAGIC, 2, \ + unsigned *) + +struct tegra_audio_out_preload { + void *data; + size_t len; + size_t len_written; +}; + +#define TEGRA_AUDIO_OUT_PRELOAD_FIFO _IOWR(TEGRA_SPDIF_MAGIC, 3, \ + struct tegra_audio_out_preload *) + +#endif/*_TEGRA_SPDIF_H*/ diff --git a/include/linux/tegra_uart.h b/include/linux/tegra_uart.h new file mode 100644 index 000000000000..121983ee8421 --- /dev/null +++ b/include/linux/tegra_uart.h @@ -0,0 +1,49 @@ +/* include/linux/tegra_uart.h + * + * Copyright (C) 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _TEGRA_UART_H_ +#define _TEGRA_UART_H_ + +#include <linux/clk.h> + +struct uart_clk_parent { + const char *name; + struct clk *parent_clk; + unsigned long fixed_clk_rate; +}; + +struct tegra_uart_platform_data { + struct uart_clk_parent *parent_clk_list; + int parent_clk_count; + bool is_loopback; + bool is_irda; + int (*irda_init)(void); + int (*irda_mode_switch)(int); + void (*irda_start)(void); + void (*irda_shutdown)(void); + void (*irda_remove)(void); +}; + +int tegra_uart_is_tx_empty(struct uart_port *); +void tegra_uart_request_clock_on(struct uart_port *); +void tegra_uart_set_mctrl(struct uart_port *, unsigned int); +void tegra_uart_request_clock_off(struct uart_port *uport); + +#endif /* _TEGRA_UART_H_ */ + diff --git a/include/linux/thermal.h b/include/linux/thermal.h index a386a1cbb6e1..c7668e2cbed3 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -185,6 +185,16 @@ struct thermal_zone_device { /* Structure that holds thermal governor information */ struct thermal_governor { char name[THERMAL_NAME_LENGTH]; + + /* + * The start and stop operations will be called when thermal zone is + * registered and when change governor via sysfs. They will not be + * called when cooling devices are registered or when cooling devices + * are bound to thermal zones. + */ + int (*start)(struct thermal_zone_device *tz); + void (*stop)(struct thermal_zone_device *tz); + int (*throttle)(struct thermal_zone_device *tz, int trip); struct list_head governor_list; }; @@ -241,6 +251,8 @@ struct thermal_cooling_device *thermal_cooling_device_register(char *, void *, void thermal_cooling_device_unregister(struct thermal_cooling_device *); struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name); int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp); +struct thermal_zone_device *thermal_zone_device_find(void *data, + int (*match)(struct thermal_zone_device *, void *)); int get_tz_trend(struct thermal_zone_device *, int); struct thermal_instance *get_thermal_instance(struct thermal_zone_device *, diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h index 932b76392248..b768209c32a7 100644 --- a/include/linux/ti_wilink_st.h +++ b/include/linux/ti_wilink_st.h @@ -389,7 +389,12 @@ void st_ll_disable(struct st_data_s *); * various funcs used by ST core to set/get the various PM states * of the chip. */ + +#ifdef CONFIG_TI_ST unsigned long st_ll_getstate(struct st_data_s *); +#else +static inline unsigned long st_ll_getstate(struct st_data_s *ll){ return 0; } +#endif unsigned long st_ll_sleep_state(struct st_data_s *, unsigned char); void st_ll_wakeup(struct st_data_s *); diff --git a/include/linux/tick.h b/include/linux/tick.h index 9180f4b85e6d..62bd8b72873c 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -174,10 +174,4 @@ static inline void tick_nohz_task_switch(struct task_struct *tsk) { } #endif -# ifdef CONFIG_CPU_IDLE_GOV_MENU -extern void menu_hrtimer_cancel(void); -# else -static inline void menu_hrtimer_cancel(void) {} -# endif /* CONFIG_CPU_IDLE_GOV_MENU */ - #endif diff --git a/include/linux/tps80031-charger.h b/include/linux/tps80031-charger.h new file mode 100644 index 000000000000..26c228edc306 --- /dev/null +++ b/include/linux/tps80031-charger.h @@ -0,0 +1,62 @@ +/* + * include/linux/tps80031-charger.h + * + * Battery charger driver interface for TI TPS80031 PMIC + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef __LINUX_TPS80031_CHARGER_H +#define __LINUX_TPS80031_CHARGER_H + +#include <linux/regulator/machine.h> + +enum charging_states { + charging_state_idle, + charging_state_charging_in_progress, + charging_state_charging_completed, + charging_state_charging_stopped, +}; + +/** + * Callback type definition which is called when any state changed in the + * charging. + */ +typedef void (*charging_callback_t)(enum charging_states state, void *args); + +struct tps80031_charger_platform_data { + int regulator_id; + int max_charge_volt_mV; + int max_charge_current_mA; + int charging_term_current_mA; + int refresh_time; + int irq_base; + int watch_time_sec; + struct regulator_consumer_supply *consumer_supplies; + int num_consumer_supplies; + int (*board_init)(void *board_data); + void *board_data; +}; + +/** + * Register the callback function for the client. This callback gets called + * when there is any change in the chanrging states. + */ +extern int register_charging_state_callback(charging_callback_t cb, void *args); + +#endif /*__LINUX_TPS80031_CHARGER_H */ diff --git a/include/linux/tracedump.h b/include/linux/tracedump.h new file mode 100644 index 000000000000..9e86946e354e --- /dev/null +++ b/include/linux/tracedump.h @@ -0,0 +1,43 @@ +/* + * include/linux/tracedump.h + * + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef _LINUX_KERNEL_TRACEDUMP_H +#define _LINUX_KERNEL_TRACEDUMP_H + +/* tracedump + * This module provides additional mechanisms for retreiving tracing data. + * For details on configurations, parameters and usage, see tracedump.txt. + */ + +#define TD_NO_PRINT 0 +#define TD_PRINT_CONSOLE 1 +#define TD_PRINT_USER 2 + +/* Dump the tracer to console */ +int tracedump_dump(size_t max_out); + +/* Dumping functions */ +int tracedump_init(void); +ssize_t tracedump_all(int print_to); +ssize_t tracedump_next(size_t max_out, int print_to); +int tracedump_reset(void); +int tracedump_deinit(void); + +#endif /* _LINUX_KERNEL_TRACEDUMP_H */ diff --git a/include/linux/tracelevel.h b/include/linux/tracelevel.h new file mode 100644 index 000000000000..ac3351c6ed85 --- /dev/null +++ b/include/linux/tracelevel.h @@ -0,0 +1,42 @@ +/* + * include/linux/tracelevel.c + * + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef _TRACELEVEL_H +#define _TRACELEVEL_H + +/* tracelevel allows a subsystem author to add priorities to + * trace_events. For usage details, see tracelevel.txt. + */ + +#define TRACELEVEL_ERR 3 +#define TRACELEVEL_WARN 2 +#define TRACELEVEL_INFO 1 +#define TRACELEVEL_DEBUG 0 + +#define TRACELEVEL_MAX TRACELEVEL_ERR +#define TRACELEVEL_DEFAULT TRACELEVEL_ERR + +int __tracelevel_register(char *name, unsigned int level); +int tracelevel_set_level(int level); + +#define tracelevel_register(name, level) \ + __tracelevel_register(#name, level) + +#endif /* _TRACELEVEL_H */ diff --git a/include/linux/tty.h b/include/linux/tty.h index 8780bd2a272a..ceef1181e797 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -269,7 +269,7 @@ struct tty_struct { void *driver_data; struct list_head tty_files; -#define N_TTY_BUF_SIZE 4096 +#define N_TTY_BUF_SIZE 32768 unsigned char closing:1; unsigned short minimum_to_wake; diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index 1b7519a8c0bf..19ae216896f3 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2011 NVIDIA Corporation. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,68 +16,103 @@ #ifndef __TEGRA_USB_PHY_H #define __TEGRA_USB_PHY_H -#include <linux/clk.h> -#include <linux/usb/otg.h> - -struct tegra_utmip_config { - u8 hssync_start_delay; - u8 elastic_limit; - u8 idle_wait_delay; - u8 term_range_adj; - u8 xcvr_setup; - u8 xcvr_lsfslew; - u8 xcvr_lsrslew; -}; - -struct tegra_ulpi_config { - int reset_gpio; - const char *clk; -}; - -enum tegra_usb_phy_port_speed { - TEGRA_USB_PHY_PORT_SPEED_FULL = 0, - TEGRA_USB_PHY_PORT_SPEED_LOW, - TEGRA_USB_PHY_PORT_SPEED_HIGH, -}; - -enum tegra_usb_phy_mode { - TEGRA_USB_PHY_MODE_DEVICE, - TEGRA_USB_PHY_MODE_HOST, -}; - -struct tegra_xtal_freq; - -struct tegra_usb_phy { - int instance; - const struct tegra_xtal_freq *freq; - void __iomem *regs; - void __iomem *pad_regs; - struct clk *clk; - struct clk *pll_u; - struct clk *pad_clk; - enum tegra_usb_phy_mode mode; - void *config; - struct usb_phy *ulpi; - struct usb_phy u_phy; - struct device *dev; - bool is_legacy_phy; - bool is_ulpi_phy; - void (*set_pts)(struct usb_phy *x, u8 pts_val); - void (*set_phcd)(struct usb_phy *x, bool enable); -}; - -struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, - void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode, - void (*set_pts)(struct usb_phy *x, u8 pts_val), - void (*set_phcd)(struct usb_phy *x, bool enable)); - -void tegra_usb_phy_preresume(struct usb_phy *phy); - -void tegra_usb_phy_postresume(struct usb_phy *phy); - -void tegra_ehci_phy_restore_start(struct usb_phy *phy, - enum tegra_usb_phy_port_speed port_speed); - -void tegra_ehci_phy_restore_end(struct usb_phy *phy); +/** + * Tegra USB phy opaque handle + */ +struct tegra_usb_phy; + +/** + * Opens the usb phy associated to the USB platform device + * tegra usb phy open must be called before accessing any phy APIs + */ +struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev); + +/** + * Handles interrupts specific to the phy interface + * Note: udc or ehci driver will handle the controller interrupts + */ +int tegra_usb_phy_irq(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality after driver reset + */ +int tegra_usb_phy_reset(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality before driver suspend + * Also, handles platform specific pre suspend functions + */ +int tegra_usb_phy_pre_suspend(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality after driver suspend + */ +int tegra_usb_phy_post_suspend(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality before driver resume + * Also, handles platform specific pre resume functions + */ +int tegra_usb_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup); + +/** + * Handles phy interface specific functionality after driver resume + */ +int tegra_usb_phy_post_resume(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality during port power on + */ +int tegra_usb_phy_port_power(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality during bus reset + */ +int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality for turning off the phy to + * put the phy in low power mode + */ +int tegra_usb_phy_power_off(struct tegra_usb_phy *phy); + +/** + * Handles phy interface specific functionality for turning on the phy to + * bring phy out of low power mode + */ +int tegra_usb_phy_power_on(struct tegra_usb_phy *phy); + +/** + * Indicates whether phy registers are accessible or not + * if phy is powered off then returns false else true + */ +bool tegra_usb_phy_hw_accessible(struct tegra_usb_phy *phy); + +/** + * Indicates whether compliance charger is connected or not + * if compliance charger is detected then returns true else false + */ +bool tegra_usb_phy_charger_detected(struct tegra_usb_phy *phy); + +/** + * Indicates whether phy resumed due to the remote wake event or not + * returns true if remote wake is detected. + */ +bool tegra_usb_phy_remote_wakeup(struct tegra_usb_phy *phy); + +/** + * Indicates controller has HOST PC register set or not + */ +bool tegra_usb_phy_has_hostpc(struct tegra_usb_phy *phy); + +/** + * Indicates controller port supports OTG or not + */ +bool tegra_usb_phy_otg_supported(struct tegra_usb_phy *phy); + + +void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy); + +void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy); #endif /* __TEGRA_USB_PHY_H */ diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h index f18d64129f99..1bbd28ed95b2 100644 --- a/include/linux/usb/usbnet.h +++ b/include/linux/usb/usbnet.h @@ -104,7 +104,7 @@ struct driver_info { #define FLAG_LINK_INTR 0x0800 /* updates link (carrier) status */ -#define FLAG_POINTTOPOINT 0x1000 /* possibly use "usb%d" names */ +#define FLAG_POINTTOPOINT 0x1000 /* possibly use "usb%d" names */ /* * Indicates to usbnet, that USB driver accumulates multiple IP packets. @@ -113,6 +113,7 @@ struct driver_info { #define FLAG_MULTI_PACKET 0x2000 #define FLAG_RX_ASSEMBLE 0x4000 /* rx packets may span >1 frames */ #define FLAG_NOARP 0x8000 /* device can't do ARP */ +#define FLAG_RMNET 0x10000 /* use "rmnet%d" names */ /* init device ... can sleep, or cause probe() failure */ int (*bind)(struct usbnet *, struct usb_interface *); diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h index b6b215f13b45..14105c26a836 100644 --- a/include/linux/user_namespace.h +++ b/include/linux/user_namespace.h @@ -23,6 +23,7 @@ struct user_namespace { struct uid_gid_map projid_map; atomic_t count; struct user_namespace *parent; + int level; kuid_t owner; kgid_t group; unsigned int proc_inum; diff --git a/include/linux/virtio.h b/include/linux/virtio.h index 9ff8645b7e0b..72398eea6e86 100644 --- a/include/linux/virtio.h +++ b/include/linux/virtio.h @@ -70,6 +70,10 @@ void virtqueue_disable_cb(struct virtqueue *vq); bool virtqueue_enable_cb(struct virtqueue *vq); +unsigned virtqueue_enable_cb_prepare(struct virtqueue *vq); + +bool virtqueue_poll(struct virtqueue *vq, unsigned); + bool virtqueue_enable_cb_delayed(struct virtqueue *vq); void *virtqueue_detach_unused_buf(struct virtqueue *vq); diff --git a/include/linux/wait.h b/include/linux/wait.h index 1133695eb067..c8e576022234 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -805,6 +805,63 @@ do { \ __ret; \ }) +#define __wait_event_interruptible_lock_irq_timeout(wq, condition, \ + lock, ret) \ +do { \ + DEFINE_WAIT(__wait); \ + \ + for (;;) { \ + prepare_to_wait(&wq, &__wait, TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (signal_pending(current)) { \ + ret = -ERESTARTSYS; \ + break; \ + } \ + spin_unlock_irq(&lock); \ + ret = schedule_timeout(ret); \ + spin_lock_irq(&lock); \ + if (!ret) \ + break; \ + } \ + finish_wait(&wq, &__wait); \ +} while (0) + +/** + * wait_event_interruptible_lock_irq_timeout - sleep until a condition gets true or a timeout elapses. + * The condition is checked under the lock. This is expected + * to be called with the lock taken. + * @wq: the waitqueue to wait on + * @condition: a C expression for the event to wait for + * @lock: a locked spinlock_t, which will be released before schedule() + * and reacquired afterwards. + * @timeout: timeout, in jiffies + * + * The process is put to sleep (TASK_INTERRUPTIBLE) until the + * @condition evaluates to true or signal is received. The @condition is + * checked each time the waitqueue @wq is woken up. + * + * wake_up() has to be called after changing any variable that could + * change the result of the wait condition. + * + * This is supposed to be called while holding the lock. The lock is + * dropped before going to sleep and is reacquired afterwards. + * + * The function returns 0 if the @timeout elapsed, -ERESTARTSYS if it + * was interrupted by a signal, and the remaining jiffies otherwise + * if the condition evaluated to true before the timeout elapsed. + */ +#define wait_event_interruptible_lock_irq_timeout(wq, condition, lock, \ + timeout) \ +({ \ + int __ret = timeout; \ + \ + if (!(condition)) \ + __wait_event_interruptible_lock_irq_timeout( \ + wq, condition, lock, __ret); \ + __ret; \ +}) + /* * These are the old interfaces to sleep waiting for an event. diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index a54fe82e704b..5fd17dcf17a5 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -36,6 +36,7 @@ enum { WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ }; + /* TCXO clock values */ enum { WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */ @@ -49,7 +50,8 @@ enum { }; struct wl12xx_platform_data { - void (*set_power)(bool enable); + int (*set_power)(int power_on); + int (*set_carddetect)(int val); /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ int irq; bool use_eeprom; diff --git a/include/media/ad5816.h b/include/media/ad5816.h new file mode 100644 index 000000000000..30baa5f46c4b --- /dev/null +++ b/include/media/ad5816.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2011-2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __AD5816_H__ +#define __AD5816_H__ + +#include <media/nvc_focus.h> +#include <media/nvc.h> + +struct ad5816_power_rail { + struct regulator *vdd; + struct regulator *vdd_i2c; +}; + +struct ad5816_platform_data { + int cfg; + int num; + int sync; + const char *dev_name; + struct nvc_focus_nvc (*nvc); + struct nvc_focus_cap (*cap); + struct ad5816_pdata_info (*info); + int gpio_count; + struct nvc_gpio_pdata *gpio; + int (*power_on)(struct ad5816_power_rail *pw); + int (*power_off)(struct ad5816_power_rail *pw); +}; + +struct ad5816_pdata_info { + float focal_length; + float fnumber; + __u32 settle_time; + __s16 pos_low; + __s16 pos_high; + __s16 limit_low; + __s16 limit_high; + int move_timeoutms; + __u32 focus_hyper_ratio; + __u32 focus_hyper_div; +}; + +// Register Definitions +#define IC_INFO 0x00 +#define IC_VERSION 0x01 +#define CONTROL 0x02 +#define VCM_CODE_MSB 0x03 +#define VCM_CODE_LSB 0x04 +#define STATUS 0x05 +#define MODE 0x06 +#define VCM_FREQ 0x07 +#define VCM_THRESHOLD 0x08 +#define SCL_LOW_DETECTION 0xC0 + + +#endif +/* __AD5816_H__ */ diff --git a/include/media/ad5820.h b/include/media/ad5820.h new file mode 100644 index 000000000000..c3e710113402 --- /dev/null +++ b/include/media/ad5820.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010-2011 NVIDIA Corporation. + * + * Contributors: + * Sachin Nikam <snikam@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __AD5820_H__ +#define __AD5820_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define AD5820_IOCTL_GET_CONFIG _IOR('o', 1, struct ad5820_config) +#define AD5820_IOCTL_SET_POSITION _IOW('o', 2, u32) + +struct ad5820_config { + __u32 settle_time; + __u32 actuator_range; + __u32 pos_low; + __u32 pos_high; + float focal_length; + float fnumber; + float max_aperture; +}; + +#endif /* __AD5820_H__ */ + diff --git a/include/media/ar0832_main.h b/include/media/ar0832_main.h new file mode 100644 index 000000000000..3cc1afcb941a --- /dev/null +++ b/include/media/ar0832_main.h @@ -0,0 +1,99 @@ +/* +* ar0832_main.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __AR0832_MAIN_H__ +#define __AR0832_MAIN_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ +#include <media/nvc_focus.h> + +#define AR0832_IOCTL_SET_MODE _IOW('o', 0x01, struct ar0832_mode) +#define AR0832_IOCTL_SET_FRAME_LENGTH _IOW('o', 0x02, __u32) +#define AR0832_IOCTL_SET_COARSE_TIME _IOW('o', 0x03, __u32) +#define AR0832_IOCTL_SET_GAIN _IOW('o', 0x04, __u16) +#define AR0832_IOCTL_GET_STATUS _IOR('o', 0x05, __u8) +#define AR0832_IOCTL_GET_OTP _IOR('o', 0x06, struct ar0832_otp_data) +#define AR0832_IOCTL_TEST_PATTERN _IOW('o', 0x07, enum ar0832_test_pattern) +#define AR0832_IOCTL_SET_POWER_ON _IOW('o', 0x08, struct ar0832_mode) +#define AR0832_IOCTL_SET_SENSOR_REGION _IOW('o', 0x09, struct ar0832_stereo_region) + +#define AR0832_FOCUSER_IOCTL_GET_CONFIG _IOR('o', 0x10, struct nv_focuser_config) +#define AR0832_FOCUSER_IOCTL_SET_POSITION _IOW('o', 0x11, __u32) + +#define AR0832_IOCTL_GET_SENSOR_ID _IOR('o', 0x12, __u16) +#define AR0832_FOCUSER_IOCTL_SET_CONFIG _IOW('o', 0x13, struct nv_focuser_config) + +#define AR0832_SENSOR_ID_8141 0x1006 +#define AR0832_SENSOR_ID_8140 0x3006 + +enum ar0832_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ar0832_otp_data { + /* Only the first 5 bytes are actually used. */ + __u8 sensor_serial_num[6]; + __u8 part_num[8]; + __u8 lens_id[1]; + __u8 manufacture_id[2]; + __u8 factory_id[2]; + __u8 manufacture_date[9]; + __u8 manufacture_line[2]; + + __u32 module_serial_num; + __u8 focuser_liftoff[2]; + __u8 focuser_macro[2]; + __u8 reserved1[12]; + __u8 shutter_cal[16]; + __u8 reserved2[183]; + + /* Big-endian. CRC16 over 0x00-0x41 (inclusive) */ + __u16 crc; + __u8 reserved3[3]; + __u8 auto_load[2]; +} __attribute__ ((packed)); + +struct ar0832_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + int stereo; +}; + +struct ar0832_point{ + int x; + int y; +}; + +struct ar0832_reg { + __u16 addr; + __u16 val; +}; + +struct ar0832_stereo_region { + int camera_index; + struct ar0832_point image_start; + struct ar0832_point image_end; +}; + + +#ifdef __KERNEL__ +struct ar0832_platform_data { + int (*power_on)(struct device *, int is_stereo); + int (*power_off)(struct device *, int is_stereo); + char *id; +}; +#endif /* __KERNEL__ */ + +#endif diff --git a/include/media/as364x.h b/include/media/as364x.h new file mode 100644 index 000000000000..c1872b5fe27b --- /dev/null +++ b/include/media/as364x.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __AS364X_H__ +#define __AS364X_H__ + +#include <media/nvc_torch.h> + +enum { + AS3643, + AS3647, + AS3648, + AS364X_NUM, +}; + +struct as364x_config { + bool use_tx_mask; /* enable TXMASK */ + u16 I_limit_mA; /* AS3647/AS3648: 2000, 2500, 3000, 3500 mA + * AS3643: 1000, 1500, 2000, 2500 mA for the coil*/ + u16 txmasked_current_mA; /* 57,113,...847, roughly 56.47 mA steps */ + u16 vin_low_v_run_mV; /* 0xffff=off, 3000, 3070, 3140, 3220, 3300, + 3338, 3470 mV battery limit for dynamic flash + reduction */ + u16 vin_low_v_mV; /* 0xffff=off, 3000, 3070, 3140, 3220, 3300, 3338, + 3470mV battery limit for flash denial */ + u8 strobe_type; /* 1=edge, 2=level */ + u8 inct_pwm; /* pwm duty cycle for indicator or low current mode */ + bool freq_switch_on; + /* balance the current sinks for unmatched LED forward valtages */ + bool load_balance_on; + bool led_off_when_vin_low; /* if 0 txmask current is used */ + bool boost_mode; /* all LED current are increased by 11% */ + /* LED configuration, two identical leds must be connected. */ + u16 max_total_current_mA; /* Both leds' maximum peak current in mA */ + u16 max_peak_current_mA; /* This led's maximum peak current in mA */ + u16 max_peak_duration_ms; /* the maximum duration max_peak_current_mA + can be applied */ + u16 max_sustained_current_mA; /* This leds maximum sustained current + in mA */ + u16 min_current_mA; /* This leds minimum current in mA, desired + values smaller than this will be realised + using PWM. */ +}; + +struct as364x_power_rail { + struct regulator *v_in; + struct regulator *v_i2c; +}; + +struct as364x_platform_data { + struct as364x_config config; + u32 type; /* flash device type, refer to as364x_type */ + u32 led_mask; /* which led(s) enabled, 1/2/3 - left/right/both */ + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state pinstate; /* see notes in driver */ + unsigned gpio_strobe; /* GPIO connected to the ACT signal */ + bool strobe_low_act; /* strobe state active low */ + + int (*power_on_callback)(struct as364x_power_rail *pw); + int (*power_off_callback)(struct as364x_power_rail *pw); +}; + +#endif +/* __AS364X_H__ */ diff --git a/include/media/imx091.h b/include/media/imx091.h new file mode 100644 index 000000000000..7f56765cd528 --- /dev/null +++ b/include/media/imx091.h @@ -0,0 +1,59 @@ +/* +* imx091.h +* +* Copyright (c) 2012, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __IMX091_H__ +#define __IMX091_H__ + +#include <media/nvc.h> +#include <media/nvc_image.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum imx091_gpio { + IMX091_GPIO_RESET = 0, + IMX091_GPIO_PWDN, + IMX091_GPIO_GP1, +}; + +/* The enumeration must be in the order the regulators are to be enabled */ +/* See Power Requirements note in the driver */ +enum imx091_vreg { + IMX091_VREG_DVDD = 0, + IMX091_VREG_AVDD, + IMX091_VREG_IOVDD, +}; + +struct imx091_flash_config { + u8 xvs_trigger_enabled; + u8 sdo_trigger_enabled; + u8 adjustable_flash_timing; + u16 pulse_width_uS; +}; + +struct imx091_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; /* see nvc.h GPIO notes */ + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct imx091_flash_config flash_cap; + struct nvc_imager_cap *cap; + unsigned lens_focal_length; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_max_aperture; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_fnumber; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_h; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_v; /* / _INT2FLOAT_DIVISOR */ + struct edp_client edpc_config; + int (*probe_clock)(unsigned long); + int (*power_on)(struct nvc_regulator *); + int (*power_off)(struct nvc_regulator *); +}; + +#endif /* __IMX091_H__ */ diff --git a/include/media/imx132.h b/include/media/imx132.h new file mode 100644 index 000000000000..01d7c67d94b7 --- /dev/null +++ b/include/media/imx132.h @@ -0,0 +1,70 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * NVIDIA Corporation and its licensors retain all intellectual property + * and proprietary rights in and to this software and related documentation + * and any modifications thereto. Any use, reproduction, disclosure or + * distribution of this software and related documentation without an express + * license agreement from NVIDIA Corporation is strictly prohibited. + */ + +#ifndef __IMX132_H__ +#define __IMX132_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define IMX132_IOCTL_SET_MODE _IOW('o', 1, struct imx132_mode) +#define IMX132_IOCTL_GET_STATUS _IOR('o', 2, __u8) +#define IMX132_IOCTL_SET_FRAME_LENGTH _IOW('o', 3, __u32) +#define IMX132_IOCTL_SET_COARSE_TIME _IOW('o', 4, __u32) +#define IMX132_IOCTL_SET_GAIN _IOW('o', 5, __u16) +#define IMX132_IOCTL_GET_SENSORDATA _IOR('o', 6, struct imx132_sensordata) +#define IMX132_IOCTL_SET_GROUP_HOLD _IOW('o', 7, struct imx132_ae) + +/* IMX132 registers */ +#define IMX132_GROUP_PARAM_HOLD (0x0104) +#define IMX132_COARSE_INTEGRATION_TIME_15_8 (0x0202) +#define IMX132_COARSE_INTEGRATION_TIME_7_0 (0x0203) +#define IMX132_ANA_GAIN_GLOBAL (0x0205) +#define IMX132_FRAME_LEN_LINES_15_8 (0x0340) +#define IMX132_FRAME_LEN_LINES_7_0 (0x0341) + +#define NUM_OF_FRAME_LEN_REG 2 +#define NUM_OF_COARSE_TIME_REG 2 +#define NUM_OF_SENSOR_ID_SPECIFIC_REG 8 +struct imx132_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct imx132_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +struct imx132_sensordata { + __u32 fuse_id_size; + __u8 fuse_id[16]; +}; + +#ifdef __KERNEL__ +struct imx132_power_rail { + struct regulator *dvdd; + struct regulator *avdd; + struct regulator *iovdd; +}; + +struct imx132_platform_data { + int (*power_on)(struct imx132_power_rail *pw); + int (*power_off)(struct imx132_power_rail *pw); +}; +#endif /* __KERNEL__ */ + +#endif /* __IMX132_H__ */ diff --git a/include/media/max77665-flash.h b/include/media/max77665-flash.h new file mode 100644 index 000000000000..fc1edc6917c5 --- /dev/null +++ b/include/media/max77665-flash.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MAX77665_H__ +#define __MAX77665_H__ + +#include <media/nvc_torch.h> + +struct max77665_f_power_rail { + /* to enable the module power */ + struct regulator *vbus; + /* to enable the host interface power */ + struct regulator *vio; + /* to enable the power on i2c bus */ + struct regulator *i2c; +}; + +struct max77665_f_led_config { + u16 color_setting; + u16 flash_torch_ratio; /* max flash to max torch ratio, in 1/1000 */ + u16 granularity; /* 1, 10, 100, ... to carry float settings */ + u16 flash_levels; /* calibrated flash levels < 32 */ + /* this table contains the calibrated flash level - luminance pair */ + struct nvc_torch_lumi_level_v1 *lumi_levels; +}; + +struct max77665_f_config { + u32 led_mask; /* led(s) enabled, 1/2/3 - left/right/both */ + bool synchronized_led; /* if both leds enabled, consider as one. */ + bool flash_on_torch; /* true=high level on the torch_en pin will + turn on flash */ + u16 flash_mode; /* 1=one_shot_mode, flash is triggerred on the + rising edge of FLASHEN/TORCHEN/I2C_bit, and + terminated based on the flash safety timer + value. + 0, 2=run for MAX timer, flash is triggerred + on the rising edge of FLASHEN/TORCHEN/I2C, + and terminated based on the falling edge of + FLASHEN/TORCHEN/I2C_bit and flash safety + timer value, whichever comes first.*/ + u16 torch_trigger_mode; /* 0, 3=torch is triggered via i2c interface. + 1=high level on the flash_en pin will turn + the torch on. + 2=high level on the torch_en pin will turn + the torch on. */ + u16 torch_mode; /* 1=torch safety timer disabled, torch is + controlled solely by the FLASHEN/TORCHEN/I2C. + 2=one_shot_mode, torch is triggerred on the + rising edge of FLASHEN/TORCHEN/I2C_bit, and + terminated based on the torch safety timer + setting. + 0, 3=run MAX timer, torch is triggerred on + the rising edge of FLASHEN/TORCHEN/I2C_bit, + and terminated based on the falling edge of + FLASHEN/TORCHEN/ I2C_bit and torch safety + timer setting, whichever comes first.*/ + u16 adaptive_mode; /* 1=fix mode, 2=adaptive mode + The BYP starts from BOOST_VOUT_FLASH value. + Then increment by 100mV steps until there is + full programmed current across the LED(s). + Fixed mode otherwise: the BYP stays at + BOOST_VOUT_FLASH value */ + u16 boost_vout_flash_mV; /* BOOST_VOUT_FLASH value */ + /* LED configuration, two identical leds must be connected. */ + u16 max_total_current_mA; /* Both leds' maximum peak current in mA */ + u16 max_peak_current_mA; /* This led's maximum peak current in mA */ + u16 max_torch_current_mA; /* This leds maximum torch current in mA */ + u16 max_peak_duration_ms; /* the maximum duration max_peak_current_mA + can be applied */ + u16 max_flash_threshold_mV; /* low battery detection threshold. + 2400mV ~ 3400mV. */ + u16 max_flash_hysteresis_mV; /* low battery detection hysteresis. + 100mV ~ 300mV */ + u16 max_flash_lbdly_f_uS; /* Low battery delay timer for falling edge + detection. Adjustable from 256uS to + 2048uS in 256uS steps. */ + u16 max_flash_lbdly_r_uS; /* Low battery delay timer for raising edge + detection. Adjustable from 256uS to + 2048uS in 256uS steps. */ + struct max77665_f_led_config led_config[2]; +}; + +struct max77665_f_platform_data { + struct max77665_f_config config; + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state pinstate; /* see notes in driver */ + unsigned gpio_strobe; /* GPIO connected to the ACT signal */ + struct edp_client edpc_config; + + int (*poweron_callback)(struct max77665_f_power_rail *pw); + int (*poweroff_callback)(struct max77665_f_power_rail *pw); +}; + +#endif +/* __MAX77665_H__ */ diff --git a/include/media/nvc.h b/include/media/nvc.h new file mode 100644 index 000000000000..ec5d6aecc44d --- /dev/null +++ b/include/media/nvc.h @@ -0,0 +1,286 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_H__ +#define __NVC_H__ + +#include <linux/ioctl.h> + +#define NVC_INT2FLOAT_DIVISOR_1K 1000 +#define NVC_INT2FLOAT_DIVISOR_1M 1000000 +#define NVC_INT2FLOAT_DIVISOR 1000 + +struct nvc_param { + int param; + __u32 sizeofvalue; + void *p_value; +} __packed; + +enum nvc_params { + NVC_PARAM_EXPOSURE = 0, + NVC_PARAM_GAIN, + NVC_PARAM_FRAMERATE, + NVC_PARAM_MAX_FRAMERATE, + NVC_PARAM_INPUT_CLOCK, + NVC_PARAM_LOCUS, + NVC_PARAM_FLASH_CAPS, + NVC_PARAM_FLASH_LEVEL, + NVC_PARAM_FLASH_PIN_STATE, + NVC_PARAM_TORCH_CAPS, + NVC_PARAM_TORCH_LEVEL, + NVC_PARAM_FOCAL_LEN, + NVC_PARAM_MAX_APERTURE, + NVC_PARAM_FNUMBER, + NVC_PARAM_EXPOSURE_LIMITS, + NVC_PARAM_GAIN_LIMITS, + NVC_PARAM_FRAMERATE_LIMITS, + NVC_PARAM_FRAME_RATES, + NVC_PARAM_CLOCK_LIMITS, + NVC_PARAM_EXP_LATCH_TIME, + NVC_PARAM_REGION_USED, + NVC_PARAM_CALIBRATION_DATA, + NVC_PARAM_CALIBRATION_OVERRIDES, + NVC_PARAM_SELF_TEST, + NVC_PARAM_STS, + NVC_PARAM_TESTMODE, + NVC_PARAM_EXPECTED_VALUES, + NVC_PARAM_RESET, + NVC_PARAM_OPTIMIZE_RES, + NVC_PARAM_DETECT_COLOR_TEMP, + NVC_PARAM_LINES_PER_SEC, + NVC_PARAM_CAPS, + NVC_PARAM_CUSTOM_BLOCK_INFO, + NVC_PARAM_STEREO_CAP, + NVC_PARAM_FOCUS_STEREO, + NVC_PARAM_STEREO, + NVC_PARAM_INHERENT_GAIN, + NVC_PARAM_VIEW_ANGLE_H, + NVC_PARAM_VIEW_ANGLE_V, + NVC_PARAM_ISP_SETTING, + NVC_PARAM_OPERATION_MODE, + NVC_PARAM_SUPPORT_ISP, + NVC_PARAM_AWB_LOCK, + NVC_PARAM_AE_LOCK, + NVC_PARAM_RES_CHANGE_WAIT_TIME, + NVC_PARAM_FACTORY_CALIBRATION_DATA, + NVC_PARAM_DEV_ID, + NVC_PARAM_GROUP_HOLD, + NVC_PARAM_SET_SENSOR_FLASH_MODE, + NVC_PARAM_BEGIN_VENDOR_EXTENSIONS = 0x10000000, + NVC_PARAM_CALIBRATION_STATUS, + NVC_PARAM_TEST_PATTERN, + NVC_PARAM_MODULE_INFO, + NVC_PARAM_FLASH_MAX_POWER, + NVC_PARAM_DIRECTION, + NVC_PARAM_SENSOR_TYPE, + NVC_PARAM_DLI_CHECK, + NVC_PARAM_PARALLEL_DLI_CHECK, + NVC_PARAM_BRACKET_CAPS, + NVC_PARAM_NUM, + NVC_PARAM_I2C, + NVC_PARAM_FORCE32 = 0x7FFFFFFF +}; + +/* sync off */ +#define NVC_SYNC_OFF 0 +/* use only this device (the one receiving the call) */ +#define NVC_SYNC_MASTER 1 +/* use only the synced device (the "other" device) */ +#define NVC_SYNC_SLAVE 2 +/* use both synced devices at the same time */ +#define NVC_SYNC_STEREO 3 + +#define NVC_RESET_HARD 0 +#define NVC_RESET_SOFT 1 + +struct nvc_param_isp { + int attr; + void *p_data; + __u32 data_size; +} __packed; + +struct nvc_isp_focus_param { + __s32 min_pos; + __s32 max_pos; + __s32 hyperfocal; + __s32 macro; + __s32 powersave; +} __packed; + +struct nvc_isp_focus_pos { + __u32 is_auto; + __s32 value; +} __packed; + +struct nvc_isp_focus_region { + __u32 num_region; + __s32 value; +} __packed; + +enum nvc_params_isp { + NVC_PARAM_ISP_FOCUS_CAF = 16389, + NVC_PARAM_ISP_FOCUS_CAF_PAUSE, + NVC_PARAM_ISP_FOCUS_CAF_STS, + NVC_PARAM_ISP_FOCUS_POS = 16407, + NVC_PARAM_ISP_FOCUS_RANGE, + NVC_PARAM_ISP_FOCUS_AF_RGN = 16413, + NVC_PARAM_ISP_FOCUS_AF_RGN_MASK, + NVC_PARAM_ISP_FOCUS_AF_RGN_STS, + NVC_PARAM_ISP_FOCUS_CTRL = 16424, + NVC_PARAM_ISP_FOCUS_TRGR, + NVC_PARAM_ISP_FOCUS_STS, +}; + +#define NVC_PARAM_ISP_FOCUS_STS_BUSY 0 +#define NVC_PARAM_ISP_FOCUS_STS_LOCKD 1 +#define NVC_PARAM_ISP_FOCUS_STS_FAILD 2 +#define NVC_PARAM_ISP_FOCUS_STS_ERR 3 + +#define NVC_PARAM_ISP_FOCUS_CTRL_ON 0 +#define NVC_PARAM_ISP_FOCUS_CTRL_OFF 1 +#define NVC_PARAM_ISP_FOCUS_CTRL_AUTO 2 +#define NVC_PARAM_ISP_FOCUS_CTRL_ALOCK 3 + +#define NVC_PARAM_ISP_FOCUS_CAF_CONVRG 1 +#define NVC_PARAM_ISP_FOCUS_CAF_SEARCH 2 + +#define NVC_PARAM_ISP_FOCUS_POS_INF 0 + + +#define NVC_IOCTL_PWR_WR _IOW('o', 102, int) +#define NVC_IOCTL_PWR_RD _IOW('o', 103, int) +#define NVC_IOCTL_PARAM_WR _IOW('o', 104, struct nvc_param) +#define NVC_IOCTL_PARAM_RD _IOWR('o', 105, struct nvc_param) +#define NVC_IOCTL_PARAM_ISP_RD _IOWR('o', 200, struct nvc_param_isp) +#define NVC_IOCTL_PARAM_ISP_WR _IOWR('o', 201, struct nvc_param_isp) + + +#ifdef __KERNEL__ + +#include <linux/regulator/consumer.h> + +/* The NVC_CFG_ defines are for the .cfg entry in the + * platform data structure. + */ +/* Device not registered if not found */ +#define NVC_CFG_NODEV (1 << 0) +/* Don't return errors */ +#define NVC_CFG_NOERR (1 << 1) +/* Always go to _PWR_STDBY instead of _PWR_OFF */ +#define NVC_CFG_OFF2STDBY (1 << 2) +/* Init device at sys boot */ +#define NVC_CFG_BOOT_INIT (1 << 3) +/* Sync mode uses an I2C MUX to send at same time */ +#define NVC_CFG_SYNC_I2C_MUX (1 << 4) + +/* Expected higher level power calls are: + * 1 = OFF + * 2 = STANDBY + * 3 = ON + * These will be multiplied by 2 before given to the driver's PM code that + * uses the _PWR_ defines. This allows us to insert defines to give more power + * granularity and still remain linear with regards to the power usage and + * full power state transition latency for easy implementation of PM + * algorithms. + * The PM actions: + * _PWR_ERR = Non-valid state. + * _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms. + * _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest + * transition time to _PWR_ON is from this state. + * _PWR_STDBY_OFF = Device is useless but powered. No communication possible. + * Device does not retain programming. Main purpose is for + * faster return to _PWR_ON without regulator delays. + * _PWR_STDBY = Device is in standby. Device retains programming. + * _PWR_COMM = Device is powered enough to communicate with the device. + * _PWR_ON = Device is at full power with active output. + * + * The kernel drivers treat these calls as Guaranteed Level Of Service. + */ + +#define NVC_PWR_ERR 0 +#define NVC_PWR_OFF_FORCE 1 +#define NVC_PWR_OFF 2 +#define NVC_PWR_STDBY_OFF 3 +#define NVC_PWR_STDBY 4 +#define NVC_PWR_COMM 5 +#define NVC_PWR_ON 6 + +struct nvc_regulator_init { + unsigned vreg_num; + const char *vreg_name; +}; + +struct nvc_regulator { + bool vreg_flag; + struct regulator *vreg; + const char *vreg_name; +}; + +/* The GPIO mechanism uses the _gpio_type in the device's header file as a key + * to define all the possible GPIO's the device will need. The key is used to + * combine the GPIO's defined in the platform board file using the + * nvc_gpio_pdata structure with the nvc_gpio structure in the nvc kernel + * driver. + */ +struct nvc_gpio_pdata { + /* use a _gpio_type enum from the device's header file */ + unsigned gpio_type; + /* the GPIO system number */ + unsigned gpio; + /* init_en is typically set to true for all GPIO's used by the driver. + * However, some GPIO's are used by multiple drivers (CSI MUX, reset, + * etc.). In this case, this is set true for only one of the drivers + * that uses the GPIO and false for the others. If the platform board + * file initializes the GPIO, then this is false for all of the drivers + * using the GPIO. + */ + bool init_en; + /* this defines the assert level for the general purpose GPIO's + * (_GPIO_TYPE_GPx, etc.). The _GPIO_TYPE_GPx can be used for a GPIO + * that the driver doesn't know about but is needed in order for the + * device to work (CSI select, regulator, etc.). The driver will + * blindly assert the GPIO when the device is operational and deassert + * when the device is turned off. + */ + bool active_high; +}; + +struct nvc_gpio_init { + /* key to match in nvc_gpio_pdata */ + unsigned gpio_type; + /* same as in gpio.h */ + unsigned long flags; + /* same as in gpio.h */ + const char *label; + /* used instead of nvc_gpio_pdata.active_high if use_flags true */ + bool active_high; + /* false if nvc_gpio_pdata.active_high used else flags is used */ + bool use_flags; +}; + +struct nvc_gpio { + unsigned gpio; /* system GPIO number */ + bool own; /* gets set if driver initializes */ + bool active_high; /* used for GP GPIOs */ + bool valid; /* set if struct data is valid */ + bool flag; /* scratch flag for driver implementation */ +}; + +#endif /* __KERNEL__ */ + +#endif /* __NVC_H__ */ + diff --git a/include/media/nvc_focus.h b/include/media/nvc_focus.h new file mode 100644 index 000000000000..4874cf1b7ee4 --- /dev/null +++ b/include/media/nvc_focus.h @@ -0,0 +1,114 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_FOCUS_H__ +#define __NVC_FOCUS_H__ + +/* NVC_FOCUS_CAP_VER0: invalid */ +/* NVC_FOCUS_CAP_VER1: + * __u32 version + * __u32 actuator_range + * __u32 settle_time + */ +#define NVC_FOCUS_CAP_VER1 1 +/* NVC_FOCUS_CAP_VER2 adds: + * __u32 focus_macro; + * __u32 focus_hyper; + * __u32 focus_infinity; + */ +#define NVC_FOCUS_CAP_VER2 2 +#define NVC_FOCUS_CAP_VER 2 /* latest version */ + +#define AF_POS_INVALID_VALUE INT_MAX + +/* These are the slew rate values coming down from the configuration */ +/* Disabled is the same as fastest. Default is the default */ +/* slew rate configuration in the focuser */ +#define SLEW_RATE_DISABLED 0 +#define SLEW_RATE_DEFAULT 1 +#define SLEW_RATE_SLOWEST 9 + + +enum nvc_focus_sts { + NVC_FOCUS_STS_UNKNOWN = 1, + NVC_FOCUS_STS_NO_DEVICE, + NVC_FOCUS_STS_INITIALIZING, + NVC_FOCUS_STS_INIT_ERR, + NVC_FOCUS_STS_WAIT_FOR_MOVE_END, + NVC_FOCUS_STS_WAIT_FOR_SETTLE, + NVC_FOCUS_STS_LENS_SETTLED, + NVC_FOCUS_STS_FORCE32 = 0x7FFFFFFF +}; + +struct nvc_focus_nvc { + __u32 focal_length; + __u32 fnumber; + __u32 max_aperature; +} __packed; + +struct nvc_focus_cap { + __u32 version; + __s32 actuator_range; + __u32 settle_time; + __s32 focus_macro; + __s32 focus_hyper; + __s32 focus_infinity; + __u32 slew_rate; + __u32 position_translate; +} __packed; + + +#define NV_FOCUSER_SET_MAX 10 +#define NV_FOCUSER_SET_DISTANCE_PAIR 16 + +struct nv_focuser_set_dist_pairs { + __s32 fdn; + __s32 distance; +} __packed; + +struct nv_focuser_set { + __s32 posture; + __s32 macro; + __s32 hyper; + __s32 inf; + __s32 hysteresis; + __u32 settle_time; + __s32 macro_offset; + __s32 inf_offset; + __u32 num_dist_pairs; + struct nv_focuser_set_dist_pairs + dist_pair[NV_FOCUSER_SET_DISTANCE_PAIR]; +} __packed; + +struct nv_focuser_config { + __u32 focal_length; + __u32 fnumber; + __u32 max_aperture; + __u32 range_ends_reversed; + __s32 pos_working_low; + __s32 pos_working_high; + __s32 pos_actual_low; + __s32 pos_actual_high; + __u32 slew_rate; + __u32 circle_of_confusion; + __u32 num_focuser_sets; + struct nv_focuser_set focuser_set[NV_FOCUSER_SET_MAX]; +} __packed; + + +#endif /* __NVC_FOCUS_H__ */ + diff --git a/include/media/nvc_image.h b/include/media/nvc_image.h new file mode 100644 index 000000000000..aa56a4103a55 --- /dev/null +++ b/include/media/nvc_image.h @@ -0,0 +1,256 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_IMAGE_H__ +#define __NVC_IMAGE_H__ + +#include <linux/ioctl.h> + +#define NVC_IMAGER_API_CAPS_VER 2 +#define NVC_IMAGER_API_STATIC_VER 1 +#define NVC_IMAGER_API_DYNAMIC_VER 1 +#define NVC_IMAGER_API_BAYER_VER 1 + +#define NVC_IMAGER_TEST_NONE 0 +#define NVC_IMAGER_TEST_COLORBARS 1 +#define NVC_IMAGER_TEST_CHECKERBOARD 2 +#define NVC_IMAGER_TEST_WALKING1S 3 + +#define NVC_IMAGER_CROPMODE_NONE 1 +#define NVC_IMAGER_CROPMODE_PARTIAL 2 + +#define NVC_IMAGER_TYPE_HUH 0 +#define NVC_IMAGER_TYPE_RAW 1 +#define NVC_IMAGER_TYPE_SOC 2 + +/** + * Defines camera imager types. + * Mirrors "NvOdmImagerRegion" in "imager/include/nvodm_imager.h". + * These must remain in sync. + */ +#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_8 1 +#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_10 2 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_A 3 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_B 4 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_C 5 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_AB 6 +#define NVC_IMAGER_SENSOR_INTERFACE_CCIR 7 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST 8 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_A 9 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_B 10 +#define NVC_IMAGER_SENSOR_INTERFACE_NUM 11 + +#define NVC_IMAGER_IDENTIFIER_MAX 32 +#define NVC_IMAGER_FORMAT_MAX 4 +#define NVC_IMAGER_CLOCK_PROFILE_MAX 2 +#define NVC_IMAGER_CAPABILITIES_VERSION2 ((0x3434 << 16) | 2) + +#define NVC_IMAGER_INT2FLOAT_DIVISOR 1000 + +#define NVC_FOCUS_INTERNAL (0x665F4E5643414D69ULL) +#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF)) +#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF)) + + +struct nvc_imager_static_nvc { + __u32 api_version; + __u32 sensor_type; + __u32 bits_per_pixel; + __u32 sensor_id; + __u32 sensor_id_minor; + __u32 focal_len; + __u32 max_aperture; + __u32 fnumber; + __u32 view_angle_h; + __u32 view_angle_v; + __u32 stereo_cap; + __u32 res_chg_wait_time; + __u8 support_isp; + __u8 align1; + __u8 align2; + __u8 align3; + __u8 fuse_id[16]; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_dynamic_nvc { + __u32 api_version; + __s32 region_start_x; + __s32 region_start_y; + __u32 x_scale; + __u32 y_scale; + __u32 bracket_caps; + __u32 flush_count; + __u32 init_intra_frame_skip; + __u32 ss_intra_frame_skip; + __u32 ss_frame_number; + __u32 coarse_time; + __u32 max_coarse_diff; + __u32 min_exposure_course; + __u32 max_exposure_course; + __u32 diff_integration_time; + __u32 line_length; + __u32 frame_length; + __u32 min_frame_length; + __u32 max_frame_length; + __u32 min_gain; + __u32 max_gain; + __u32 inherent_gain; + __u32 inherent_gain_bin_en; + __u8 support_bin_control; + __u8 support_fast_mode; + __u8 align2; + __u8 align3; + __u32 pll_mult; + __u32 pll_div; + __u32 mode_sw_wait_frames; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; +} __packed; + +struct nvc_imager_bayer { + __u32 api_version; + __s32 res_x; + __s32 res_y; + __u32 frame_length; + __u32 coarse_time; + __u32 gain; + __u8 bin_en; + __u8 align1; + __u8 align2; + __u8 align3; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_mode { + __s32 res_x; + __s32 res_y; + __s32 active_start_x; + __s32 active_stary_y; + __u32 peak_frame_rate; + __u32 pixel_aspect_ratio; + __u32 pll_multiplier; + __u32 crop_mode; + __u32 rect_left; + __u32 rect_top; + __u32 rect_right; + __u32 rect_bottom; + __u32 point_x; + __u32 point_y; + __u32 type; +} __packed; + +struct nvc_imager_dnvc { + __s32 res_x; + __s32 res_y; + struct nvc_imager_mode *p_mode; + struct nvc_imager_dynamic_nvc *p_dnvc; +} __packed; + +struct nvc_imager_mode_list { + struct nvc_imager_mode *p_modes; + __u32 *p_num_mode; +} __packed; + +struct nvc_clock_profile { + __u32 external_clock_khz; + __u32 clock_multiplier; +} __packed; + +struct nvc_imager_cap { + char identifier[NVC_IMAGER_IDENTIFIER_MAX]; + __u32 sensor_nvc_interface; + __u32 pixel_types[NVC_IMAGER_FORMAT_MAX]; + __u32 orientation; + __u32 direction; + __u32 initial_clock_rate_khz; + struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX]; + __u32 h_sync_edge; + __u32 v_sync_edge; + __u32 mclk_on_vgp0; + __u8 csi_port; + __u8 data_lanes; + __u8 virtual_channel_id; + __u8 discontinuous_clk_mode; + __u8 cil_threshold_settle; + __u8 align1; + __u8 align2; + __u8 align3; + __s32 min_blank_time_width; + __s32 min_blank_time_height; + __u32 preferred_mode_index; + __u64 focuser_guid; + __u64 torch_guid; + __u32 cap_version; + __u8 flash_control_enabled; + __u8 adjustable_flash_timing; + __u8 align4; + __u8 align5; +} __packed; + +struct nvc_imager_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __u32 gain; + __u8 gain_enable; +} __packed; + +union nvc_imager_flash_control { + __u16 mode; + struct { + __u16 enable:1; /* enable the on-sensor flash control */ + __u16 edge_trig_en:1; /* two types of flash controls: + * 0 - LED_FLASH_EN - supports continued + * flash level only, doesn't + * support start edge/repeat/dly. + * 1 - FLASH_EN - supports control pulse + * control pulse attributes are + * defined below. + */ + __u16 start_edge:1; /* flash control pulse rise position: + * 0 - at the start of the next frame. + * 1 - at the effective pixel end + * position of the next frame. + */ + __u16 repeat:1; /* flash control pulse repeat: + * 0 - only triggers one frame. + * 1 - trigger repeats every frame until + * Flash_EN = 0. + */ + __u16 delay_frm:2; /* flash control pulse can be delayed + * in frame units: (0 - 3) - frame + * numbers the pulse is delayed. + */ + } settings; +}; + +#define NVC_IOCTL_CAPS_RD _IOWR('o', 106, struct nvc_imager_cap) +#define NVC_IOCTL_MODE_WR _IOW('o', 107, struct nvc_imager_bayer) +#define NVC_IOCTL_MODE_RD _IOWR('o', 108, struct nvc_imager_mode_list) +#define NVC_IOCTL_STATIC_RD _IOWR('o', 109, struct nvc_imager_static_nvc) +#define NVC_IOCTL_DYNAMIC_RD _IOWR('o', 110, struct nvc_imager_dnvc) + +#endif /* __NVC_IMAGE_H__ */ diff --git a/include/media/nvc_torch.h b/include/media/nvc_torch.h new file mode 100644 index 000000000000..3acdc0cb6ce6 --- /dev/null +++ b/include/media/nvc_torch.h @@ -0,0 +1,113 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_TORCH_H__ +#define __NVC_TORCH_H__ + +struct nvc_torch_level_info { + __s32 guidenum; + __u32 sustaintime; + __s32 rechargefactor; +} __packed; + +struct nvc_torch_pin_state { + __u16 mask; + __u16 values; +} __packed; + +struct nvc_torch_flash_capabilities { + __u32 numberoflevels; + struct nvc_torch_level_info levels[]; +} __packed; + +struct nvc_torch_torch_capabilities { + __u32 numberoflevels; + __s32 guidenum[]; +} __packed; + +/* advanced flash/torch capability settings */ +/* use version number to distinguish between different capability structures */ +#define NVC_TORCH_LED_ATTR_FLASH_SYNC 1 +#define NVC_TORCH_LED_ATTR_IND_FTIMER (1 << 1) +#define NVC_TORCH_LED_ATTR_TORCH_SYNC (1 << 16) +#define NVC_TORCH_LED_ATTR_IND_TTIMER (1 << 17) + +struct nvc_torch_capability_query { + __u8 version; + __u8 flash_num; /* number of flashes supported by this device */ + __u8 torch_num; /* number of torches supported by this device */ + __u8 reserved; + __u32 led_attr; +}; + +#define NVC_TORCH_CAPABILITY_LEGACY 0 +#define NVC_TORCH_CAPABILITY_VER_1 1 + +struct nvc_torch_set_level_v1 { + __u16 ledmask; + __u16 timeout; + /* flash/torch levels mapped to ledmask for lsb to msb respectively */ + __u16 levels[2]; +}; + +struct nvc_torch_lumi_level_v1 { + __u16 guidenum; + __u32 luminance; + __u32 reserved; +}; + +struct nvc_torch_timeout_v1 { + __u32 timeout; + __u32 reserved1; +}; + +struct nvc_torch_timer_capabilities_v1 { + __u32 timeout_num; + /* time out durations in uS */ + struct nvc_torch_timeout_v1 timeouts[]; +}; + +struct nvc_torch_flash_capabilities_v1 { + __u8 version; /* fixed number 1 */ + __u8 led_idx; + __u8 reserved1; + __u8 reserved2; + __u32 attribute; + __u16 granularity; /* 1, 10, 100, ... to carry float settings */ + __u16 flash_torch_ratio; + __u32 timeout_num; + __u32 timeout_off; + __u32 numberoflevels; + struct nvc_torch_lumi_level_v1 levels[]; +}; + +struct nvc_torch_torch_capabilities_v1 { + __u8 version; /* fixed number 1 */ + __u8 led_idx; + __u8 reserved1; + __u8 reserved2; + __u32 attribute; + __u16 granularity; /* 1, 10, 100, ... to carry float settings */ + __u16 reserved4; + __u32 timeout_num; + __u32 timeout_off; + __u32 numberoflevels; + struct nvc_torch_lumi_level_v1 levels[]; +}; + +#endif /* __NVC_TORCH_H__ */ + diff --git a/include/media/ov14810.h b/include/media/ov14810.h new file mode 100644 index 000000000000..c9d6e8147ecd --- /dev/null +++ b/include/media/ov14810.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV14810_H__ +#define __OV14810_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV14810_IOCTL_SET_MODE _IOW('o', 1, struct ov14810_mode) +#define OV14810_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV14810_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV14810_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV14810_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV14810_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV14810_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) + +struct ov14810_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; +#ifdef __KERNEL__ +struct ov14810_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV14810_H__ */ diff --git a/include/media/ov2710.h b/include/media/ov2710.h new file mode 100644 index 000000000000..a3e070b5ade4 --- /dev/null +++ b/include/media/ov2710.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV2710_H__ +#define __OV2710_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV2710_IOCTL_SET_MODE _IOW('o', 1, struct ov2710_mode) +#define OV2710_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV2710_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV2710_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV2710_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV2710_IOCTL_SET_GROUP_HOLD _IOW('o', 6, struct ov2710_ae) + +struct ov2710_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov2710_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +#ifdef __KERNEL__ +struct ov2710_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __OV2710_H__ */ + diff --git a/include/media/ov5640.h b/include/media/ov5640.h new file mode 100644 index 000000000000..da6be4d1d441 --- /dev/null +++ b/include/media/ov5640.h @@ -0,0 +1,73 @@ +/* + * ov5640.h - header for YUV camera sensor OV5640 driver. + * + * Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV5640_H__ +#define __OV5640_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV5640_IOCTL_SET_SENSOR_MODE _IOW('o', 1, struct ov5640_mode) +#define OV5640_IOCTL_GET_SENSOR_STATUS _IOR('o', 2, __u8) +#define OV5640_IOCTL_GET_CONFIG _IOR('o', 3, struct ov5640_config) +#define OV5640_IOCTL_SET_FPOSITION _IOW('o', 4, __u32) +#define OV5640_IOCTL_POWER_LEVEL _IOW('o', 5, __u32) +#define OV5640_IOCTL_GET_AF_STATUS _IOR('o', 6, __u8) +#define OV5640_IOCTL_SET_AF_MODE _IOR('o', 7, __u8) +#define OV5640_IOCTL_SET_WB _IOR('o', 9, __u8) + +#define OV5640_POWER_LEVEL_OFF 0 +#define OV5640_POWER_LEVEL_ON 1 +#define OV5640_POWER_LEVEL_SUS 2 + +struct ov5640_mode { + int xres; + int yres; +}; + +struct ov5640_config { + __u32 settle_time; + __u32 pos_low; + __u32 pos_high; + float focal_length; + float fnumber; +}; + +enum { + OV5640_AF_INIFINITY, + OV5640_AF_TRIGGER, +}; + +enum { + OV5640_WB_AUTO, + OV5640_WB_INCANDESCENT, + OV5640_WB_DAYLIGHT, + OV5640_WB_FLUORESCENT, + OV5640_WB_CLOUDY, +}; + +#ifdef __KERNEL__ +struct ov5640_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __OV5640_H__ */ diff --git a/include/media/ov5650.h b/include/media/ov5650.h new file mode 100644 index 000000000000..f1f2f67acd56 --- /dev/null +++ b/include/media/ov5650.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV5650_H__ +#define __OV5650_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV5650_IOCTL_SET_MODE _IOW('o', 1, struct ov5650_mode) +#define OV5650_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV5650_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV5650_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV5650_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV5650_IOCTL_SET_BINNING _IOW('o', 6, __u8) +#define OV5650_IOCTL_TEST_PATTERN _IOW('o', 7, enum ov5650_test_pattern) +#define OV5650_IOCTL_SET_GROUP_HOLD _IOW('o', 8, struct ov5650_ae) +#define OV5650_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV5650_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) +#define OV5650_IOCTL_GET_SENSORDATA _IOR('o', 12, struct ov5650_sensordata) + +/* OV5650 registers */ +#define OV5650_SRM_GRUP_ACCESS (0x3212) +#define OV5650_ARRAY_CONTROL_01 (0x3621) +#define OV5650_ANALOG_CONTROL_D (0x370D) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_CONTROL_HS_HIGH (0x3800) +#define OV5650_TIMING_CONTROL_HS_LOW (0x3801) +#define OV5650_TIMING_CONTROL_VS_HIGH (0x3802) +#define OV5650_TIMING_CONTROL_VS_LOW (0x3803) +#define OV5650_TIMING_HW_HIGH (0x3804) +#define OV5650_TIMING_HW_LOW (0x3805) +#define OV5650_TIMING_VH_HIGH (0x3806) +#define OV5650_TIMING_VH_LOW (0x3807) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_HREFST_MAN_HIGH (0x3824) +#define OV5650_TIMING_HREFST_MAN_LOW (0x3825) +#define OV5650_H_BINNING_BIT (1 << 7) +#define OV5650_H_SUBSAMPLING_BIT (1 << 6) +#define OV5650_V_BINNING_BIT (1 << 6) +#define OV5650_V_SUBSAMPLING_BIT (1 << 0) +#define OV5650_GROUP_HOLD_BIT (1 << 7) +#define OV5650_GROUP_LAUNCH_BIT (1 << 5) +#define OV5650_GROUP_HOLD_END_BIT (1 << 4) +#define OV5650_GROUP_ID(id) (id) + +enum ov5650_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ov5650_sensordata { + __u32 fuse_id_size; + __u8 fuse_id[16]; +}; + +struct ov5650_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov5650_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +#ifdef __KERNEL__ +struct ov5650_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV5650_H__ */ + diff --git a/include/media/ov9726.h b/include/media/ov9726.h new file mode 100644 index 000000000000..e942000380b4 --- /dev/null +++ b/include/media/ov9726.h @@ -0,0 +1,72 @@ +/* +* ov9726.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __OV9726_H__ +#define __OV9726_H__ + +#include <linux/ioctl.h> + +#define OV9726_I2C_ADDR 0x20 + +#define OV9726_IOCTL_SET_MODE _IOW('o', 1, struct ov9726_mode) +#define OV9726_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV9726_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV9726_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV9726_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV9726_IOCTL_SET_GROUP_HOLD _IOW('o', 6, struct ov9726_ae) + +struct ov9726_mode { + int mode_id; + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov9726_ae { + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + __u8 frame_length_enable; + __u8 coarse_time_enable; + __u8 gain_enable; +}; + +struct ov9726_reg { + __u16 addr; + __u16 val; +}; + +#ifdef __KERNEL__ +#define OV9726_REG_FRAME_LENGTH_HI 0x340 +#define OV9726_REG_FRAME_LENGTH_LO 0x341 +#define OV9726_REG_COARSE_TIME_HI 0x202 +#define OV9726_REG_COARSE_TIME_LO 0x203 +#define OV9726_REG_GAIN_HI 0x204 +#define OV9726_REG_GAIN_LO 0x205 + +#define OV9726_MAX_RETRIES 3 + +#define OV9726_TABLE_WAIT_MS 0 +#define OV9726_TABLE_END 1 + +struct ov9726_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + unsigned gpio_rst; + bool rst_low_active; + unsigned gpio_pwdn; + bool pwdn_low_active; +}; +#endif /* __KERNEL__ */ + +#endif /* __OV9726_H__ */ + diff --git a/include/media/ov9772.h b/include/media/ov9772.h new file mode 100644 index 000000000000..82075b7e384e --- /dev/null +++ b/include/media/ov9772.h @@ -0,0 +1,53 @@ +/* + * nvc_ov9772.h - ov9772 sensor driver + * + * * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * Contributors: + * Phil Breczinski <pbreczinski@nvidia.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __OV9772_H__ +#define __OV9772_H__ + +#include <media/nvc.h> +#include <media/nvc_image.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum ov9772_gpio_type { + OV9772_GPIO_TYPE_SHTDN = 0, + OV9772_GPIO_TYPE_PWRDN, + OV9772_GPIO_TYPE_I2CMUX, + OV9772_GPIO_TYPE_GP1, + OV9772_GPIO_TYPE_GP2, + OV9772_GPIO_TYPE_GP3, +}; + +struct ov9772_power_rail { + struct regulator *dvdd; + struct regulator *avdd; + struct regulator *dovdd; +}; + +struct ov9772_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct nvc_imager_cap *cap; + unsigned lens_focal_length; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_max_aperture; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_fnumber; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_h; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_v; /* / _INT2FLOAT_DIVISOR */ + int (*probe_clock)(unsigned long); + int (*power_on)(struct ov9772_power_rail *); + int (*power_off)(struct ov9772_power_rail *); +}; +#endif /* __OV9772_H__ */ diff --git a/include/media/sh532u.h b/include/media/sh532u.h new file mode 100644 index 000000000000..e9653e68b21f --- /dev/null +++ b/include/media/sh532u.h @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2011-2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SH532U_H__ +#define __SH532U_H__ + +#include <media/nvc.h> +#include <media/nvc_focus.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum sh532u_gpio { + SH532U_GPIO_RESET = 0, + SH532U_GPIO_I2CMUX, + SH532U_GPIO_GP1, + SH532U_GPIO_GP2, + SH532U_GPIO_GP3, +}; + +/* The enumeration must be in the order the regulators are to be enabled */ +/* See Power Requirements note in the driver */ +enum sh532u_vreg { + SH532U_VREG_DVDD = 0, + SH532U_VREG_AVDD, +}; + +struct sh532u_pdata_info { + __s16 pos_low; + __s16 pos_high; + __s16 limit_low; + __s16 limit_high; + int move_timeoutms; + __u32 focus_hyper_ratio; + __u32 focus_hyper_div; +}; + +struct sh532u_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; /* see nvc.h GPIO notes */ + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct nvc_focus_nvc (*nvc); + struct nvc_focus_cap (*cap); + struct sh532u_pdata_info (*info); + __u8 i2c_addr_rom; +}; + +/* Register Definition : Sany Driver IC */ +/* EEPROM addresses */ +#define addrHallOffset 0x10 +#define addrHallBias 0x11 +#define addrInf1 0x12 +#define addrMac1 0x13 +#define addrLoopGainH 0x14 +#define addrLoopGainL 0x15 +#define addrInf2 0x16 +#define addrMac2 0x17 + +#define addrInf1_H 0x20 /* bottom mechanical limit of HVCA */ +#define addrInf1_L 0x21 +#define addrMac1_H 0x22 /* top mechanical limit of HVCA */ +#define addrMac1_L 0x23 +#define addrInf2_H 0x24 /* lens position when object is ?120cm */ +#define addrInf2_L 0x25 +#define addrMac2_H 0x26 /* lens position when object is ?10cm */ +#define addrMac2_L 0x27 +#define addrDacDeltaUp_H 0x28 /* difference between face up and down */ +#define addrDacDeltaUp_L 0x29 +#define addrAFoffset_H 0x2A /* best focus position subtract value */ +#define addrAFoffset_L 0x2B + +/* Convergence Judgement */ +#define INI_MSSET_211 0x00 +#define CHTGOKN_TIME 0x80 +#define CHTGOKN_WAIT 1 +#define CHTGOKN_TIMEOUT 50 +#define CHTGSTOKN_TOMEOUT 15 + +/* StepMove */ +#define STMV_SIZE 0x0180 + +#define STMCHTG_ON 0x08 +#define STMSV_ON 0x04 +#define STMLFF_ON 0x02 +#define STMVEN_ON 0x01 +#define STMCHTG_OFF 0x00 +#define STMSV_OFF 0x00 +#define STMLFF_OFF 0x00 +#define STMVEN_OFF 0x00 + +#define STMCHTG_SET STMCHTG_ON +#define STMSV_SET STMSV_ON +#define STMLFF_SET STMLFF_OFF + +#define CHTGST_ON 0x01 +#define DEFAULT_DADAT 0x8040 + +/* Delay RAM 00h ~ 3Fh */ +#define ADHXI_211H 0x00 +#define ADHXI_211L 0x01 +#define PIDZO_211H 0x02 +#define PIDZO_211L 0x03 +#define RZ_211H 0x04 +#define RZ_211L 0x05 +#define DZ1_211H 0x06 +#define DZ1_211L 0x07 +#define DZ2_211H 0x08 +#define DZ2_211L 0x09 +#define UZ1_211H 0x0A +#define UZ1_211L 0x0B +#define UZ2_211H 0x0C +#define UZ2_211L 0x0D +#define IZ1_211H 0x0E +#define IZ1_211L 0x0F +#define IZ2_211H 0x10 +#define IZ2_211L 0x11 +#define MS1Z01_211H 0x12 +#define MS1Z01_211L 0x13 +#define MS1Z11_211H 0x14 +#define MS1Z11_211L 0x15 +#define MS1Z12_211H 0x16 +#define MS1Z12_211L 0x17 +#define MS1Z22_211H 0x18 +#define MS1Z22_211L 0x19 +#define MS2Z01_211H 0x1A +#define MS2Z01_211L 0x1B +#define MS2Z11_211H 0x1C +#define MS2Z11_211L 0x1D +#define MS2Z12_211H 0x1E +#define MS2Z12_211L 0x1F +#define MS2Z22_211H 0x20 +#define MS2Z22_211L 0x21 +#define MS2Z23_211H 0x22 +#define MS2Z23_211L 0x23 +#define OZ1_211H 0x24 +#define OZ1_211L 0x25 +#define OZ2_211H 0x26 +#define OZ2_211L 0x27 +#define DAHLXO_211H 0x28 +#define DAHLXO_211L 0x29 +#define OZ3_211H 0x2A +#define OZ3_211L 0x2B +#define OZ4_211H 0x2C +#define OZ4_211L 0x2D +#define OZ5_211H 0x2E +#define OZ5_211L 0x2F +#define oe_211H 0x30 +#define oe_211L 0x31 +#define MSR1CMAX_211H 0x32 +#define MSR1CMAX_211L 0x33 +#define MSR1CMIN_211H 0x34 +#define MSR1CMIN_211L 0x35 +#define MSR2CMAX_211H 0x36 +#define MSR2CMAX_211L 0x37 +#define MSR2CMIN_211H 0x38 +#define MSR2CMIN_211L 0x39 +#define OFFSET_211H 0x3A +#define OFFSET_211L 0x3B +#define ADOFFSET_211H 0x3C +#define ADOFFSET_211L 0x3D +#define EZ_211H 0x3E +#define EZ_211L 0x3F + +/* Coefficient RAM 40h ~ 7Fh */ +#define ag_211H 0x40 +#define ag_211L 0x41 +#define da_211H 0x42 +#define da_211L 0x43 +#define db_211H 0x44 +#define db_211L 0x45 +#define dc_211H 0x46 +#define dc_211L 0x47 +#define dg_211H 0x48 +#define dg_211L 0x49 +#define pg_211H 0x4A +#define pg_211L 0x4B +#define gain1_211H 0x4C +#define gain1_211L 0x4D +#define gain2_211H 0x4E +#define gain2_211L 0x4F +#define ua_211H 0x50 +#define ua_211L 0x51 +#define uc_211H 0x52 +#define uc_211L 0x53 +#define ia_211H 0x54 +#define ia_211L 0x55 +#define ib_211H 0x56 +#define ib_211L 0x57 +#define i_c_211H 0x58 +#define i_c_211L 0x59 +#define ms11a_211H 0x5A +#define ms11a_211L 0x5B +#define ms11c_211H 0x5C +#define ms11c_211L 0x5D +#define ms12a_211H 0x5E +#define ms12a_211L 0x5F +#define ms12c_211H 0x60 +#define ms12c_211L 0x61 +#define ms21a_211H 0x62 +#define ms21a_211L 0x63 +#define ms21b_211H 0x64 +#define ms21b_211L 0x65 +#define ms21c_211H 0x66 +#define ms21c_211L 0x67 +#define ms22a_211H 0x68 +#define ms22a_211L 0x69 +#define ms22c_211H 0x6A +#define ms22c_211L 0x6B +#define ms22d_211H 0x6C +#define ms22d_211L 0x6D +#define ms22e_211H 0x6E +#define ms22e_211L 0x6F +#define ms23p_211H 0x70 +#define ms23p_211L 0x71 +#define oa_211H 0x72 +#define oa_211L 0x73 +#define oc_211H 0x74 +#define oc_211L 0x75 +#define PX12_211H 0x76 +#define PX12_211L 0x77 +#define PX3_211H 0x78 +#define PX3_211L 0x79 +#define MS2X_211H 0x7A +#define MS2X_211L 0x7B +#define CHTGX_211H 0x7C +#define CHTGX_211L 0x7D +#define CHTGN_211H 0x7E +#define CHTGN_211L 0x7F + +/* Register 80h ~ 9F */ +#define CLKSEL_211 0x80 +#define ADSET_211 0x81 +#define PWMSEL_211 0x82 +#define SWTCH_211 0x83 +#define STBY_211 0x84 +#define CLR_211 0x85 +#define DSSEL_211 0x86 +#define ENBL_211 0x87 +#define ANA1_211 0x88 +#define STMVEN_211 0x8A +#define STPT_211 0x8B +#define SWFC_211 0x8C +#define SWEN_211 0x8D +#define MSNUM_211 0x8E +#define MSSET_211 0x8F +#define DLYMON_211 0x90 +#define MONA_211 0x91 +#define PWMLIMIT_211 0x92 +#define PINSEL_211 0x93 +#define PWMSEL2_211 0x94 +#define SFTRST_211 0x95 +#define TEST_211 0x96 +#define PWMZONE2_211 0x97 +#define PWMZONE1_211 0x98 +#define PWMZONE0_211 0x99 +#define ZONE3_211 0x9A +#define ZONE2_211 0x9B +#define ZONE1_211 0x9C +#define ZONE0_211 0x9D +#define GCTIM_211 0x9E +#define GCTIM_211NU 0x9F +#define STMINT_211 0xA0 +#define STMVENDH_211 0xA1 +#define STMVENDL_211 0xA2 +#define MSNUMR_211 0xA3 +#define ANA2_211 0xA4 + +/* Device ID of HVCA Drive IC */ +#define HVCA_DEVICE_ID 0xE4 + +/* Device ID of E2P ROM */ +#define EEP_DEVICE_ID 0xA0 +#define EEP_PAGE0 0x00 +#define EEP_PAGE1 0x02 +#define EEP_PAGE2 0x04 +#define EEP_PAGE3 0x06 +/* E2P ROM has 1023 bytes. So there are 4 pages memory */ +/* E2PROM Device ID = 1 0 1 0 0 P0 P1 0 */ +/* +P0 P1 +0 0 : Page 0 +0 1 : Page 1 +1 0 : Page 2 +1 1 : Page 3 +*/ +/* Page 0: address 0x000~0x0FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE0 */ +/* Page 1: address 0x100~0x1FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE1 */ +/* Page 2: address 0x200~0x2FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE2 */ +/* Page 3: address 0x300~0x3FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE3 */ +/* +*/ + +/* E2P data type define of HVCA Initial Value Section */ +#define DIRECT_MODE 0x00 +#define INDIRECT_EEPROM 0x10 +#define INDIRECT_HVCA 0x20 +#define MASK_AND 0x70 +#define MASK_OR 0x80 + +#define DATA_1BYTE 0x01 +#define DATA_2BYTE 0x02 + +#define START_ADDR 0x0030 +#define END_ADDR 0x01BF + +/*Macro define*/ +#if !defined(abs) +#define abs(a) (((a) > 0) ? (a) : -(a)) +#endif + +#endif +/* __SH532U_H__ */ + diff --git a/include/media/soc380.h b/include/media/soc380.h new file mode 100644 index 000000000000..e732cc0fd29e --- /dev/null +++ b/include/media/soc380.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION, All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of NVIDIA CORPORATION nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC380_H__ +#define __SOC380_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define SOC380_IOCTL_SET_MODE _IOW('o', 1, struct soc380_mode) +#define SOC380_IOCTL_GET_STATUS _IOR('o', 2, struct soc380_status) + +struct soc380_mode { + int xres; + int yres; +}; + +struct soc380_status { + int data; + int status; +}; + +#ifdef __KERNEL__ +struct soc380_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __SOC380_H__ */ + diff --git a/include/media/ssl3250a.h b/include/media/ssl3250a.h new file mode 100644 index 000000000000..c4e802fa2efc --- /dev/null +++ b/include/media/ssl3250a.h @@ -0,0 +1,38 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SSL3250A_H__ +#define __SSL3250A_H__ + +#include <media/nvc_torch.h> + +#define SSL3250A_MAX_TORCH_LEVEL 11 +#define SSL3250A_MAX_FLASH_LEVEL 20 + +struct ssl3250a_platform_data { + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state (*pinstate); /* see notes in driver */ + unsigned max_amp_torch; /* maximum torch value allowed */ + unsigned max_amp_flash; /* maximum flash value allowed */ + unsigned gpio_act; /* GPIO connected to the ACT signal */ +}; + +#endif /* __SSL3250A_H__ */ + diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h new file mode 100644 index 000000000000..9dea1485781d --- /dev/null +++ b/include/media/tegra_camera.h @@ -0,0 +1,58 @@ +/* + * include/linux/tegra_camera.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef TEGRA_CAMERA_H +#define TEGRA_CAMERA_H + +/* this is to enable VI pattern generator (Null Sensor) */ +#define TEGRA_CAMERA_ENABLE_PD2VI_CLK 0x1 + +enum { + TEGRA_CAMERA_MODULE_ISP = 0, + TEGRA_CAMERA_MODULE_VI, + TEGRA_CAMERA_MODULE_CSI, + TEGRA_CAMERA_MODULE_EMC, + TEGRA_CAMERA_MODULE_MAX +}; + +enum { + TEGRA_CAMERA_VI_CLK, + TEGRA_CAMERA_VI_SENSOR_CLK, + TEGRA_CAMERA_EMC_CLK +}; + +struct tegra_camera_clk_info { + uint id; + uint clk_id; + unsigned long rate; + uint flag; /* to inform if any special bits need to enabled/disabled */ +}; + +enum StereoCameraMode { + Main = 0x0, /* Sets the default camera to Main */ + StereoCameraMode_Left = 0x01, /* the left camera is on. */ + StereoCameraMode_Right = 0x02, /* the right camera is on. */ + StereoCameraMode_Stereo = 0x03, /* both cameras are on. */ + StereoCameraMode_Force32 = 0x7FFFFFFF +}; + + +#define TEGRA_CAMERA_IOCTL_ENABLE _IOWR('i', 1, uint) +#define TEGRA_CAMERA_IOCTL_DISABLE _IOWR('i', 2, uint) +#define TEGRA_CAMERA_IOCTL_CLK_SET_RATE \ + _IOWR('i', 3, struct tegra_camera_clk_info) +#define TEGRA_CAMERA_IOCTL_RESET _IOWR('i', 4, uint) + +#endif diff --git a/include/media/tegra_dtv.h b/include/media/tegra_dtv.h new file mode 100644 index 000000000000..798e3e3bf9c0 --- /dev/null +++ b/include/media/tegra_dtv.h @@ -0,0 +1,134 @@ +/* + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA_DTV_H__ +#define __TEGRA_DTV_H__ + +#include <linux/ioctl.h> + +#define TEGRA_DTV_MAGIC 'v' + +#define TEGRA_DTV_IOCTL_START _IO(TEGRA_DTV_MAGIC, 0) +#define TEGRA_DTV_IOCTL_STOP _IO(TEGRA_DTV_MAGIC, 1) + +struct tegra_dtv_hw_config { + int clk_edge; /*< clock edge to be used to sample DTV input signals */ + int byte_swz_enabled; /*< byte order during deserialization */ + int bit_swz_enabled; /*< bit order during deserialization */ + + int protocol_sel; /*< VD pin configuration. */ + int clk_mode; /*< input clock characteristics */ + int fec_size; /*< FEC size */ + int body_size; /*< BODY size */ + int body_valid_sel; /*< VALID signal gate */ + int start_sel; /*< START of the package */ + int err_pol; /*< ERROR pin polarity */ + int psync_pol; /*< PSYNC pin polarity */ + int valid_pol; /*< VALID pin polarity */ +}; + +#define TEGRA_DTV_IOCTL_SET_HW_CONFIG _IOW(TEGRA_DTV_MAGIC, 2, \ + const struct tegra_dtv_hw_config *) +#define TEGRA_DTV_IOCTL_GET_HW_CONFIG _IOR(TEGRA_DTV_MAGIC, 3, \ + struct tegra_dtv_hw_config *) + +/** + * clock edge settings for clk_edge + * + * RISE_EDGE: sample input signal at rising edge + * FALL_EDGE: sample input signal at falling edge + */ +enum { + TEGRA_DTV_CLK_RISE_EDGE = 0, + TEGRA_DTV_CLK_FALL_EDGE, +}; + +/** + * swizzle settings for byte_swz and bit_swz + * + * ENABLE: enable swizzle during deserialization + * DISABLE: disable swizzle during deserialization + * + * If swizzling is enabled then deserialized data will be re-ordered to + * fit the required format for tegra. + * + * For example, if raw BGR data is inputed into DTV interface, the data + * could be swizzled into RGB. + * + * For TS/MPEG-2 stream, please disable this feature. + */ +enum { + TEGRA_DTV_SWZ_DISABLE = 0, + TEGRA_DTV_SWZ_ENABLE, +}; + +/* for selecting the pin configuration for VD(valid). + * NONE : ERROR is tied to 0, PSYNC is tied to 0 + * ERROR: ERROR is tied to VD, PSYNC is tied to 0 + * PSYNC: ERROR is tied to 0, PSYNC is tied to VD + */ +enum { + TEGRA_DTV_PROTOCOL_NONE = 0, + TEGRA_DTV_PROTOCOL_ERROR, + TEGRA_DTV_PROTOCOL_PSYNC, +}; + +enum { + TEGRA_DTV_CLK_DISCONTINUOUS = 0, + TEGRA_DTV_CLK_CONTINUOUS, +}; + +enum { + TEGRA_DTV_BODY_VALID_IGNORE = 0, + TEGRA_DTV_BODY_VALID_GATE, +}; + +enum { + TEGRA_DTV_START_RESERVED = 0, /* never use this */ + TEGRA_DTV_START_PSYNC, + TEGRA_DTV_START_VALID, + TEGRA_DTV_START_BOTH, +}; + +enum { + TEGRA_DTV_ERROR_POLARITY_HIGH = 0, + TEGRA_DTV_ERROR_POLARITY_LOW, +}; + +enum { + TEGRA_DTV_PSYNC_POLARITY_HIGH = 0, + TEGRA_DTV_PSYNC_POLARITY_LOW, +}; + +enum { + TEGRA_DTV_VALID_POLARITY_HIGH = 0, + TEGRA_DTV_VALID_POLARITY_LOW, +}; + +#ifdef __KERNEL__ +enum { + TEGRA_DTV_CLK_POSEDGE, + TEGRA_DTV_CLK_NEGEDGE, +}; + +struct tegra_dtv_platform_data { + unsigned int dma_buf_size; + int clk_edge; + bool byte_swz_enabled; + bool bit_swz_enabled; +}; +#endif /* __KERNEL__ */ + +#endif /* __TEGRA_DTV_H__ */ diff --git a/include/media/tegra_v4l2_camera.h b/include/media/tegra_v4l2_camera.h new file mode 100644 index 000000000000..f6390b6e5609 --- /dev/null +++ b/include/media/tegra_v4l2_camera.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA_CAMERA_H_ +#define _TEGRA_CAMERA_H_ + +#include <linux/regulator/consumer.h> +#include <linux/i2c.h> +#include <linux/nvhost.h> + +enum tegra_camera_port { + TEGRA_CAMERA_PORT_CSI_A = 1, + TEGRA_CAMERA_PORT_CSI_B, + TEGRA_CAMERA_PORT_VIP, +}; + +struct tegra_camera_platform_data { + int (*enable_camera)(struct nvhost_device *ndev); + void (*disable_camera)(struct nvhost_device *ndev); + bool flip_h; + bool flip_v; + enum tegra_camera_port port; + int lanes; /* For CSI port only */ + bool continuous_clk; /* For CSI port only */ +}; + +#endif /* _TEGRA_CAMERA_H_ */ diff --git a/include/media/tps61050.h b/include/media/tps61050.h new file mode 100644 index 000000000000..1c289eb3616e --- /dev/null +++ b/include/media/tps61050.h @@ -0,0 +1,36 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __TPS61050_H__ +#define __TPS61050_H__ + +#include <media/nvc_torch.h> + +#define TPS61050_MAX_TORCH_LEVEL 7 +#define TPS61050_MAX_FLASH_LEVEL 8 + +struct tps61050_platform_data { + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state (*pinstate); /* see notes in driver */ + unsigned max_amp_torch; /* see implementation notes in driver */ + unsigned max_amp_flash; /* see implementation notes in driver */ +}; + +#endif /* __TPS61050_H__ */ diff --git a/include/media/videobuf2-dma-nvmap.h b/include/media/videobuf2-dma-nvmap.h new file mode 100644 index 000000000000..39ae3d3a1d5d --- /dev/null +++ b/include/media/videobuf2-dma-nvmap.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _MEDIA_VIDEOBUF2_DMA_NVMAP_H +#define _MEDIA_VIDEOBUF2_DMA_NVMAP_H + +#include <media/videobuf2-core.h> +#include <linux/dma-mapping.h> + +static inline dma_addr_t +vb2_dma_nvmap_plane_paddr(struct vb2_buffer *vb, unsigned int plane_no) +{ + dma_addr_t *paddr = vb2_plane_cookie(vb, plane_no); + + return *paddr; +} + +void *vb2_dma_nvmap_init_ctx(struct device *dev); +void vb2_dma_nvmap_cleanup_ctx(void *alloc_ctx); + +extern const struct vb2_mem_ops vb2_dma_nvmap_memops; + +#endif diff --git a/include/net/addrconf.h b/include/net/addrconf.h index 21f702704f24..01b1a1ad77d2 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -86,6 +86,9 @@ extern int ipv6_dev_get_saddr(struct net *net, const struct in6_addr *daddr, unsigned int srcprefs, struct in6_addr *saddr); +extern int __ipv6_get_lladdr(struct inet6_dev *idev, + struct in6_addr *addr, + unsigned char banned_flags); extern int ipv6_get_lladdr(struct net_device *dev, struct in6_addr *addr, unsigned char banned_flags); diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index 57123eeb21aa..85d86e2a883e 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -1071,6 +1071,9 @@ static inline u16 eir_append_data(u8 *eir, u16 eir_len, u8 type, u8 *data, int hci_register_cb(struct hci_cb *hcb); int hci_unregister_cb(struct hci_cb *hcb); +int hci_register_notifier(struct notifier_block *nb); +int hci_unregister_notifier(struct notifier_block *nb); + struct hci_request { struct hci_dev *hdev; struct sk_buff_head cmd_q; diff --git a/include/net/ndisc.h b/include/net/ndisc.h index 745bf741e029..5043f8b08053 100644 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h @@ -119,7 +119,7 @@ extern struct ndisc_options *ndisc_parse_options(u8 *opt, int opt_len, * if RFC 3831 IPv6-over-Fibre Channel is ever implemented it may * also need a pad of 2. */ -static int ndisc_addr_option_pad(unsigned short type) +static inline int ndisc_addr_option_pad(unsigned short type) { switch (type) { case ARPHRD_INFINIBAND: return 2; diff --git a/include/net/udp.h b/include/net/udp.h index 065f379c6503..ad99eedc6168 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -181,6 +181,7 @@ extern int udp_get_port(struct sock *sk, unsigned short snum, extern void udp_err(struct sk_buff *, u32); extern int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, size_t len); +extern int udp_push_pending_frames(struct sock *sk); extern void udp_flush_pending_frames(struct sock *sk); extern int udp_rcv(struct sk_buff *skb); extern int udp_ioctl(struct sock *sk, int cmd, unsigned long arg); diff --git a/include/sound/max98088.h b/include/sound/max98088.h index c3ba8239182d..9b4fceb360ac 100644 --- a/include/sound/max98088.h +++ b/include/sound/max98088.h @@ -31,6 +31,10 @@ struct max98088_pdata { struct max98088_eq_cfg *eq_cfg; unsigned int eq_cfgcnt; + /* has to be one of 25,50,100 or 200 ms + as per the data sheet */ + unsigned int debounce_time_ms; + /* Receiver output can be configured as power amplifier or LINE out */ /* Set receiver_mode to: * 0 = amplifier output, or diff --git a/include/sound/tegra_wm8903.h b/include/sound/tegra_wm8903.h new file mode 100644 index 000000000000..57b202ee97c3 --- /dev/null +++ b/include/sound/tegra_wm8903.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011 NVIDIA, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOUND_TEGRA_WM38903_H +#define __SOUND_TEGRA_WM38903_H + +struct tegra_wm8903_platform_data { + int gpio_spkr_en; + int gpio_hp_det; + int gpio_hp_mute; + int gpio_int_mic_en; + int gpio_ext_mic_en; +}; + +#endif diff --git a/include/sound/tlv320aic326x.h b/include/sound/tlv320aic326x.h new file mode 100644 index 000000000000..97e5841f9044 --- /dev/null +++ b/include/sound/tlv320aic326x.h @@ -0,0 +1,23 @@ +/* + * Platform data for Texas Instruments TLV320AIC326x codec + * + * Copyright 2010 TI Products + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifndef __LINUX_SND_TLV320AIC326x_H__ +#define __LINUX_SND_TLV320AIC326x_H__ + +/* codec platform data */ +struct aic326x_pdata { + + /* has to be one of 16,32,64,128,256,512 ms + as per the data sheet */ + unsigned int debounce_time_ms; +}; + +#endif diff --git a/include/target/iscsi/iscsi_transport.h b/include/target/iscsi/iscsi_transport.h index 23a87d0cd72c..c5aade523863 100644 --- a/include/target/iscsi/iscsi_transport.h +++ b/include/target/iscsi/iscsi_transport.h @@ -34,8 +34,6 @@ extern void iscsit_put_transport(struct iscsit_transport *); /* * From iscsi_target.c */ -extern int iscsit_add_reject_from_cmd(u8, int, int, unsigned char *, - struct iscsi_cmd *); extern int iscsit_setup_scsi_cmd(struct iscsi_conn *, struct iscsi_cmd *, unsigned char *); extern void iscsit_set_unsoliticed_dataout(struct iscsi_cmd *); @@ -67,6 +65,10 @@ extern int iscsit_logout_post_handler(struct iscsi_cmd *, struct iscsi_conn *); */ extern void iscsit_increment_maxcmdsn(struct iscsi_cmd *, struct iscsi_session *); /* + * From iscsi_target_erl0.c + */ +extern void iscsit_cause_connection_reinstatement(struct iscsi_conn *, int); +/* * From iscsi_target_erl1.c */ extern void iscsit_stop_dataout_timer(struct iscsi_cmd *); @@ -80,4 +82,5 @@ extern int iscsit_tmr_post_handler(struct iscsi_cmd *, struct iscsi_conn *); * From iscsi_target_util.c */ extern struct iscsi_cmd *iscsit_allocate_cmd(struct iscsi_conn *, gfp_t); -extern int iscsit_sequence_cmd(struct iscsi_conn *, struct iscsi_cmd *, __be32); +extern int iscsit_sequence_cmd(struct iscsi_conn *, struct iscsi_cmd *, + unsigned char *, __be32); diff --git a/include/trace/events/display.h b/include/trace/events/display.h new file mode 100644 index 000000000000..c4e6853832f0 --- /dev/null +++ b/include/trace/events/display.h @@ -0,0 +1,260 @@ +/* + * include/trace/events/display.h + * + * Display event logging to ftrace. + * + * Copyright (c) 2012, NVIDIA CORPORATION, All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM display + +#if !defined(_TRACE_DISPLAY_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_DISPLAY_H + +#include "../../../drivers/video/tegra/dc/dc_priv_defs.h" +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(display_basic_template, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc), + TP_STRUCT__entry( + __field( bool, enabled) + __field( u8, dev_id) + __field( int, bw_rate) + __field( int, new_bw_rate) + __field( int, underflows_a) + __field( int, underflows_b) + __field( int, underflows_c) + ), + TP_fast_assign( + __entry->enabled = dc->enabled; + __entry->dev_id = dc->ndev->dev.id; + __entry->bw_rate = dc->emc_clk_rate; + __entry->new_bw_rate = dc->new_emc_clk_rate; + __entry->underflows_a = dc->stats.underflows_a; + __entry->underflows_b = dc->stats.underflows_b; + __entry->underflows_c = dc->stats.underflows_c; + ), + TP_printk("dc%u enabled=%d bw_rate=%d new_bw_rate=%d underflows=%d/%d/%d", + __entry->dev_id, __entry->enabled, + __entry->bw_rate, __entry->new_bw_rate, + __entry->underflows_a, __entry->underflows_b, + __entry->underflows_c) +); + +DEFINE_EVENT(display_basic_template, display_enable, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, display_disable, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, display_suspend, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, display_resume, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, display_reset, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, update_windows, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, sync_windows, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, clear_bandwidth, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, program_bandwidth, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, set_dynamic_emc, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +DEFINE_EVENT(display_basic_template, underflow, + TP_PROTO(struct tegra_dc *dc), + TP_ARGS(dc) +); + +TRACE_EVENT(display_syncpt_flush, + TP_PROTO(struct tegra_dc *dc, u32 id, u32 min, u32 max), + TP_ARGS(dc, id, min, max), + TP_STRUCT__entry( + __field( bool, enabled) + __field( u8, dev_id) + __field( u32, syncpt_id) + __field( u32, syncpt_min) + __field( u32, syncpt_max) + ), + TP_fast_assign( + __entry->enabled = dc->enabled; + __entry->dev_id = dc->ndev->dev.id; + __entry->syncpt_id = id; + __entry->syncpt_min = min; + __entry->syncpt_max = max; + ), + TP_printk("dc%u enabled=%d syncpt: id=%x min=%x max=%x", + __entry->dev_id, __entry->enabled, + __entry->syncpt_id, __entry->syncpt_min, __entry->syncpt_max) +); + +DECLARE_EVENT_CLASS(display_io_template, + TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg), + TP_ARGS(dc, val, reg), + TP_STRUCT__entry( + __field( bool, enabled) + __field( u8, dev_id) + __field( const void *, reg) + __field( u32, val) + ), + TP_fast_assign( + __entry->enabled = dc->enabled; + __entry->dev_id = dc->ndev->dev.id; + __entry->reg = reg; + __entry->val = val; + ), + TP_printk("dc%u enabled=%d reg=%p val=0x%08x", + __entry->dev_id, __entry->enabled, + __entry->reg, __entry->val) +); + +DEFINE_EVENT(display_io_template, display_writel, + TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg), + TP_ARGS(dc, val, reg) +); + +DEFINE_EVENT(display_io_template, display_readl, + TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg), + TP_ARGS(dc, val, reg) +); + +TRACE_EVENT(display_mode, + TP_PROTO(struct tegra_dc *dc, struct tegra_dc_mode *mode), + TP_ARGS(dc, mode), + TP_STRUCT__entry( + __field( bool, enabled) + __field( u8, dev_id) + __field( unsigned long, pclk) + __field( unsigned short, h_active) + __field( unsigned short, v_active) + __field( unsigned short, h_front_porch) + __field( unsigned short, v_front_porch) + __field( unsigned short, h_back_porch) + __field( unsigned short, v_back_porch) + __field( unsigned short, h_ref_to_sync) + __field( unsigned short, v_ref_to_sync) + __field( unsigned short, h_sync_width) + __field( unsigned short, v_sync_width) + __field( bool, stereo_mode) + ), + TP_fast_assign( + __entry->enabled = dc->enabled; + __entry->dev_id = dc->ndev->dev.id; + __entry->pclk = mode->pclk; + __entry->stereo_mode = mode->stereo_mode; + __entry->h_active = mode->h_active; + __entry->v_active = mode->v_active; + __entry->h_front_porch = mode->h_front_porch; + __entry->v_front_porch = mode->v_front_porch; + __entry->h_back_porch = mode->h_back_porch; + __entry->v_back_porch = mode->v_back_porch; + __entry->h_sync_width = mode->h_sync_width; + __entry->v_sync_width = mode->v_sync_width; + __entry->h_ref_to_sync = mode->h_ref_to_sync; + __entry->v_ref_to_sync = mode->v_ref_to_sync; + ), + TP_printk("dc%u enabled=%d " + "ref_to_sync: H=%d V=%d " + "sync_width: H=%d V=%d " + "back_porch: H=%d V=%d " + "active: H=%d V=%d " + "front_porch: H=%d V=%d " + "pclk=%ld stereo mode=%d\n", + __entry->dev_id, __entry->enabled, + __entry->h_ref_to_sync, __entry->v_ref_to_sync, + __entry->h_sync_width, __entry->v_sync_width, + __entry->h_back_porch, __entry->v_back_porch, + __entry->h_active, __entry->v_active, + __entry->h_front_porch, __entry->v_front_porch, + __entry->pclk, __entry->stereo_mode + ) +); + +TRACE_EVENT(window_update, + TP_PROTO(struct tegra_dc *dc, struct tegra_dc_win *win), + TP_ARGS(dc, win), + TP_STRUCT__entry( + __field( bool, enabled) + __field( u8, dev_id) + __field( u32, win_fmt) + __field( unsigned short, win_x) + __field( unsigned short, win_y) + __field( unsigned short, win_w) + __field( unsigned short, win_h) + __field( unsigned short, win_out_x) + __field( unsigned short, win_out_y) + __field( unsigned short, win_out_w) + __field( unsigned short, win_out_h) + ), + TP_fast_assign( + __entry->enabled = dc->enabled; + __entry->dev_id = dc->ndev->dev.id; + __entry->win_fmt = win->fmt; + __entry->win_x = dfixed_trunc(win->x); + __entry->win_y = dfixed_trunc(win->y); + __entry->win_w = dfixed_trunc(win->w); + __entry->win_h = dfixed_trunc(win->h); + __entry->win_out_x = win->out_x; + __entry->win_out_y = win->out_y; + __entry->win_out_w = win->out_w; + __entry->win_out_h = win->out_h; + ), + TP_printk("dc%u enabled=%d fmt=%#x in=[x:%u y:%u w:%u h:%u] " + "out=[x:%u y:%u w:%u h:%u] ", + __entry->dev_id, __entry->enabled, __entry->win_fmt, + __entry->win_x, __entry->win_y, + __entry->win_w, __entry->win_h, + __entry->win_out_x, __entry->win_out_y, + __entry->win_out_w, __entry->win_out_h + ) +); +#endif /* _TRACE_DISPLAY_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/trace/events/nvhost.h b/include/trace/events/nvhost.h new file mode 100644 index 000000000000..a932d3a569e9 --- /dev/null +++ b/include/trace/events/nvhost.h @@ -0,0 +1,711 @@ +/* + * include/trace/events/nvhost.h + * + * Nvhost event logging to ftrace. + * + * Copyright (c) 2010-2013, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM nvhost + +#if !defined(_TRACE_NVHOST_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_NVHOST_H + +#include <linux/ktime.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(nvhost, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry(__field(const char *, name)), + TP_fast_assign(__entry->name = name;), + TP_printk("name=%s", __entry->name) +); + +DEFINE_EVENT(nvhost, nvhost_channel_open, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +DEFINE_EVENT(nvhost, nvhost_channel_release, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +DEFINE_EVENT(nvhost, nvhost_ioctl_channel_flush, + TP_PROTO(const char *name), + TP_ARGS(name) +); + +TRACE_EVENT(nvhost_channel_write_submit, + TP_PROTO(const char *name, ssize_t count, u32 cmdbufs, u32 relocs, + u32 syncpt_id, u32 syncpt_incrs), + + TP_ARGS(name, count, cmdbufs, relocs, syncpt_id, syncpt_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(ssize_t, count) + __field(u32, cmdbufs) + __field(u32, relocs) + __field(u32, syncpt_id) + __field(u32, syncpt_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->count = count; + __entry->cmdbufs = cmdbufs; + __entry->relocs = relocs; + __entry->syncpt_id = syncpt_id; + __entry->syncpt_incrs = syncpt_incrs; + ), + + TP_printk("name=%s, count=%d, cmdbufs=%u, relocs=%u, syncpt_id=%u, syncpt_incrs=%u", + __entry->name, __entry->count, __entry->cmdbufs, __entry->relocs, + __entry->syncpt_id, __entry->syncpt_incrs) +); + +TRACE_EVENT(nvhost_channel_submit, + TP_PROTO(const char *name, u32 cmdbufs, u32 relocs, u32 waitchks, + u32 syncpt_id, u32 syncpt_incrs), + + TP_ARGS(name, cmdbufs, relocs, waitchks, syncpt_id, syncpt_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, cmdbufs) + __field(u32, relocs) + __field(u32, waitchks) + __field(u32, syncpt_id) + __field(u32, syncpt_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->cmdbufs = cmdbufs; + __entry->relocs = relocs; + __entry->waitchks = waitchks; + __entry->syncpt_id = syncpt_id; + __entry->syncpt_incrs = syncpt_incrs; + ), + + TP_printk("name=%s, cmdbufs=%u, relocs=%u, waitchks=%d," + "syncpt_id=%u, syncpt_incrs=%u", + __entry->name, __entry->cmdbufs, __entry->relocs, __entry->waitchks, + __entry->syncpt_id, __entry->syncpt_incrs) +); + +TRACE_EVENT(nvhost_ioctl_channel_submit, + TP_PROTO(const char *name, u32 version, u32 cmdbufs, u32 relocs, + u32 waitchks, u32 syncpt_id, u32 syncpt_incrs), + + TP_ARGS(name, version, cmdbufs, relocs, waitchks, + syncpt_id, syncpt_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, version) + __field(u32, cmdbufs) + __field(u32, relocs) + __field(u32, waitchks) + __field(u32, syncpt_id) + __field(u32, syncpt_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->version = version; + __entry->cmdbufs = cmdbufs; + __entry->relocs = relocs; + __entry->waitchks = waitchks; + __entry->syncpt_id = syncpt_id; + __entry->syncpt_incrs = syncpt_incrs; + ), + + TP_printk("name=%s, version=%u, cmdbufs=%u, relocs=%u, waitchks=%u, syncpt_id=%u, syncpt_incrs=%u", + __entry->name, __entry->version, __entry->cmdbufs, __entry->relocs, + __entry->waitchks, __entry->syncpt_id, __entry->syncpt_incrs) +); + +TRACE_EVENT(nvhost_channel_write_cmdbuf, + TP_PROTO(const char *name, u32 mem_id, + u32 words, u32 offset), + + TP_ARGS(name, mem_id, words, offset), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, mem_id) + __field(u32, words) + __field(u32, offset) + ), + + TP_fast_assign( + __entry->name = name; + __entry->mem_id = mem_id; + __entry->words = words; + __entry->offset = offset; + ), + + TP_printk("name=%s, mem_id=%08x, words=%u, offset=%d", + __entry->name, __entry->mem_id, + __entry->words, __entry->offset) +); + +TRACE_EVENT(nvhost_cdma_end, + TP_PROTO(const char *name, int prio, + int hi_count, int med_count, int low_count), + + TP_ARGS(name, prio, hi_count, med_count, low_count), + + TP_STRUCT__entry( + __field(const char *, name) + __field(int, prio) + __field(int, hi_count) + __field(int, med_count) + __field(int, low_count) + ), + + TP_fast_assign( + __entry->name = name; + __entry->prio = prio; + __entry->hi_count = hi_count; + __entry->med_count = med_count; + __entry->low_count = low_count; + ), + + TP_printk("name=%s, prio=%d, hi=%d, med=%d, low=%d", + __entry->name, __entry->prio, + __entry->hi_count, __entry->med_count, __entry->low_count) +); + +TRACE_EVENT(nvhost_cdma_flush, + TP_PROTO(const char *name, int timeout), + + TP_ARGS(name, timeout), + + TP_STRUCT__entry( + __field(const char *, name) + __field(int, timeout) + ), + + TP_fast_assign( + __entry->name = name; + __entry->timeout = timeout; + ), + + TP_printk("name=%s, timeout=%d", + __entry->name, __entry->timeout) +); + +TRACE_EVENT(nvhost_cdma_push, + TP_PROTO(const char *name, u32 op1, u32 op2), + + TP_ARGS(name, op1, op2), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, op1) + __field(u32, op2) + ), + + TP_fast_assign( + __entry->name = name; + __entry->op1 = op1; + __entry->op2 = op2; + ), + + TP_printk("name=%s, op1=%08x, op2=%08x", + __entry->name, __entry->op1, __entry->op2) +); + +TRACE_EVENT(nvhost_cdma_push_gather, + TP_PROTO(const char *name, u32 mem_id, + u32 words, u32 offset, void *cmdbuf), + + TP_ARGS(name, mem_id, words, offset, cmdbuf), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, mem_id) + __field(u32, words) + __field(u32, offset) + __field(bool, cmdbuf) + __dynamic_array(u32, cmdbuf, words) + ), + + TP_fast_assign( + if (cmdbuf) { + memcpy(__get_dynamic_array(cmdbuf), cmdbuf+offset, + words * sizeof(u32)); + } + __entry->cmdbuf = cmdbuf; + __entry->name = name; + __entry->mem_id = mem_id; + __entry->words = words; + __entry->offset = offset; + ), + + TP_printk("name=%s, mem_id=%08x, words=%u, offset=%d, contents=[%s]", + __entry->name, __entry->mem_id, + __entry->words, __entry->offset, + __print_hex(__get_dynamic_array(cmdbuf), + __entry->cmdbuf ? __entry->words * 4 : 0)) +); + +TRACE_EVENT(nvhost_channel_write_reloc, + TP_PROTO(const char *name, u32 cmdbuf_mem, u32 cmdbuf_offset, + u32 target, u32 target_offset), + + TP_ARGS(name, cmdbuf_mem, cmdbuf_offset, target, target_offset), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, cmdbuf_mem) + __field(u32, cmdbuf_offset) + __field(u32, target) + __field(u32, target_offset) + ), + + TP_fast_assign( + __entry->name = name; + __entry->cmdbuf_mem = cmdbuf_mem; + __entry->cmdbuf_offset = cmdbuf_offset; + __entry->target = target; + __entry->target_offset = target_offset; + ), + + TP_printk("name=%s, cmdbuf_mem=%08x, cmdbuf_offset=%04x, target=%08x, target_offset=%04x", + __entry->name, __entry->cmdbuf_mem, __entry->cmdbuf_offset, + __entry->target, __entry->target_offset) +); + +TRACE_EVENT(nvhost_channel_write_waitchks, + TP_PROTO(const char *name, u32 waitchks), + + TP_ARGS(name, waitchks), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, waitchks) + ), + + TP_fast_assign( + __entry->name = name; + __entry->waitchks = waitchks; + ), + + TP_printk("name=%s, waitchks=%u", + __entry->name, __entry->waitchks) +); + +TRACE_EVENT(nvhost_channel_context_save, + TP_PROTO(const char *name, void *ctx), + + TP_ARGS(name, ctx), + + TP_STRUCT__entry( + __field(const char *, name) + __field(void*, ctx) + ), + + TP_fast_assign( + __entry->name = name; + __entry->ctx = ctx; + ), + + TP_printk("name=%s, ctx=%p", + __entry->name, __entry->ctx) +); + +TRACE_EVENT(nvhost_channel_context_restore, + TP_PROTO(const char *name, void *ctx), + + TP_ARGS(name, ctx), + + TP_STRUCT__entry( + __field(const char *, name) + __field(void*, ctx) + ), + + TP_fast_assign( + __entry->name = name; + __entry->ctx = ctx; + ), + + TP_printk("name=%s, ctx=%p", + __entry->name, __entry->ctx) +); + +TRACE_EVENT(nvhost_ioctl_channel_set_ctxswitch, + TP_PROTO(const char *name, void *ctx, + u32 save_mem, u32 save_offset, u32 save_words, + u32 restore_mem, u32 restore_offset, u32 restore_words, + u32 syncpt_id, u32 waitbase, u32 save_incrs, u32 restore_incrs), + + TP_ARGS(name, ctx, + save_mem, save_offset, save_words, + restore_mem, restore_offset, restore_words, + syncpt_id, waitbase, save_incrs, restore_incrs), + + TP_STRUCT__entry( + __field(const char *, name) + __field(void *, ctx) + __field(u32, save_mem) + __field(u32, save_offset) + __field(u32, save_words) + __field(u32, restore_mem) + __field(u32, restore_offset) + __field(u32, restore_words) + __field(u32, syncpt_id) + __field(u32, waitbase) + __field(u32, save_incrs) + __field(u32, restore_incrs) + ), + + TP_fast_assign( + __entry->name = name; + __entry->ctx = ctx; + __entry->save_mem = save_mem; + __entry->save_offset = save_offset; + __entry->save_words = save_words; + __entry->restore_mem = restore_mem; + __entry->restore_offset = restore_offset; + __entry->restore_words = restore_words; + __entry->syncpt_id = syncpt_id; + __entry->waitbase = waitbase; + __entry->save_incrs = save_incrs; + __entry->restore_incrs = restore_incrs; + ), + + TP_printk("name=%s, ctx=%p, save_mem=%08x, save_offset=%d, save_words=%d, restore_mem=%08x, restore_offset=%d, restore_words=%d, syncpt_id=%d, waitbase=%d, save_incrs=%d, restore_incrs=%d", + __entry->name, __entry->ctx, + __entry->save_mem, __entry->save_offset, __entry->save_words, + __entry->restore_mem, __entry->restore_offset, __entry->restore_words, + __entry->syncpt_id, __entry->waitbase, + __entry->save_incrs, __entry->restore_incrs) +); +TRACE_EVENT(nvhost_ctrlopen, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name + ), + TP_printk("name=%s", __entry->name) +); + +TRACE_EVENT(nvhost_ctrlrelease, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name + ), + TP_printk("name=%s", __entry->name) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_module_mutex, + TP_PROTO(u32 lock, u32 id), + + TP_ARGS(lock, id), + + TP_STRUCT__entry( + __field(u32, lock); + __field(u32, id); + ), + + TP_fast_assign( + __entry->lock = lock; + __entry->id = id; + ), + + TP_printk("lock=%u, id=%d", + __entry->lock, __entry->id) + ); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_incr, + TP_PROTO(u32 id), + + TP_ARGS(id), + + TP_STRUCT__entry( + __field(u32, id); + ), + + TP_fast_assign( + __entry->id = id; + ), + + TP_printk("id=%d", __entry->id) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_read, + TP_PROTO(u32 id, u32 value), + + TP_ARGS(id, value), + + TP_STRUCT__entry( + __field(u32, id); + __field(u32, value); + ), + + TP_fast_assign( + __entry->id = id; + __entry->value = value; + ), + + TP_printk("id=%d, value=%d", __entry->id, __entry->value) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_syncpt_wait, + TP_PROTO(u32 id, u32 threshold, s32 timeout, u32 value, int err), + + TP_ARGS(id, threshold, timeout, value, err), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, threshold) + __field(s32, timeout) + __field(u32, value) + __field(int, err) + ), + + TP_fast_assign( + __entry->id = id; + __entry->threshold = threshold; + __entry->timeout = timeout; + __entry->value = value; + __entry->err = err; + ), + + TP_printk("id=%u, threshold=%u, timeout=%d, value=%u, err=%d", + __entry->id, __entry->threshold, __entry->timeout, + __entry->value, __entry->err) +); + +TRACE_EVENT(nvhost_ioctl_channel_module_regrdwr, + TP_PROTO(u32 id, u32 num_offsets, bool write), + + TP_ARGS(id, num_offsets, write), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, num_offsets) + __field(bool, write) + ), + + TP_fast_assign( + __entry->id = id; + __entry->num_offsets = num_offsets; + __entry->write = write; + ), + + TP_printk("id=%u, num_offsets=%u, write=%d", + __entry->id, __entry->num_offsets, __entry->write) +); + +TRACE_EVENT(nvhost_ioctl_ctrl_module_regrdwr, + TP_PROTO(u32 id, u32 num_offsets, bool write), + + TP_ARGS(id, num_offsets, write), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, num_offsets) + __field(bool, write) + ), + + TP_fast_assign( + __entry->id = id; + __entry->num_offsets = num_offsets; + __entry->write = write; + ), + + TP_printk("id=%u, num_offsets=%u, write=%d", + __entry->id, __entry->num_offsets, __entry->write) +); + +TRACE_EVENT(nvhost_channel_submitted, + TP_PROTO(const char *name, u32 syncpt_base, u32 syncpt_max), + + TP_ARGS(name, syncpt_base, syncpt_max), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, syncpt_base) + __field(u32, syncpt_max) + ), + + TP_fast_assign( + __entry->name = name; + __entry->syncpt_base = syncpt_base; + __entry->syncpt_max = syncpt_max; + ), + + TP_printk("name=%s, syncpt_base=%d, syncpt_max=%d", + __entry->name, __entry->syncpt_base, __entry->syncpt_max) +); + +TRACE_EVENT(nvhost_channel_submit_complete, + TP_PROTO(const char *name, int count, u32 thresh, + int hi_count, int med_count, int low_count), + + TP_ARGS(name, count, thresh, hi_count, med_count, low_count), + + TP_STRUCT__entry( + __field(const char *, name) + __field(int, count) + __field(u32, thresh) + __field(int, hi_count) + __field(int, med_count) + __field(int, low_count) + ), + + TP_fast_assign( + __entry->name = name; + __entry->count = count; + __entry->thresh = thresh; + __entry->hi_count = hi_count; + __entry->med_count = med_count; + __entry->low_count = low_count; + ), + + TP_printk("name=%s, count=%d, thresh=%d, hi=%d, med=%d, low=%d", + __entry->name, __entry->count, __entry->thresh, + __entry->hi_count, __entry->med_count, __entry->low_count) +); + +TRACE_EVENT(nvhost_wait_cdma, + TP_PROTO(const char *name, u32 eventid), + + TP_ARGS(name, eventid), + + TP_STRUCT__entry( + __field(const char *, name) + __field(u32, eventid) + ), + + TP_fast_assign( + __entry->name = name; + __entry->eventid = eventid; + ), + + TP_printk("name=%s, event=%d", __entry->name, __entry->eventid) +); + +TRACE_EVENT(nvhost_syncpt_update_min, + TP_PROTO(u32 id, u32 val), + + TP_ARGS(id, val), + + TP_STRUCT__entry( + __field(u32, id) + __field(u32, val) + ), + + TP_fast_assign( + __entry->id = id; + __entry->val = val; + ), + + TP_printk("id=%d, val=%d", __entry->id, __entry->val) +); + +TRACE_EVENT(nvhost_syncpt_wait_check, + TP_PROTO(u32 mem_id, u32 offset, u32 syncpt_id, u32 thresh, u32 min), + + TP_ARGS(mem_id, offset, syncpt_id, thresh, min), + + TP_STRUCT__entry( + __field(u32, mem_id) + __field(u32, offset) + __field(u32, syncpt_id) + __field(u32, thresh) + __field(u32, min) + ), + + TP_fast_assign( + __entry->mem_id = mem_id; + __entry->offset = offset; + __entry->syncpt_id = syncpt_id; + __entry->thresh = thresh; + __entry->min = min; + ), + + TP_printk("mem_id=%08x, offset=%05x, id=%d, thresh=%d, current=%d", + __entry->mem_id, __entry->offset, + __entry->syncpt_id, __entry->thresh, + __entry->min) +); + +TRACE_EVENT(nvhost_module_set_devfreq_rate, + TP_PROTO(const char *devname, const char *clockname, + unsigned long rate), + + TP_ARGS(devname, clockname, rate), + + TP_STRUCT__entry( + __field(const char *, devname) + __field(const char *, clockname) + __field(unsigned long, rate) + ), + + TP_fast_assign( + __entry->devname = devname; + __entry->clockname = clockname; + __entry->rate = rate; + ), + + TP_printk("dev=%s, clock=%s, rate=%ld", + __entry->devname, __entry->clockname, + __entry->rate) +); + +TRACE_EVENT(nvhost_module_update_rate, + TP_PROTO(const char *devname, const char *clockname, + unsigned long rate), + + TP_ARGS(devname, clockname, rate), + + TP_STRUCT__entry( + __field(const char *, devname) + __field(const char *, clockname) + __field(unsigned long, rate) + ), + + TP_fast_assign( + __entry->devname = devname; + __entry->clockname = clockname; + __entry->rate = rate; + ), + + TP_printk("dev=%s, clock=%s, rate=%ld", + __entry->devname, __entry->clockname, + __entry->rate) +); + +#endif /* _TRACE_NVHOST_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/trace/events/nvhost_podgov.h b/include/trace/events/nvhost_podgov.h new file mode 100644 index 000000000000..5eb12a84dbfd --- /dev/null +++ b/include/trace/events/nvhost_podgov.h @@ -0,0 +1,195 @@ +/* + * include/trace/events/nvhost_podgov.h + * + * Nvhost event logging to ftrace. + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM nvhost_podgov + +#if !defined(_TRACE_NVHOST_PODGOV_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_NVHOST_PODGOV_H + +#include <linux/ktime.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(podgov_update_freq, + TP_PROTO(unsigned long old_freq, unsigned long new_freq), + + TP_ARGS(old_freq, new_freq), + + TP_STRUCT__entry( + __field(unsigned long, old_freq) + __field(unsigned long, new_freq) + ), + + TP_fast_assign( + __entry->old_freq = old_freq; + __entry->new_freq = new_freq; + ), + + TP_printk("old_freq=%lu, new_freq=%lu", + __entry->old_freq, __entry->new_freq) +); + +DEFINE_EVENT(podgov_update_freq, podgov_do_scale, + TP_PROTO(unsigned long old_freq, unsigned long new_freq), + TP_ARGS(old_freq, new_freq) +); + +DEFINE_EVENT(podgov_update_freq, podgov_scaling_state_check, + TP_PROTO(unsigned long old_freq, unsigned long new_freq), + TP_ARGS(old_freq, new_freq) +); + +DEFINE_EVENT(podgov_update_freq, podgov_estimate_freq, + TP_PROTO(unsigned long old_freq, unsigned long new_freq), + TP_ARGS(old_freq, new_freq) +); + +DEFINE_EVENT(podgov_update_freq, podgov_clocks_handler, + TP_PROTO(unsigned long old_freq, unsigned long new_freq), + TP_ARGS(old_freq, new_freq) +); + +TRACE_EVENT(podgov_enabled, + TP_PROTO(int enable), + + TP_ARGS(enable), + + TP_STRUCT__entry( + __field(int, enable) + ), + + TP_fast_assign( + __entry->enable = enable; + ), + + TP_printk("scaling_enabled=%d", __entry->enable) +); + +TRACE_EVENT(podgov_busy, + TP_PROTO(unsigned long busyness), + + TP_ARGS(busyness), + + TP_STRUCT__entry( + __field(unsigned long, busyness) + ), + + TP_fast_assign( + __entry->busyness = busyness; + ), + + TP_printk("busyness=%lu", __entry->busyness) +); + +TRACE_EVENT(podgov_hint, + TP_PROTO(long idle_estimate, int hint), + + TP_ARGS(idle_estimate, hint), + + TP_STRUCT__entry( + __field(long, idle_estimate) + __field(int, hint) + ), + + TP_fast_assign( + __entry->idle_estimate = idle_estimate; + __entry->hint = hint; + ), + + TP_printk("podgov: idle %ld, hint %d", __entry->idle_estimate, + __entry->hint) +); + +TRACE_EVENT(podgov_idle, + TP_PROTO(unsigned long idleness), + + TP_ARGS(idleness), + + TP_STRUCT__entry( + __field(unsigned long, idleness) + ), + + TP_fast_assign( + __entry->idleness = idleness; + ), + + TP_printk("idleness=%lu", __entry->idleness) +); + +TRACE_EVENT(podgov_print_target, + TP_PROTO(long busy, int avg_busy, long curr, long target, int hint, + int avg_hint), + + TP_ARGS(busy, avg_busy, curr, target, hint, avg_hint), + + TP_STRUCT__entry( + __field(long, busy) + __field(int, avg_busy) + __field(long, curr) + __field(long, target) + __field(int, hint) + __field(int, avg_hint) + ), + + TP_fast_assign( + __entry->busy = busy; + __entry->avg_busy = avg_busy; + __entry->curr = curr; + __entry->target = target; + __entry->hint = hint; + __entry->avg_hint = avg_hint; + ), + + TP_printk("podgov: busy %ld <%d>, curr %ld, t %ld, hint %d <%d>\n", + __entry->busy, __entry->avg_busy, __entry->curr, + __entry->target, __entry->hint, __entry->avg_hint) +); + +TRACE_EVENT(podgov_stats, + TP_PROTO(int fast_up_count, int slow_down_count, unsigned int idle_min, + unsigned int idle_max), + + TP_ARGS(fast_up_count, slow_down_count, idle_min, idle_max), + + TP_STRUCT__entry( + __field(int, fast_up_count) + __field(int, slow_down_count) + __field(unsigned int, idle_min) + __field(unsigned int, idle_max) + ), + + TP_fast_assign( + __entry->fast_up_count = fast_up_count; + __entry->slow_down_count = slow_down_count; + __entry->idle_min = idle_min; + __entry->idle_max = idle_max; + ), + + TP_printk("podgov stats: + %d - %d min %u max %u\n", + __entry->fast_up_count, __entry->slow_down_count, + __entry->idle_min, __entry->idle_max) +); + +#endif /* _TRACE_NVHOST_PODGOV_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/trace/events/nvmap.h b/include/trace/events/nvmap.h new file mode 100644 index 000000000000..3ee2f5dcdcdd --- /dev/null +++ b/include/trace/events/nvmap.h @@ -0,0 +1,353 @@ +/* + * include/trace/events/nvmap.h + * + * NvMap event logging to ftrace. + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM nvmap + +#if !defined(_TRACE_NVMAP_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_NVMAP_H + +#include "../../../drivers/video/tegra/nvmap/nvmap.h" +#include <linux/nvmap.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(nvmap, + TP_PROTO(struct nvmap_client *client), + TP_ARGS(client), + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + ), + TP_fast_assign( + __entry->client = client; + ), + TP_printk("client=%p, name=%s", + __entry->client, __entry->client->name) +); + +DEFINE_EVENT(nvmap, nvmap_open, + TP_PROTO(struct nvmap_client *client), + TP_ARGS(client) +); + +DEFINE_EVENT(nvmap, nvmap_release, + TP_PROTO(struct nvmap_client *client), + TP_ARGS(client) +); + +TRACE_EVENT(nvmap_create_handle, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 size, + struct nvmap_handle_ref *ref + ), + + TP_ARGS(client, h, size, ref), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(struct nvmap_handle *, h) + __field(u32, size) + __field(struct nvmap_handle_ref *, ref) + ), + + TP_fast_assign( + __entry->client = client; + __entry->h = h; + __entry->size = size; + __entry->ref = ref; + ), + + TP_printk("client=%p, name=%s, handle=%p, size=%d, ref=%p", + __entry->client, __entry->client->name, + __entry->h, __entry->size, __entry->ref) +); + +TRACE_EVENT(nvmap_alloc_handle_id, + TP_PROTO(struct nvmap_client *client, + unsigned long handle_id, + u32 heap_mask, + u32 align, + u32 flags + ), + + TP_ARGS(client, handle_id, heap_mask, align, flags), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(unsigned long, handle_id) + __field(u32, heap_mask) + __field(u32, align) + __field(u32, flags) + ), + + TP_fast_assign( + __entry->client = client; + __entry->handle_id = handle_id; + __entry->heap_mask = heap_mask; + __entry->align = align; + __entry->flags = flags; + ), + + TP_printk("client=%p, id=0x%lx, heap_mask=0x%x, align=%d, flags=0x%x", + __entry->client, __entry->handle_id, __entry->heap_mask, + __entry->align, __entry->flags) +); + +TRACE_EVENT(nvmap_free_handle_id, + TP_PROTO(struct nvmap_client *client, + unsigned long handle_id + ), + + TP_ARGS(client, handle_id), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(unsigned long, handle_id) + ), + + TP_fast_assign( + __entry->client = client; + __entry->handle_id = handle_id; + ), + + TP_printk("client=%p, id=0x%lx", + __entry->client, __entry->handle_id) +); + +TRACE_EVENT(nvmap_duplicate_handle_id, + TP_PROTO(struct nvmap_client *client, + unsigned long handle_id, + struct nvmap_handle_ref *ref + ), + + TP_ARGS(client, handle_id, ref), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(unsigned long, handle_id) + __field(struct nvmap_handle_ref *, ref) + ), + + TP_fast_assign( + __entry->client = client; + __entry->handle_id = handle_id; + __entry->ref = ref; + ), + + TP_printk("client=%p, id=0x%lx, ref=%p", + __entry->client, __entry->handle_id, __entry->ref) +); + +TRACE_EVENT(cache_maint, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + unsigned long start, + unsigned long end, + u32 op + ), + + TP_ARGS(client, h, start, end, op), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(struct nvmap_handle *, h) + __field(unsigned long, start) + __field(unsigned long, end) + __field(u32, op) + ), + + TP_fast_assign( + __entry->client = client; + __entry->h = h; + __entry->start = start; + __entry->end = end; + __entry->op = op; + ), + + TP_printk("client=%p, h=%p, start=0x%lx, end=0x%lx, op=%d", + __entry->client, __entry->h, __entry->start, + __entry->end, __entry->op) +); + +TRACE_EVENT(nvmap_map_into_caller_ptr, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 offset, + u32 length, + u32 flags + ), + + TP_ARGS(client, h, offset, length, flags), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(struct nvmap_handle *, h) + __field(u32, offset) + __field(u32, length) + __field(u32, flags) + ), + + TP_fast_assign( + __entry->client = client; + __entry->h = h; + __entry->offset = offset; + __entry->length = length; + __entry->flags = flags; + ), + + TP_printk("client=%p, h=%p, offset=%d, length=%d, flags=0x%x", + __entry->client, __entry->h, __entry->offset, + __entry->length, __entry->flags) +); + +TRACE_EVENT(nvmap_ioctl_rw_handle, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 is_read, + u32 offset, + unsigned long addr, + u32 mem_stride, + u32 user_stride, + u32 elem_size, + u32 count + ), + + TP_ARGS(client, h, is_read, offset, addr, mem_stride, + user_stride, elem_size, count), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(struct nvmap_handle *, h) + __field(u32, is_read) + __field(u32, offset) + __field(unsigned long, addr) + __field(u32, mem_stride) + __field(u32, user_stride) + __field(u32, elem_size) + __field(u32, count) + ), + + TP_fast_assign( + __entry->client = client; + __entry->h = h; + __entry->is_read = is_read; + __entry->offset = offset; + __entry->addr = addr; + __entry->mem_stride = mem_stride; + __entry->user_stride = user_stride; + __entry->elem_size = elem_size; + __entry->count = count; + ), + + TP_printk("client=%p, h=%p, is_read=%d, offset=%d, addr=0x%lx," + "mem_stride=%d, user_stride=%d, elem_size=%d, count=%d", + __entry->client, __entry->h, __entry->is_read, __entry->offset, + __entry->addr, __entry->mem_stride, __entry->user_stride, + __entry->elem_size, __entry->count) +); + +TRACE_EVENT(nvmap_ioctl_pinop, + TP_PROTO(struct nvmap_client *client, + u32 is_pin, + u32 count, + unsigned long *ids + ), + + TP_ARGS(client, is_pin, count, ids), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(u32, is_pin) + __field(u32, count) + __field(unsigned long *, ids) + __dynamic_array(unsigned long, ids, count) + ), + + TP_fast_assign( + __entry->client = client; + __entry->is_pin = is_pin; + __entry->count = count; + __entry->ids = ids; + memcpy(__get_dynamic_array(ids), ids, + sizeof(unsigned long) * count); + ), + + TP_printk("client=%p, is_pin=%d, count=%d, ids=[%s]", + __entry->client, __entry->is_pin, __entry->count, + __print_hex(__get_dynamic_array(ids), __entry->ids ? + sizeof(unsigned long) * __entry->count : 0)) +); + + +DECLARE_EVENT_CLASS(pin_unpin, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 pin_count + ), + + TP_ARGS(client, h, pin_count), + + TP_STRUCT__entry( + __field(struct nvmap_client *, client) + __field(struct nvmap_handle *, h) + __field(u32, pin_count) + ), + + TP_fast_assign( + __entry->client = client; + __entry->h = h; + __entry->pin_count = pin_count; + ), + + TP_printk("client=%p, name=%s, h=%p, pin_count=%d", + __entry->client, __entry->client->name, + __entry->h, __entry->pin_count) +); + +DEFINE_EVENT(pin_unpin, handle_pin, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 pin_count + ), + TP_ARGS(client, h, pin_count) +); + +DEFINE_EVENT(pin_unpin, handle_unpin, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 pin_count + ), + TP_ARGS(client, h, pin_count) +); + +DEFINE_EVENT(pin_unpin, handle_unpin_error, + TP_PROTO(struct nvmap_client *client, + struct nvmap_handle *h, + u32 pin_count + ), + TP_ARGS(client, h, pin_count) +); + +#endif /* _TRACE_NVMAP_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/trace/events/power.h b/include/trace/events/power.h index 503fc2b870b9..ce7e46d40a48 100644 --- a/include/trace/events/power.h +++ b/include/trace/events/power.h @@ -39,8 +39,111 @@ DEFINE_EVENT(cpu, cpu_idle, #define _PWR_EVENT_AVOID_DOUBLE_DEFINING #define PWR_EVENT_EXIT -1 + +enum { + CPU_SUSPEND_START, + CPU_SUSPEND_DONE +}; + +enum { + POWER_CPU_UP_START, + POWER_CPU_UP_DONE, + POWER_CPU_DOWN_START, + POWER_CPU_DOWN_DONE, +}; + +enum { + POWER_CPU_SCALE_START, + POWER_CPU_SCALE_DONE, +}; + +enum { + POWER_CPU_CLUSTER_START, + POWER_CPU_CLUSTER_DONE, +}; + #endif +TRACE_EVENT(cpu_suspend, + + TP_PROTO(unsigned int state), + + TP_ARGS(state), + + TP_STRUCT__entry( + __field(u32, state) + ), + + TP_fast_assign( + __entry->state = state; + ), + + TP_printk("state=%lu", (unsigned long)__entry->state) +); + +TRACE_EVENT(cpu_hotplug, + + TP_PROTO(unsigned int cpu_id, int state), + + TP_ARGS(cpu_id, state), + + TP_STRUCT__entry( + __field(u32, cpu_id) + __field(u32, state) + ), + + TP_fast_assign( + __entry->cpu_id = cpu_id; + __entry->state = state; + ), + + TP_printk("cpu_id=%lu, state=%lu", + (unsigned long)__entry->cpu_id, + (unsigned long)__entry->state) +); + +TRACE_EVENT(cpu_scale, + + TP_PROTO(unsigned int cpu_id, unsigned int freq, int state), + + TP_ARGS(cpu_id, freq, state), + + TP_STRUCT__entry( + __field(u64, cpu_id) + __field(u32, freq) + __field(u32, state) + ), + + TP_fast_assign( + __entry->cpu_id = cpu_id; + __entry->freq = freq; + __entry->state = state; + ), + + TP_printk("cpu_id=%lu, freq=%lu, state=%lu", + (unsigned long)__entry->cpu_id, + (unsigned long)__entry->freq, + (unsigned long)__entry->state) +); + +TRACE_EVENT(cpu_cluster, + + TP_PROTO(int state), + + TP_ARGS(state), + + TP_STRUCT__entry( + __field(u64, state) + ), + + TP_fast_assign( + __entry->state = state; + ), + + TP_printk("state=%lu", + (unsigned long)__entry->state) +); + DEFINE_EVENT(cpu, cpu_frequency, TP_PROTO(unsigned int frequency, unsigned int cpu_id), diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h index fb795c3b3c17..cd82f184c63a 100644 --- a/include/uapi/linux/fb.h +++ b/include/uapi/linux/fb.h @@ -226,6 +226,19 @@ struct fb_bitfield { #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ +#define FB_FLAG_RATIO_4_3 64 +#define FB_FLAG_RATIO_16_9 128 +#define FB_FLAG_PIXEL_REPEAT 256 + +/* + * Stereo modes + */ +#define FB_VMODE_STEREO_NONE 0x00000000 /* not stereo */ +#define FB_VMODE_STEREO_FRAME_PACK 0x01000000 /* frame packing */ +#define FB_VMODE_STEREO_TOP_BOTTOM 0x02000000 /* top-bottom */ +#define FB_VMODE_STEREO_LEFT_RIGHT 0x04000000 /* left-right */ +#define FB_VMODE_STEREO_MASK 0xFF000000 + /* * Display rotation support */ diff --git a/include/uapi/linux/firewire-cdev.h b/include/uapi/linux/firewire-cdev.h index d50036953497..1db453e4b550 100644 --- a/include/uapi/linux/firewire-cdev.h +++ b/include/uapi/linux/firewire-cdev.h @@ -215,8 +215,8 @@ struct fw_cdev_event_request2 { * with the %FW_CDEV_ISO_INTERRUPT bit set, when explicitly requested with * %FW_CDEV_IOC_FLUSH_ISO, or when there have been so many completed packets * without the interrupt bit set that the kernel's internal buffer for @header - * is about to overflow. (In the last case, kernels with ABI version < 5 drop - * header data up to the next interrupt packet.) + * is about to overflow. (In the last case, ABI versions < 5 drop header data + * up to the next interrupt packet.) * * Isochronous transmit events (context type %FW_CDEV_ISO_CONTEXT_TRANSMIT): * diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h index 0e949cbfd333..19bff0452b1e 100644 --- a/include/uapi/linux/i2c.h +++ b/include/uapi/linux/i2c.h @@ -100,6 +100,7 @@ struct i2c_msg { #define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000 #define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */ #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */ +#define I2C_FUNC_I2C_SLAVE_SUPPORT 0x10000000 /* i2c slave support */ #define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \ I2C_FUNC_SMBUS_WRITE_BYTE) diff --git a/include/uapi/linux/if_pppox.h b/include/uapi/linux/if_pppox.h index 772cf0841e9a..87f478b0ca6f 100644 --- a/include/uapi/linux/if_pppox.h +++ b/include/uapi/linux/if_pppox.h @@ -139,11 +139,11 @@ struct pppoe_tag { struct pppoe_hdr { #if defined(__LITTLE_ENDIAN_BITFIELD) - __u8 ver : 4; __u8 type : 4; + __u8 ver : 4; #elif defined(__BIG_ENDIAN_BITFIELD) - __u8 type : 4; __u8 ver : 4; + __u8 type : 4; #else #error "Please fix <asm/byteorder.h>" #endif diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index e6322605b138..8303853fd1dd 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -2,10 +2,10 @@ * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. - * - * Redistribution of this file is permitted under the terms of the GNU + * + * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) - * + * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). @@ -90,7 +90,7 @@ #define UART_LCR 3 /* Out: Line Control Register */ /* - * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ @@ -114,8 +114,10 @@ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_HW_RTS 0x40 /* Enable hw control of RTS (Tegra UART) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_HW_CTS 0x20 /* Enable HW based CTS control (Tegra UART)*/ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ diff --git a/include/video/nvhdcp.h b/include/video/nvhdcp.h new file mode 100644 index 000000000000..f282ff8caa99 --- /dev/null +++ b/include/video/nvhdcp.h @@ -0,0 +1,91 @@ +/* + * include/video/nvhdcp.h + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_NVHDCP_H_ +#define _LINUX_NVHDCP_H_ + +#include <linux/fb.h> +#include <linux/types.h> +#include <asm/ioctl.h> + +/* maximum receivers and repeaters connected at a time */ +#define TEGRA_NVHDCP_MAX_DEVS 127 + +/* values for value_flags */ +#define TEGRA_NVHDCP_FLAG_AN 0x0001 +#define TEGRA_NVHDCP_FLAG_AKSV 0x0002 +#define TEGRA_NVHDCP_FLAG_BKSV 0x0004 +#define TEGRA_NVHDCP_FLAG_BSTATUS 0x0008 /* repeater status */ +#define TEGRA_NVHDCP_FLAG_CN 0x0010 /* c_n */ +#define TEGRA_NVHDCP_FLAG_CKSV 0x0020 /* c_ksv */ +#define TEGRA_NVHDCP_FLAG_DKSV 0x0040 /* d_ksv */ +#define TEGRA_NVHDCP_FLAG_KP 0x0080 /* k_prime */ +#define TEGRA_NVHDCP_FLAG_S 0x0100 /* hdcp_status */ +#define TEGRA_NVHDCP_FLAG_CS 0x0200 /* connection state */ +#define TEGRA_NVHDCP_FLAG_V 0x0400 +#define TEGRA_NVHDCP_FLAG_MP 0x0800 +#define TEGRA_NVHDCP_FLAG_BKSVLIST 0x1000 + +/* values for packet_results */ +#define TEGRA_NVHDCP_RESULT_SUCCESS 0 +#define TEGRA_NVHDCP_RESULT_UNSUCCESSFUL 1 +#define TEGRA_NVHDCP_RESULT_PENDING 0x103 +#define TEGRA_NVHDCP_RESULT_LINK_FAILED 0xc0000013 +/* TODO: replace with -EINVAL */ +#define TEGRA_NVHDCP_RESULT_INVALID_PARAMETER 0xc000000d +#define TEGRA_NVHDCP_RESULT_INVALID_PARAMETER_MIX 0xc0000030 +/* TODO: replace with -ENOMEM */ +#define TEGRA_NVHDCP_RESULT_NO_MEMORY 0xc0000017 + +struct tegra_nvhdcp_packet { + __u32 value_flags; // (IN/OUT) + __u32 packet_results; // (OUT) + + __u64 c_n; // (IN) upstream exchange number + __u64 c_ksv; // (IN) + + __u32 b_status; // (OUT) link/repeater status + __u64 hdcp_status; // (OUT) READ_S + __u64 cs; // (OUT) Connection State + + __u64 k_prime; // (OUT) + __u64 a_n; // (OUT) + __u64 a_ksv; // (OUT) + __u64 b_ksv; // (OUT) + __u64 d_ksv; // (OUT) + __u8 v_prime[20]; // (OUT) 160-bit + __u64 m_prime; // (OUT) + + // (OUT) Valid KSVs in the bKsvList. Maximum is 127 devices + __u32 num_bksv_list; + + // (OUT) Up to 127 receivers & repeaters + __u64 bksv_list[TEGRA_NVHDCP_MAX_DEVS]; +}; + +/* parameters to TEGRAIO_NVHDCP_SET_POLICY */ +#define TEGRA_NVHDCP_POLICY_ON_DEMAND 0 +#define TEGRA_NVHDCP_POLICY_ALWAYS_ON 1 + +/* ioctls */ +#define TEGRAIO_NVHDCP_ON _IO('F', 0x70) +#define TEGRAIO_NVHDCP_OFF _IO('F', 0x71) +#define TEGRAIO_NVHDCP_SET_POLICY _IOW('F', 0x72, __u32) +#define TEGRAIO_NVHDCP_READ_M _IOWR('F', 0x73, struct tegra_nvhdcp_packet) +#define TEGRAIO_NVHDCP_READ_S _IOWR('F', 0x74, struct tegra_nvhdcp_packet) +#define TEGRAIO_NVHDCP_RENEGOTIATE _IO('F', 0x75) + +#endif diff --git a/include/video/tegra_dc_ext.h b/include/video/tegra_dc_ext.h new file mode 100644 index 000000000000..edb0f6565782 --- /dev/null +++ b/include/video/tegra_dc_ext.h @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2011-2013, NVIDIA Corporation + * + * Author: Robert Morell <rmorell@nvidia.com> + * Some code based on fbdev extensions written by: + * Erik Gilling <konkers@android.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_DC_EXT_H +#define __TEGRA_DC_EXT_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#if defined(__KERNEL__) +# include <linux/time.h> +#else +# include <time.h> +# include <unistd.h> +#endif + +#define TEGRA_DC_EXT_FMT_P1 0 +#define TEGRA_DC_EXT_FMT_P2 1 +#define TEGRA_DC_EXT_FMT_P4 2 +#define TEGRA_DC_EXT_FMT_P8 3 +#define TEGRA_DC_EXT_FMT_B4G4R4A4 4 +#define TEGRA_DC_EXT_FMT_B5G5R5A 5 +#define TEGRA_DC_EXT_FMT_B5G6R5 6 +#define TEGRA_DC_EXT_FMT_AB5G5R5 7 +#define TEGRA_DC_EXT_FMT_B8G8R8A8 12 +#define TEGRA_DC_EXT_FMT_R8G8B8A8 13 +#define TEGRA_DC_EXT_FMT_B6x2G6x2R6x2A8 14 +#define TEGRA_DC_EXT_FMT_R6x2G6x2B6x2A8 15 +#define TEGRA_DC_EXT_FMT_YCbCr422 16 +#define TEGRA_DC_EXT_FMT_YUV422 17 +#define TEGRA_DC_EXT_FMT_YCbCr420P 18 +#define TEGRA_DC_EXT_FMT_YUV420P 19 +#define TEGRA_DC_EXT_FMT_YCbCr422P 20 +#define TEGRA_DC_EXT_FMT_YUV422P 21 +#define TEGRA_DC_EXT_FMT_YCbCr422R 22 +#define TEGRA_DC_EXT_FMT_YUV422R 23 +#define TEGRA_DC_EXT_FMT_YCbCr422RA 24 +#define TEGRA_DC_EXT_FMT_YUV422RA 25 + +#define TEGRA_DC_EXT_BLEND_NONE 0 +#define TEGRA_DC_EXT_BLEND_PREMULT 1 +#define TEGRA_DC_EXT_BLEND_COVERAGE 2 + +#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_H (1 << 0) +#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_V (1 << 1) +#define TEGRA_DC_EXT_FLIP_FLAG_TILED (1 << 2) +#define TEGRA_DC_EXT_FLIP_FLAG_CURSOR (1 << 3) +#define TEGRA_DC_EXT_FLIP_FLAG_GLOBAL_ALPHA (1 << 4) +#define TEGRA_DC_EXT_FLIP_FLAG_SCAN_COLUMN (1 << 6) + +struct tegra_dc_ext_flip_windowattr { + __s32 index; + __u32 buff_id; + __u32 blend; + __u32 offset; + __u32 offset_u; + __u32 offset_v; + __u32 stride; + __u32 stride_uv; + __u32 pixformat; + /* + * x, y, w, h are fixed-point: 20 bits of integer (MSB) and 12 bits of + * fractional (LSB) + */ + __u32 x; + __u32 y; + __u32 w; + __u32 h; + __u32 out_x; + __u32 out_y; + __u32 out_w; + __u32 out_h; + __u32 z; + __u32 swap_interval; + struct timespec timestamp; + __u32 pre_syncpt_id; + __u32 pre_syncpt_val; + /* These two are optional; if zero, U and V are taken from buff_id */ + __u32 buff_id_u; + __u32 buff_id_v; + __u32 flags; + __u8 global_alpha; /* requires TEGRA_DC_EXT_FLIP_FLAG_GLOBAL_ALPHA */ + /* Leave some wiggle room for future expansion */ + __u8 pad1[3]; + __u32 pad2[4]; +}; + +#define TEGRA_DC_EXT_FLIP_N_WINDOWS 3 + +struct tegra_dc_ext_flip { + struct tegra_dc_ext_flip_windowattr win[TEGRA_DC_EXT_FLIP_N_WINDOWS]; + __u32 post_syncpt_id; + __u32 post_syncpt_val; +}; + +struct tegra_dc_ext_flip_2 { + struct tegra_dc_ext_flip_windowattr *win; + __u8 win_num; + __u8 reserved1; /* unused - must be 0 */ + __u16 reserved2; /* unused - must be 0 */ + __u32 post_syncpt_id; + __u32 post_syncpt_val; + __u16 dirty_rect[4]; /* x,y,w,h for partial screen update. 0 ignores */ +}; + +/* + * Cursor image format: + * - Tegra hardware supports two colors: foreground and background, specified + * by the client in RGB8. + * - The image should be specified as two 1bpp bitmaps immediately following + * each other in memory. Each pixel in the final cursor will be constructed + * from the bitmaps with the following logic: + * bitmap1 bitmap0 + * (mask) (color) + * 1 0 transparent + * 1 1 inverted + * 0 0 background color + * 0 1 foreground color + * - Exactly one of the SIZE flags must be specified. + */ +#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_32x32 1 +#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_64x64 2 +struct tegra_dc_ext_cursor_image { + struct { + __u8 r; + __u8 g; + __u8 b; + } foreground, background; + __u32 buff_id; + __u32 flags; +}; + +/* Possible flags for struct nvdc_cursor's flags field */ +#define TEGRA_DC_EXT_CURSOR_FLAGS_VISIBLE 1 + +struct tegra_dc_ext_cursor { + __s16 x; + __s16 y; + __u32 flags; +}; + +/* + * Color conversion is performed as follows: + * + * r = sat(kyrgb * sat(y + yof) + kur * u + kvr * v) + * g = sat(kyrgb * sat(y + yof) + kug * u + kvg * v) + * b = sat(kyrgb * sat(y + yof) + kub * u + kvb * v) + * + * Coefficients should be specified as fixed-point values; the exact format + * varies for each coefficient. + * The format for each coefficient is listed below with the syntax: + * - A "s." prefix means that the coefficient has a sign bit (twos complement). + * - The first number is the number of bits in the integer component (not + * including the optional sign bit). + * - The second number is the number of bits in the fractional component. + * + * All three fields should be tightly packed, justified to the LSB of the + * 16-bit value. For example, the "s.2.8" value should be packed as: + * (MSB) 5 bits of 0, 1 bit of sign, 2 bits of integer, 8 bits of frac (LSB) + */ +struct tegra_dc_ext_csc { + __u32 win_index; + __u16 yof; /* s.7.0 */ + __u16 kyrgb; /* 2.8 */ + __u16 kur; /* s.2.8 */ + __u16 kvr; /* s.2.8 */ + __u16 kug; /* s.1.8 */ + __u16 kvg; /* s.1.8 */ + __u16 kub; /* s.2.8 */ + __u16 kvb; /* s.2.8 */ +}; + +struct tegra_dc_ext_cmu { + __u16 cmu_enable; + __u16 csc[9]; + __u16 lut1[256]; + __u16 lut2[960]; +}; + +/* + * RGB Lookup table + * + * In true-color and YUV modes this is used for post-CSC RGB->RGB lookup, i.e. + * gamma-correction. In palette-indexed RGB modes, this table designates the + * mode's color palette. + * + * To convert 8-bit per channel RGB values to 16-bit, duplicate the 8 bits + * in low and high byte, e.g. r=r|(r<<8) + * + * To just update flags, set len to 0. + * + * Current Tegra DC hardware supports 8-bit per channel to 8-bit per channel, + * and each hardware window (overlay) uses its own lookup table. + * + */ +struct tegra_dc_ext_lut { + __u32 win_index; /* window index to set lut for */ + __u32 flags; /* Flag bitmask, see TEGRA_DC_EXT_LUT_FLAGS_* */ + __u32 start; /* start index to update lut from */ + __u32 len; /* number of valid lut entries */ + __u16 *r; /* array of 16-bit red values, 0 to reset */ + __u16 *g; /* array of 16-bit green values, 0 to reset */ + __u16 *b; /* array of 16-bit blue values, 0 to reset */ +}; + +/* tegra_dc_ext_lut.flags - override global fb device lookup table. + * Default behaviour is double-lookup. + */ +#define TEGRA_DC_EXT_LUT_FLAGS_FBOVERRIDE 0x01 + +#define TEGRA_DC_EXT_FLAGS_ENABLED 1 +struct tegra_dc_ext_status { + __u32 flags; + /* Leave some wiggle room for future expansion */ + __u32 pad[3]; +}; + +struct tegra_dc_ext_feature { + __u32 length; + __u32 *entries; +}; + +#define TEGRA_DC_EXT_SET_NVMAP_FD \ + _IOW('D', 0x00, __s32) + +#define TEGRA_DC_EXT_GET_WINDOW \ + _IOW('D', 0x01, __u32) +#define TEGRA_DC_EXT_PUT_WINDOW \ + _IOW('D', 0x02, __u32) + +#define TEGRA_DC_EXT_FLIP \ + _IOWR('D', 0x03, struct tegra_dc_ext_flip) + +#define TEGRA_DC_EXT_GET_CURSOR \ + _IO('D', 0x04) +#define TEGRA_DC_EXT_PUT_CURSOR \ + _IO('D', 0x05) +#define TEGRA_DC_EXT_SET_CURSOR_IMAGE \ + _IOW('D', 0x06, struct tegra_dc_ext_cursor_image) +#define TEGRA_DC_EXT_SET_CURSOR \ + _IOW('D', 0x07, struct tegra_dc_ext_cursor) + +#define TEGRA_DC_EXT_SET_CSC \ + _IOW('D', 0x08, struct tegra_dc_ext_csc) + +#define TEGRA_DC_EXT_GET_STATUS \ + _IOR('D', 0x09, struct tegra_dc_ext_status) + +/* + * Returns the auto-incrementing vblank syncpoint for the head associated with + * this device node + */ +#define TEGRA_DC_EXT_GET_VBLANK_SYNCPT \ + _IOR('D', 0x09, __u32) + +#define TEGRA_DC_EXT_SET_LUT \ + _IOW('D', 0x0A, struct tegra_dc_ext_lut) + +#define TEGRA_DC_EXT_GET_FEATURES \ + _IOW('D', 0x0B, struct tegra_dc_ext_feature) + +#define TEGRA_DC_EXT_CURSOR_CLIP \ + _IOW('D', 0x0C, __s32) + +#define TEGRA_DC_EXT_SET_CMU \ + _IOW('D', 0x0D, struct tegra_dc_ext_cmu) + +#define TEGRA_DC_EXT_FLIP2 \ + _IOWR('D', 0x0E, struct tegra_dc_ext_flip_2) + + +enum tegra_dc_ext_control_output_type { + TEGRA_DC_EXT_DSI, + TEGRA_DC_EXT_LVDS, + TEGRA_DC_EXT_VGA, + TEGRA_DC_EXT_HDMI, + TEGRA_DC_EXT_DVI, +}; + +/* + * Get the properties for a given output. + * + * handle (in): Which output to query + * type (out): Describes the type of the output + * connected (out): Non-zero iff the output is currently connected + * associated_head (out): The head number that the output is currently + * bound to. -1 iff the output is not associated with any head. + * head_mask (out): Bitmask of which heads the output may be bound to (some + * outputs are permanently bound to a single head). + */ +struct tegra_dc_ext_control_output_properties { + __u32 handle; + enum tegra_dc_ext_control_output_type type; + __u32 connected; + __s32 associated_head; + __u32 head_mask; +}; + +/* + * This allows userspace to query the raw EDID data for the specified output + * handle. + * + * Here, the size parameter is both an input and an output: + * 1. Userspace passes in the size of the buffer allocated for data. + * 2. If size is too small, the call fails with the error EFBIG; otherwise, the + * raw EDID data is written to the buffer pointed to by data. In both + * cases, size will be filled in with the size of the data. + */ +struct tegra_dc_ext_control_output_edid { + __u32 handle; + __u32 size; + void *data; +}; + +struct tegra_dc_ext_event { + __u32 type; + ssize_t data_size; + char data[0]; +}; + +#define TEGRA_DC_EXT_EVENT_HOTPLUG 0x1 +struct tegra_dc_ext_control_event_hotplug { + __u32 handle; +}; + + +#define TEGRA_DC_EXT_CAPABILITIES_CURSOR_MODE (1 << 0) +struct tegra_dc_ext_control_capabilities { + __u32 caps; + /* Leave some wiggle room for future expansion */ + __u32 pad[3]; +}; + +#define TEGRA_DC_EXT_CONTROL_GET_NUM_OUTPUTS \ + _IOR('C', 0x00, __u32) +#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_PROPERTIES \ + _IOWR('C', 0x01, struct tegra_dc_ext_control_output_properties) +#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_EDID \ + _IOWR('C', 0x02, struct tegra_dc_ext_control_output_edid) +#define TEGRA_DC_EXT_CONTROL_SET_EVENT_MASK \ + _IOW('C', 0x03, __u32) +#define TEGRA_DC_EXT_CONTROL_GET_CAPABILITIES \ + _IOR('C', 0x04, struct tegra_dc_ext_control_capabilities) + +#endif /* __TEGRA_DC_EXT_H */ diff --git a/include/video/tegrafb.h b/include/video/tegrafb.h new file mode 100644 index 000000000000..919661b1a8e0 --- /dev/null +++ b/include/video/tegrafb.h @@ -0,0 +1,32 @@ +/* + * include/video/tegrafb.h + * + * Copyright (C) 2010 Google, Inc. + * Author: Erik Gilling <konkers@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_TEGRAFB_H_ +#define _LINUX_TEGRAFB_H_ + +#include <linux/fb.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +struct tegra_fb_modedb { + struct fb_var_screeninfo *modedb; + __u32 modedb_len; +}; + +#define FBIO_TEGRA_GET_MODEDB _IOWR('F', 0x42, struct tegra_fb_modedb) + +#endif |