diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/imx8mm-clock.h | 697 |
1 files changed, 235 insertions, 462 deletions
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 083dd6d0116d..45fcb1e9ba22 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -1,473 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2017-2018 NXP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H #define __DT_BINDINGS_CLOCK_IMX8MM_H -#define IMX8MM_CLK_DUMMY 0 -#define IMX8MM_CLK_32K 1 -#define IMX8MM_CLK_24M 2 -#define IMX8MM_OSC_HDMI_CLK 3 -#define IMX8MM_CLK_EXT1 4 -#define IMX8MM_CLK_EXT2 5 -#define IMX8MM_CLK_EXT3 6 -#define IMX8MM_CLK_EXT4 7 -#define IMX8MM_AUDIO_PLL1_REF_SEL 8 -#define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 -#define IMX8MM_DRAM_PLL_REF_SEL 11 -#define IMX8MM_GPU_PLL_REF_SEL 12 -#define IMX8MM_VPU_PLL_REF_SEL 13 -#define IMX8MM_ARM_PLL_REF_SEL 14 -#define IMX8MM_SYS_PLL1_REF_SEL 15 -#define IMX8MM_SYS_PLL2_REF_SEL 16 -#define IMX8MM_SYS_PLL3_REF_SEL 17 -#define IMX8MM_AUDIO_PLL1 18 -#define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 -#define IMX8MM_DRAM_PLL 21 -#define IMX8MM_GPU_PLL 22 -#define IMX8MM_VPU_PLL 23 -#define IMX8MM_ARM_PLL 24 -#define IMX8MM_SYS_PLL1 25 -#define IMX8MM_SYS_PLL2 26 -#define IMX8MM_SYS_PLL3 27 -#define IMX8MM_AUDIO_PLL1_BYPASS 28 -#define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 -#define IMX8MM_DRAM_PLL_BYPASS 31 -#define IMX8MM_GPU_PLL_BYPASS 32 -#define IMX8MM_VPU_PLL_BYPASS 33 -#define IMX8MM_ARM_PLL_BYPASS 34 -#define IMX8MM_SYS_PLL1_BYPASS 35 -#define IMX8MM_SYS_PLL2_BYPASS 36 -#define IMX8MM_SYS_PLL3_BYPASS 37 -#define IMX8MM_AUDIO_PLL1_OUT 38 -#define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 -#define IMX8MM_DRAM_PLL_OUT 41 -#define IMX8MM_GPU_PLL_OUT 42 -#define IMX8MM_VPU_PLL_OUT 43 -#define IMX8MM_ARM_PLL_OUT 44 -#define IMX8MM_SYS_PLL1_OUT 45 -#define IMX8MM_SYS_PLL2_OUT 46 -#define IMX8MM_SYS_PLL3_OUT 47 -#define IMX8MM_SYS_PLL1_40M 48 -#define IMX8MM_SYS_PLL1_80M 49 -#define IMX8MM_SYS_PLL1_100M 50 -#define IMX8MM_SYS_PLL1_133M 51 -#define IMX8MM_SYS_PLL1_160M 52 -#define IMX8MM_SYS_PLL1_200M 53 -#define IMX8MM_SYS_PLL1_266M 54 -#define IMX8MM_SYS_PLL1_400M 55 -#define IMX8MM_SYS_PLL1_800M 56 -#define IMX8MM_SYS_PLL2_50M 57 -#define IMX8MM_SYS_PLL2_100M 58 -#define IMX8MM_SYS_PLL2_125M 59 -#define IMX8MM_SYS_PLL2_166M 60 -#define IMX8MM_SYS_PLL2_200M 61 -#define IMX8MM_SYS_PLL2_250M 62 -#define IMX8MM_SYS_PLL2_333M 63 -#define IMX8MM_SYS_PLL2_500M 64 -#define IMX8MM_SYS_PLL2_1000M 65 -#define IMX8MM_CLK_A53_SRC 66 -#define IMX8MM_CLK_M4_SRC 67 -#define IMX8MM_CLK_VPU_SRC 68 -#define IMX8MM_CLK_GPU3D_SRC 69 -#define IMX8MM_CLK_GPU2D_SRC 70 -#define IMX8MM_CLK_A53_CG 71 -#define IMX8MM_CLK_M4_CG 72 -#define IMX8MM_CLK_VPU_CG 73 -#define IMX8MM_CLK_GPU3D_CG 74 -#define IMX8MM_CLK_GPU2D_CG 75 -#define IMX8MM_CLK_A53_DIV 76 -#define IMX8MM_CLK_M4_DIV 77 -#define IMX8MM_CLK_VPU_DIV 78 -#define IMX8MM_CLK_GPU3D_DIV 79 -#define IMX8MM_CLK_GPU2D_DIV 80 -#define IMX8MM_CLK_MAIN_AXI_SRC 81 -#define IMX8MM_CLK_ENET_AXI_SRC 82 -#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83 -#define IMX8MM_CLK_VPU_BUS_SRC 84 -#define IMX8MM_CLK_DISP_AXI_SRC 85 -#define IMX8MM_CLK_DISP_APB_SRC 86 -#define IMX8MM_CLK_DISP_RTRM_SRC 87 -#define IMX8MM_CLK_USB_BUS_SRC 88 -#define IMX8MM_CLK_GPU_AXI_SRC 89 -#define IMX8MM_CLK_GPU_AHB_SRC 90 -#define IMX8MM_CLK_NOC_SRC 91 -#define IMX8MM_CLK_NOC_APB_SRC 92 -#define IMX8MM_CLK_MAIN_AXI_CG 93 -#define IMX8MM_CLK_ENET_AXI_CG 94 -#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95 -#define IMX8MM_CLK_VPU_BUS_CG 96 -#define IMX8MM_CLK_DISP_AXI_CG 97 -#define IMX8MM_CLK_DISP_APB_CG 98 -#define IMX8MM_CLK_DISP_RTRM_CG 99 -#define IMX8MM_CLK_USB_BUS_CG 100 -#define IMX8MM_CLK_GPU_AXI_CG 101 -#define IMX8MM_CLK_GPU_AHB_CG 102 -#define IMX8MM_CLK_NOC_CG 103 -#define IMX8MM_CLK_NOC_APB_CG 104 -#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105 -#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106 -#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107 -#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108 -#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109 -#define IMX8MM_CLK_DISP_APB_PRE_DIV 110 -#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111 -#define IMX8MM_CLK_USB_BUS_PRE_DIV 112 -#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113 -#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114 -#define IMX8MM_CLK_NOC_PRE_DIV 115 -#define IMX8MM_CLK_NOC_APB_PRE_DIV 116 -#define IMX8MM_CLK_MAIN_AXI_DIV 117 -#define IMX8MM_CLK_ENET_AXI_DIV 118 -#define IMX8MM_CLK_NAND_USDHC_BUS_DIV 119 -#define IMX8MM_CLK_VPU_BUS_DIV 120 -#define IMX8MM_CLK_DISP_AXI_DIV 121 -#define IMX8MM_CLK_DISP_APB_DIV 122 -#define IMX8MM_CLK_DISP_RTRM_DIV 123 -#define IMX8MM_CLK_USB_BUS_DIV 124 -#define IMX8MM_CLK_GPU_AXI_DIV 125 -#define IMX8MM_CLK_GPU_AHB_DIV 126 -#define IMX8MM_CLK_NOC_DIV 127 -#define IMX8MM_CLK_NOC_APB_DIV 128 -#define IMX8MM_CLK_AHB_SRC 129 -#define IMX8MM_CLK_AUDIO_AHB_SRC 130 -#define IMX8MM_CLK_DSI_ESC_RX_SRC 131 -#define IMX8MM_CLK_AHB_CG 132 -#define IMX8MM_CLK_AUDIO_AHB_CG 133 -#define IMX8MM_CLK_DSI_ESC_RX_CG 134 -#define IMX8MM_CLK_AHB_PRE_DIV 135 -#define IMX8MM_CLK_AUDIO_AHB_PRE_DIV 136 -#define IMX8MM_CLK_DSI_ESC_RX_PRE_DIV 137 -#define IMX8MM_CLK_AHB_DIV 138 -#define IMX8MM_CLK_AUDIO_AHB_DIV 139 -#define IMX8MM_CLK_DSI_ESC_RX_DIV 140 -#define IMX8MM_CLK_IPG_ROOT 141 -#define IMX8MM_CLK_IPG_AUDIO_ROOT 142 -#define IMX8MM_CLK_IPG_DSI_ESC_RX_ROOT 143 -#define IMX8MM_CLK_DRAM_ALT_SRC 144 -#define IMX8MM_CLK_DRAM_APB_SRC 145 -#define IMX8MM_CLK_VPU_G1_SRC 146 -#define IMX8MM_CLK_VPU_G2_SRC 147 -#define IMX8MM_CLK_DISP_DTRC_SRC 148 -#define IMX8MM_CLK_DISP_DC8000_SRC 149 -#define IMX8MM_CLK_PCIE1_CTRL_SRC 150 -#define IMX8MM_CLK_PCIE1_PHY_SRC 151 -#define IMX8MM_CLK_PCIE1_AUX_SRC 152 -#define IMX8MM_CLK_DC_PIXEL_SRC 153 -#define IMX8MM_CLK_LCDIF_PIXEL_SRC 154 -#define IMX8MM_CLK_SAI1_SRC 155 -#define IMX8MM_CLK_SAI2_SRC 156 -#define IMX8MM_CLK_SAI3_SRC 157 -#define IMX8MM_CLK_SAI4_SRC 158 -#define IMX8MM_CLK_SAI5_SRC 159 -#define IMX8MM_CLK_SAI6_SRC 160 -#define IMX8MM_CLK_SPDIF1_SRC 161 -#define IMX8MM_CLK_SPDIF2_SRC 162 -#define IMX8MM_CLK_ENET_REF_SRC 163 -#define IMX8MM_CLK_ENET_TIMER_SRC 164 -#define IMX8MM_CLK_ENET_PHY_REF_SRC 165 -#define IMX8MM_CLK_NAND_SRC 166 -#define IMX8MM_CLK_QSPI_SRC 167 -#define IMX8MM_CLK_USDHC1_SRC 168 -#define IMX8MM_CLK_USDHC2_SRC 169 -#define IMX8MM_CLK_I2C1_SRC 170 -#define IMX8MM_CLK_I2C2_SRC 171 -#define IMX8MM_CLK_I2C3_SRC 172 -#define IMX8MM_CLK_I2C4_SRC 173 -#define IMX8MM_CLK_UART1_SRC 174 -#define IMX8MM_CLK_UART2_SRC 175 -#define IMX8MM_CLK_UART3_SRC 176 -#define IMX8MM_CLK_UART4_SRC 177 -#define IMX8MM_CLK_USB_CORE_REF_SRC 178 -#define IMX8MM_CLK_USB_PHY_REF_SRC 179 -#define IMX8MM_CLK_ECSPI1_SRC 180 -#define IMX8MM_CLK_ECSPI2_SRC 181 -#define IMX8MM_CLK_PWM1_SRC 182 -#define IMX8MM_CLK_PWM2_SRC 183 -#define IMX8MM_CLK_PWM3_SRC 184 -#define IMX8MM_CLK_PWM4_SRC 185 -#define IMX8MM_CLK_GPT1_SRC 186 -#define IMX8MM_CLK_WDOG_SRC 187 -#define IMX8MM_CLK_WRCLK_SRC 188 -#define IMX8MM_CLK_DSI_CORE_SRC 189 -#define IMX8MM_CLK_DSI_PHY_REF_SRC 190 -#define IMX8MM_CLK_DSI_DBI_SRC 191 -#define IMX8MM_CLK_USDHC3_SRC 192 -#define IMX8MM_CLK_CSI1_CORE_SRC 193 -#define IMX8MM_CLK_CSI1_PHY_REF_SRC 194 -#define IMX8MM_CLK_CSI1_ESC_SRC 195 -#define IMX8MM_CLK_CSI2_CORE_SRC 196 -#define IMX8MM_CLK_CSI2_PHY_REF_SRC 197 -#define IMX8MM_CLK_CSI2_ESC_SRC 198 -#define IMX8MM_CLK_PCIE2_CTRL_SRC 199 -#define IMX8MM_CLK_PCIE2_PHY_SRC 200 -#define IMX8MM_CLK_PCIE2_AUX_SRC 201 -#define IMX8MM_CLK_ECSPI3_SRC 202 -#define IMX8MM_CLK_PDM_SRC 203 -#define IMX8MM_CLK_VPU_H1_SRC 204 -#define IMX8MM_CLK_DRAM_ALT_CG 205 -#define IMX8MM_CLK_DRAM_APB_CG 206 -#define IMX8MM_CLK_VPU_G1_CG 207 -#define IMX8MM_CLK_VPU_G2_CG 208 -#define IMX8MM_CLK_DISP_DTRC_CG 209 -#define IMX8MM_CLK_DISP_DC8000_CG 210 -#define IMX8MM_CLK_PCIE1_CTRL_CG 211 -#define IMX8MM_CLK_PCIE1_PHY_CG 212 -#define IMX8MM_CLK_PCIE1_AUX_CG 213 -#define IMX8MM_CLK_DC_PIXEL_CG 214 -#define IMX8MM_CLK_LCDIF_PIXEL_CG 215 -#define IMX8MM_CLK_SAI1_CG 216 -#define IMX8MM_CLK_SAI2_CG 217 -#define IMX8MM_CLK_SAI3_CG 218 -#define IMX8MM_CLK_SAI4_CG 219 -#define IMX8MM_CLK_SAI5_CG 220 -#define IMX8MM_CLK_SAI6_CG 221 -#define IMX8MM_CLK_SPDIF1_CG 222 -#define IMX8MM_CLK_SPDIF2_CG 223 -#define IMX8MM_CLK_ENET_REF_CG 224 -#define IMX8MM_CLK_ENET_TIMER_CG 225 -#define IMX8MM_CLK_ENET_PHY_REF_CG 226 -#define IMX8MM_CLK_NAND_CG 227 -#define IMX8MM_CLK_QSPI_CG 228 -#define IMX8MM_CLK_USDHC1_CG 229 -#define IMX8MM_CLK_USDHC2_CG 230 -#define IMX8MM_CLK_I2C1_CG 231 -#define IMX8MM_CLK_I2C2_CG 232 -#define IMX8MM_CLK_I2C3_CG 233 -#define IMX8MM_CLK_I2C4_CG 234 -#define IMX8MM_CLK_UART1_CG 235 -#define IMX8MM_CLK_UART2_CG 236 -#define IMX8MM_CLK_UART3_CG 237 -#define IMX8MM_CLK_UART4_CG 238 -#define IMX8MM_CLK_USB_CORE_REF_CG 239 -#define IMX8MM_CLK_USB_PHY_REF_CG 240 -#define IMX8MM_CLK_ECSPI1_CG 241 -#define IMX8MM_CLK_ECSPI2_CG 242 -#define IMX8MM_CLK_PWM1_CG 243 -#define IMX8MM_CLK_PWM2_CG 244 -#define IMX8MM_CLK_PWM3_CG 245 -#define IMX8MM_CLK_PWM4_CG 246 -#define IMX8MM_CLK_GPT1_CG 247 -#define IMX8MM_CLK_WDOG_CG 248 -#define IMX8MM_CLK_WRCLK_CG 249 -#define IMX8MM_CLK_DSI_CORE_CG 250 -#define IMX8MM_CLK_DSI_PHY_REF_CG 251 -#define IMX8MM_CLK_DSI_DBI_CG 252 -#define IMX8MM_CLK_USDHC3_CG 253 -#define IMX8MM_CLK_CSI1_CORE_CG 254 -#define IMX8MM_CLK_CSI1_PHY_REF_CG 255 -#define IMX8MM_CLK_CSI1_ESC_CG 256 -#define IMX8MM_CLK_CSI2_CORE_CG 257 -#define IMX8MM_CLK_CSI2_PHY_REF_CG 258 -#define IMX8MM_CLK_CSI2_ESC_CG 259 -#define IMX8MM_CLK_PCIE2_CTRL_CG 260 -#define IMX8MM_CLK_PCIE2_PHY_CG 261 -#define IMX8MM_CLK_PCIE2_AUX_CG 262 -#define IMX8MM_CLK_ECSPI3_CG 263 -#define IMX8MM_CLK_PDM_CG 264 -#define IMX8MM_CLK_VPU_H1_CG 265 -#define IMX8MM_CLK_DRAM_ALT_PRE_DIV 266 -#define IMX8MM_CLK_DRAM_APB_PRE_DIV 267 -#define IMX8MM_CLK_VPU_G1_PRE_DIV 268 -#define IMX8MM_CLK_VPU_G2_PRE_DIV 269 -#define IMX8MM_CLK_DISP_DTRC_PRE_DIV 270 -#define IMX8MM_CLK_DISP_DC8000_PRE_DIV 271 -#define IMX8MM_CLK_PCIE1_CTRL_PRE_DIV 272 -#define IMX8MM_CLK_PCIE1_PHY_PRE_DIV 273 -#define IMX8MM_CLK_PCIE1_AUX_PRE_DIV 274 -#define IMX8MM_CLK_DC_PIXEL_PRE_DIV 275 -#define IMX8MM_CLK_LCDIF_PIXEL_PRE_DIV 276 -#define IMX8MM_CLK_SAI1_PRE_DIV 277 -#define IMX8MM_CLK_SAI2_PRE_DIV 278 -#define IMX8MM_CLK_SAI3_PRE_DIV 279 -#define IMX8MM_CLK_SAI4_PRE_DIV 280 -#define IMX8MM_CLK_SAI5_PRE_DIV 281 -#define IMX8MM_CLK_SAI6_PRE_DIV 282 -#define IMX8MM_CLK_SPDIF1_PRE_DIV 283 -#define IMX8MM_CLK_SPDIF2_PRE_DIV 284 -#define IMX8MM_CLK_ENET_REF_PRE_DIV 285 -#define IMX8MM_CLK_ENET_TIMER_PRE_DIV 286 -#define IMX8MM_CLK_ENET_PHY_REF_PRE_DIV 287 -#define IMX8MM_CLK_NAND_PRE_DIV 288 -#define IMX8MM_CLK_QSPI_PRE_DIV 289 -#define IMX8MM_CLK_USDHC1_PRE_DIV 290 -#define IMX8MM_CLK_USDHC2_PRE_DIV 291 -#define IMX8MM_CLK_I2C1_PRE_DIV 292 -#define IMX8MM_CLK_I2C2_PRE_DIV 293 -#define IMX8MM_CLK_I2C3_PRE_DIV 294 -#define IMX8MM_CLK_I2C4_PRE_DIV 295 -#define IMX8MM_CLK_UART1_PRE_DIV 296 -#define IMX8MM_CLK_UART2_PRE_DIV 297 -#define IMX8MM_CLK_UART3_PRE_DIV 298 -#define IMX8MM_CLK_UART4_PRE_DIV 299 -#define IMX8MM_CLK_USB_CORE_REF_PRE_DIV 300 -#define IMX8MM_CLK_USB_PHY_REF_PRE_DIV 301 -#define IMX8MM_CLK_ECSPI1_PRE_DIV 302 -#define IMX8MM_CLK_ECSPI2_PRE_DIV 303 -#define IMX8MM_CLK_PWM1_PRE_DIV 304 -#define IMX8MM_CLK_PWM2_PRE_DIV 305 -#define IMX8MM_CLK_PWM3_PRE_DIV 306 -#define IMX8MM_CLK_PWM4_PRE_DIV 307 -#define IMX8MM_CLK_GPT1_PRE_DIV 308 -#define IMX8MM_CLK_WDOG_PRE_DIV 309 -#define IMX8MM_CLK_WRCLK_PRE_DIV 310 -#define IMX8MM_CLK_DSI_CORE_PRE_DIV 311 -#define IMX8MM_CLK_DSI_PHY_REF_PRE_DIV 312 -#define IMX8MM_CLK_DSI_DBI_PRE_DIV 313 -#define IMX8MM_CLK_USDHC3_PRE_DIV 314 -#define IMX8MM_CLK_CSI1_CORE_PRE_DIV 315 -#define IMX8MM_CLK_CSI1_PHY_REF_PRE_DIV 316 -#define IMX8MM_CLK_CSI1_ESC_PRE_DIV 317 -#define IMX8MM_CLK_CSI2_CORE_PRE_DIV 318 -#define IMX8MM_CLK_CSI2_PHY_REF_PRE_DIV 319 -#define IMX8MM_CLK_CSI2_ESC_PRE_DIV 320 -#define IMX8MM_CLK_PCIE2_CTRL_PRE_DIV 321 -#define IMX8MM_CLK_PCIE2_PHY_PRE_DIV 322 -#define IMX8MM_CLK_PCIE2_AUX_PRE_DIV 323 -#define IMX8MM_CLK_ECSPI3_PRE_DIV 324 -#define IMX8MM_CLK_PDM_PRE_DIV 325 -#define IMX8MM_CLK_VPU_H1_PRE_DIV 326 -#define IMX8MM_CLK_DRAM_ALT_DIV 327 -#define IMX8MM_CLK_DRAM_APB_DIV 328 -#define IMX8MM_CLK_VPU_G1_DIV 329 -#define IMX8MM_CLK_VPU_G2_DIV 330 -#define IMX8MM_CLK_DISP_DTRC_DIV 331 -#define IMX8MM_CLK_DISP_DC8000_DIV 332 -#define IMX8MM_CLK_PCIE1_CTRL_DIV 333 -#define IMX8MM_CLK_PCIE1_PHY_DIV 334 -#define IMX8MM_CLK_PCIE1_AUX_DIV 335 -#define IMX8MM_CLK_DC_PIXEL_DIV 336 -#define IMX8MM_CLK_LCDIF_PIXEL_DIV 337 -#define IMX8MM_CLK_SAI1_DIV 338 -#define IMX8MM_CLK_SAI2_DIV 339 -#define IMX8MM_CLK_SAI3_DIV 340 -#define IMX8MM_CLK_SAI4_DIV 341 -#define IMX8MM_CLK_SAI5_DIV 342 -#define IMX8MM_CLK_SAI6_DIV 343 -#define IMX8MM_CLK_SPDIF1_DIV 344 -#define IMX8MM_CLK_SPDIF2_DIV 345 -#define IMX8MM_CLK_ENET_REF_DIV 346 -#define IMX8MM_CLK_ENET_TIMER_DIV 347 -#define IMX8MM_CLK_ENET_PHY_REF_DIV 348 -#define IMX8MM_CLK_NAND_DIV 349 -#define IMX8MM_CLK_QSPI_DIV 350 -#define IMX8MM_CLK_USDHC1_DIV 351 -#define IMX8MM_CLK_USDHC2_DIV 352 -#define IMX8MM_CLK_I2C1_DIV 353 -#define IMX8MM_CLK_I2C2_DIV 354 -#define IMX8MM_CLK_I2C3_DIV 355 -#define IMX8MM_CLK_I2C4_DIV 356 -#define IMX8MM_CLK_UART1_DIV 357 -#define IMX8MM_CLK_UART2_DIV 358 -#define IMX8MM_CLK_UART3_DIV 359 -#define IMX8MM_CLK_UART4_DIV 360 -#define IMX8MM_CLK_USB_CORE_REF_DIV 361 -#define IMX8MM_CLK_USB_PHY_REF_DIV 362 -#define IMX8MM_CLK_ECSPI1_DIV 363 -#define IMX8MM_CLK_ECSPI2_DIV 364 -#define IMX8MM_CLK_PWM1_DIV 365 -#define IMX8MM_CLK_PWM2_DIV 366 -#define IMX8MM_CLK_PWM3_DIV 367 -#define IMX8MM_CLK_PWM4_DIV 368 -#define IMX8MM_CLK_GPT1_DIV 369 -#define IMX8MM_CLK_WDOG_DIV 370 -#define IMX8MM_CLK_WRCLK_DIV 371 -#define IMX8MM_CLK_DSI_CORE_DIV 372 -#define IMX8MM_CLK_DSI_PHY_REF_DIV 373 -#define IMX8MM_CLK_DSI_DBI_DIV 374 -#define IMX8MM_CLK_USDHC3_DIV 375 -#define IMX8MM_CLK_CSI1_CORE_DIV 376 -#define IMX8MM_CLK_CSI1_PHY_REF_DIV 377 -#define IMX8MM_CLK_CSI1_ESC_DIV 378 -#define IMX8MM_CLK_CSI2_CORE_DIV 379 -#define IMX8MM_CLK_CSI2_PHY_REF_DIV 380 -#define IMX8MM_CLK_CSI2_ESC_DIV 381 -#define IMX8MM_CLK_PCIE2_CTRL_DIV 382 -#define IMX8MM_CLK_PCIE2_PHY_DIV 383 -#define IMX8MM_CLK_PCIE2_AUX_DIV 384 -#define IMX8MM_CLK_ECSPI3_DIV 385 -#define IMX8MM_CLK_PDM_DIV 386 -#define IMX8MM_CLK_VPU_H1_DIV 387 -#define IMX8MM_CLK_ECSPI1_ROOT 388 -#define IMX8MM_CLK_ECSPI2_ROOT 389 -#define IMX8MM_CLK_ECSPI3_ROOT 390 -#define IMX8MM_CLK_ENET1_ROOT 391 -#define IMX8MM_CLK_GPT1_ROOT 392 -#define IMX8MM_CLK_I2C1_ROOT 393 -#define IMX8MM_CLK_I2C2_ROOT 394 -#define IMX8MM_CLK_I2C3_ROOT 395 -#define IMX8MM_CLK_I2C4_ROOT 396 -#define IMX8MM_CLK_OCOTP_ROOT 397 -#define IMX8MM_CLK_PCIE1_ROOT 398 -#define IMX8MM_CLK_PWM1_ROOT 399 -#define IMX8MM_CLK_PWM2_ROOT 400 -#define IMX8MM_CLK_PWM3_ROOT 401 -#define IMX8MM_CLK_PWM4_ROOT 402 -#define IMX8MM_CLK_QSPI_ROOT 403 -#define IMX8MM_CLK_NAND_ROOT 404 -#define IMX8MM_CLK_SAI1_ROOT 405 -#define IMX8MM_CLK_SAI1_IPG 406 -#define IMX8MM_CLK_SAI2_ROOT 407 -#define IMX8MM_CLK_SAI2_IPG 408 -#define IMX8MM_CLK_SAI3_ROOT 409 -#define IMX8MM_CLK_SAI3_IPG 410 -#define IMX8MM_CLK_SAI4_ROOT 411 -#define IMX8MM_CLK_SAI4_IPG 412 -#define IMX8MM_CLK_SAI5_ROOT 413 -#define IMX8MM_CLK_SAI5_IPG 414 -#define IMX8MM_CLK_SAI6_ROOT 415 -#define IMX8MM_CLK_SAI6_IPG 416 -#define IMX8MM_CLK_UART1_ROOT 417 -#define IMX8MM_CLK_UART2_ROOT 418 -#define IMX8MM_CLK_UART3_ROOT 419 -#define IMX8MM_CLK_UART4_ROOT 420 -#define IMX8MM_CLK_USB1_CTRL_ROOT 421 -#define IMX8MM_CLK_GPU3D_ROOT 422 -#define IMX8MM_CLK_USDHC1_ROOT 423 -#define IMX8MM_CLK_USDHC2_ROOT 424 -#define IMX8MM_CLK_WDOG1_ROOT 425 -#define IMX8MM_CLK_WDOG2_ROOT 426 -#define IMX8MM_CLK_WDOG3_ROOT 427 -#define IMX8MM_CLK_VPU_G1_ROOT 428 -#define IMX8MM_CLK_GPU_BUS_ROOT 429 -#define IMX8MM_CLK_VPU_H1_ROOT 430 -#define IMX8MM_CLK_VPU_G2_ROOT 431 -#define IMX8MM_CLK_PDM_ROOT 432 -#define IMX8MM_CLK_DISP_ROOT 433 -#define IMX8MM_CLK_DISP_AXI_ROOT 434 -#define IMX8MM_CLK_DISP_APB_ROOT 435 -#define IMX8MM_CLK_DISP_RTRM_ROOT 436 -#define IMX8MM_CLK_USDHC3_ROOT 437 -#define IMX8MM_CLK_TMU_ROOT 438 -#define IMX8MM_CLK_VPU_DEC_ROOT 439 -#define IMX8MM_CLK_SDMA1_ROOT 440 -#define IMX8MM_CLK_SDMA2_ROOT 441 -#define IMX8MM_CLK_SDMA3_ROOT 442 -#define IMX8MM_CLK_GPT_3M 443 -#define IMX8MM_CLK_ARM 444 -#define IMX8MM_CLK_PDM_IPG 445 -#define IMX8MM_CLK_GPU2D_ROOT 446 -#define IMX8MM_CLK_MU_ROOT 447 -#define IMX8MM_CLK_CSI1_ROOT 448 -#define IMX8MM_CLK_CLKO1_SRC 449 -#define IMX8MM_CLK_CLKO1_CG 450 -#define IMX8MM_CLK_CLKO1_PRE_DIV 451 -#define IMX8MM_CLK_CLKO1_DIV 452 +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MM_CLK_EXT1 4 +#define IMX8MM_CLK_EXT2 5 +#define IMX8MM_CLK_EXT3 6 +#define IMX8MM_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 -#define IMX8MM_CLK_DRAM_CORE 453 -#define IMX8MM_CLK_DRAM_ALT_ROOT 454 +/* core */ +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG 74 +#define IMX8MM_CLK_GPU2D_CG 75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 -#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 455 -#define IMX8MM_CLK_SIM_HSIO 456 +/* bus */ +#define IMX8MM_CLK_MAIN_AXI 81 +#define IMX8MM_CLK_ENET_AXI 82 +#define IMX8MM_CLK_NAND_USDHC_BUS 83 +#define IMX8MM_CLK_VPU_BUS 84 +#define IMX8MM_CLK_DISP_AXI 85 +#define IMX8MM_CLK_DISP_APB 86 +#define IMX8MM_CLK_DISP_RTRM 87 +#define IMX8MM_CLK_USB_BUS 88 +#define IMX8MM_CLK_GPU_AXI 89 +#define IMX8MM_CLK_GPU_AHB 90 +#define IMX8MM_CLK_NOC 91 +#define IMX8MM_CLK_NOC_APB 92 + +#define IMX8MM_CLK_AHB 93 +#define IMX8MM_CLK_AUDIO_AHB 94 +#define IMX8MM_CLK_IPG_ROOT 95 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 + +#define IMX8MM_CLK_DRAM_ALT 97 +#define IMX8MM_CLK_DRAM_APB 98 +#define IMX8MM_CLK_VPU_G1 99 +#define IMX8MM_CLK_VPU_G2 100 +#define IMX8MM_CLK_DISP_DTRC 101 +#define IMX8MM_CLK_DISP_DC8000 102 +#define IMX8MM_CLK_PCIE1_CTRL 103 +#define IMX8MM_CLK_PCIE1_PHY 104 +#define IMX8MM_CLK_PCIE1_AUX 105 +#define IMX8MM_CLK_DC_PIXEL 106 +#define IMX8MM_CLK_LCDIF_PIXEL 107 +#define IMX8MM_CLK_SAI1 108 +#define IMX8MM_CLK_SAI2 109 +#define IMX8MM_CLK_SAI3 110 +#define IMX8MM_CLK_SAI4 111 +#define IMX8MM_CLK_SAI5 112 +#define IMX8MM_CLK_SAI6 113 +#define IMX8MM_CLK_SPDIF1 114 +#define IMX8MM_CLK_SPDIF2 115 +#define IMX8MM_CLK_ENET_REF 116 +#define IMX8MM_CLK_ENET_TIMER 117 +#define IMX8MM_CLK_ENET_PHY_REF 118 +#define IMX8MM_CLK_NAND 119 +#define IMX8MM_CLK_QSPI 120 +#define IMX8MM_CLK_USDHC1 121 +#define IMX8MM_CLK_USDHC2 122 +#define IMX8MM_CLK_I2C1 123 +#define IMX8MM_CLK_I2C2 124 +#define IMX8MM_CLK_I2C3 125 +#define IMX8MM_CLK_I2C4 126 +#define IMX8MM_CLK_UART1 127 +#define IMX8MM_CLK_UART2 128 +#define IMX8MM_CLK_UART3 129 +#define IMX8MM_CLK_UART4 130 +#define IMX8MM_CLK_USB_CORE_REF 131 +#define IMX8MM_CLK_USB_PHY_REF 132 +#define IMX8MM_CLK_ECSPI1 133 +#define IMX8MM_CLK_ECSPI2 134 +#define IMX8MM_CLK_PWM1 135 +#define IMX8MM_CLK_PWM2 136 +#define IMX8MM_CLK_PWM3 137 +#define IMX8MM_CLK_PWM4 138 +#define IMX8MM_CLK_GPT1 139 +#define IMX8MM_CLK_WDOG 140 +#define IMX8MM_CLK_WRCLK 141 +#define IMX8MM_CLK_DSI_CORE 142 +#define IMX8MM_CLK_DSI_PHY_REF 143 +#define IMX8MM_CLK_DSI_DBI 144 +#define IMX8MM_CLK_USDHC3 145 +#define IMX8MM_CLK_CSI1_CORE 146 +#define IMX8MM_CLK_CSI1_PHY_REF 147 +#define IMX8MM_CLK_CSI1_ESC 148 +#define IMX8MM_CLK_CSI2_CORE 149 +#define IMX8MM_CLK_CSI2_PHY_REF 150 +#define IMX8MM_CLK_CSI2_ESC 151 +#define IMX8MM_CLK_PCIE2_CTRL 152 +#define IMX8MM_CLK_PCIE2_PHY 153 +#define IMX8MM_CLK_PCIE2_AUX 154 +#define IMX8MM_CLK_ECSPI3 155 +#define IMX8MM_CLK_PDM 156 +#define IMX8MM_CLK_VPU_H1 157 +#define IMX8MM_CLK_CLKO1 158 + +#define IMX8MM_CLK_ECSPI1_ROOT 159 +#define IMX8MM_CLK_ECSPI2_ROOT 160 +#define IMX8MM_CLK_ECSPI3_ROOT 161 +#define IMX8MM_CLK_ENET1_ROOT 162 +#define IMX8MM_CLK_GPT1_ROOT 163 +#define IMX8MM_CLK_I2C1_ROOT 164 +#define IMX8MM_CLK_I2C2_ROOT 165 +#define IMX8MM_CLK_I2C3_ROOT 166 +#define IMX8MM_CLK_I2C4_ROOT 167 +#define IMX8MM_CLK_OCOTP_ROOT 168 +#define IMX8MM_CLK_PCIE1_ROOT 169 +#define IMX8MM_CLK_PWM1_ROOT 170 +#define IMX8MM_CLK_PWM2_ROOT 171 +#define IMX8MM_CLK_PWM3_ROOT 172 +#define IMX8MM_CLK_PWM4_ROOT 173 +#define IMX8MM_CLK_QSPI_ROOT 174 +#define IMX8MM_CLK_NAND_ROOT 175 +#define IMX8MM_CLK_SAI1_ROOT 176 +#define IMX8MM_CLK_SAI1_IPG 177 +#define IMX8MM_CLK_SAI2_ROOT 178 +#define IMX8MM_CLK_SAI2_IPG 179 +#define IMX8MM_CLK_SAI3_ROOT 180 +#define IMX8MM_CLK_SAI3_IPG 181 +#define IMX8MM_CLK_SAI4_ROOT 182 +#define IMX8MM_CLK_SAI4_IPG 183 +#define IMX8MM_CLK_SAI5_ROOT 184 +#define IMX8MM_CLK_SAI5_IPG 185 +#define IMX8MM_CLK_SAI6_ROOT 186 +#define IMX8MM_CLK_SAI6_IPG 187 +#define IMX8MM_CLK_UART1_ROOT 188 +#define IMX8MM_CLK_UART2_ROOT 189 +#define IMX8MM_CLK_UART3_ROOT 190 +#define IMX8MM_CLK_UART4_ROOT 191 +#define IMX8MM_CLK_USB1_CTRL_ROOT 192 +#define IMX8MM_CLK_GPU3D_ROOT 193 +#define IMX8MM_CLK_USDHC1_ROOT 194 +#define IMX8MM_CLK_USDHC2_ROOT 195 +#define IMX8MM_CLK_WDOG1_ROOT 196 +#define IMX8MM_CLK_WDOG2_ROOT 197 +#define IMX8MM_CLK_WDOG3_ROOT 198 +#define IMX8MM_CLK_VPU_G1_ROOT 199 +#define IMX8MM_CLK_GPU_BUS_ROOT 200 +#define IMX8MM_CLK_VPU_H1_ROOT 201 +#define IMX8MM_CLK_VPU_G2_ROOT 202 +#define IMX8MM_CLK_PDM_ROOT 203 +#define IMX8MM_CLK_DISP_ROOT 204 +#define IMX8MM_CLK_DISP_AXI_ROOT 205 +#define IMX8MM_CLK_DISP_APB_ROOT 206 +#define IMX8MM_CLK_DISP_RTRM_ROOT 207 +#define IMX8MM_CLK_USDHC3_ROOT 208 +#define IMX8MM_CLK_TMU_ROOT 209 +#define IMX8MM_CLK_VPU_DEC_ROOT 210 +#define IMX8MM_CLK_SDMA1_ROOT 211 +#define IMX8MM_CLK_SDMA2_ROOT 212 +#define IMX8MM_CLK_SDMA3_ROOT 213 +#define IMX8MM_CLK_GPT_3M 214 +#define IMX8MM_CLK_ARM 215 +#define IMX8MM_CLK_PDM_IPG 216 +#define IMX8MM_CLK_GPU2D_ROOT 217 +#define IMX8MM_CLK_MU_ROOT 218 +#define IMX8MM_CLK_CSI1_ROOT 219 + +#define IMX8MM_CLK_DRAM_CORE 220 +#define IMX8MM_CLK_DRAM_ALT_ROOT 221 + +#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 + +#define IMX8MM_CLK_SIM_HSIO 223 + +#define IMX8MM_CLK_END 224 -#define IMX8MM_CLK_END 457 #endif |