diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/cmp.h | 18 | ||||
| -rw-r--r-- | include/asm-mips/cpu.h | 7 | ||||
| -rw-r--r-- | include/asm-mips/gcmpregs.h | 117 | ||||
| -rw-r--r-- | include/asm-mips/gic.h | 487 | ||||
| -rw-r--r-- | include/asm-mips/mips-boards/launch.h | 35 | ||||
| -rw-r--r-- | include/asm-mips/mips-boards/malta.h | 23 | ||||
| -rw-r--r-- | include/asm-mips/mips-boards/maltaint.h | 27 | ||||
| -rw-r--r-- | include/asm-mips/mips-boards/maltasmp.h | 36 | ||||
| -rw-r--r-- | include/asm-mips/mipsmtregs.h | 8 | ||||
| -rw-r--r-- | include/asm-mips/r4k-timer.h | 30 | ||||
| -rw-r--r-- | include/asm-mips/smp-ops.h | 1 | ||||
| -rw-r--r-- | include/asm-mips/smtc.h | 1 | ||||
| -rw-r--r-- | include/asm-mips/smvp.h | 19 |
13 files changed, 802 insertions, 7 deletions
diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h new file mode 100644 index 000000000000..89a73fb93ae6 --- /dev/null +++ b/include/asm-mips/cmp.h @@ -0,0 +1,18 @@ +#ifndef _ASM_CMP_H +#define _ASM_CMP_H + +/* + * Definitions for CMP multitasking on MIPS cores + */ +struct task_struct; + +extern void cmp_smp_setup(void); +extern void cmp_smp_finish(void); +extern void cmp_boot_secondary(int cpu, struct task_struct *t); +extern void cmp_init_secondary(void); +extern void cmp_cpus_done(void); +extern void cmp_prepare_cpus(unsigned int max_cpus); + +/* This is platform specific */ +extern void cmp_send_ipi(int cpu, unsigned int action); +#endif /* _ASM_CMP_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index bf5bbc78a9f7..6d04ea912254 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,7 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_1004K 0x9900 #define PRID_IMP_LOONGSON1 0x4200 #define PRID_IMP_LOONGSON2 0x6300 @@ -194,9 +195,9 @@ enum cpu_type_enum { /* * MIPS32 class processors */ - CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, - CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550, - CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, + CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, + CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h new file mode 100644 index 000000000000..d74a8a4ca861 --- /dev/null +++ b/include/asm-mips/gcmpregs.h @@ -0,0 +1,117 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * + * Multiprocessor Subsystem Register Definitions + * + */ +#ifndef _ASM_GCMPREGS_H +#define _ASM_GCMPREGS_H + + +/* Offsets to major blocks within GCMP from GCMP base */ +#define GCMP_GCB_OFS 0x0000 /* Global Control Block */ +#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ +#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ +#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ + +/* Offsets to individual GCMP registers from GCMP base */ +#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) + +#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) +#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) +#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) +#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) + +/* GCMP register access */ +#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) +#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) +#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) +#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) + +/* Mask generation */ +#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) +#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) +#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) +#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) + +/* GCB registers */ +#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ +#define GCMP_GCB_GC_NUMIOCU_SHF 8 +#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) +#define GCMP_GCB_GC_NUMCORES_SHF 0 +#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) +#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ +#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 +#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) +#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 +#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) +#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 +#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 +#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ +#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ +#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 +#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) +#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ +#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ +#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ +#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 +#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) +#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 +#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) +#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ +#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ +#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 +#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) +#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ +#define GCMP_GCB_GICBA_BASE_SHF 17 +#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) +#define GCMP_GCB_GICBA_EN_SHF 0 +#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) + +/* GCB Regions */ +#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ +#define GCMP_GCB_CMxBASE_BASE_SHF 16 +#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) +#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ +#define GCMP_GCB_CMxMASK_MASK_SHF 16 +#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) +#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 +#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) +#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 +#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 +#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 +#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 + + +/* Core local/Core other control block registers */ +#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ +#define GCMP_CCB_RESETR_INRESET_SHF 0 +#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) +#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ +#define GCMP_CCB_COHCTL_DOMAIN_SHF 0 +#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) +#define GCMP_CCB_CFG_OFS 0x0010 /* Config */ +#define GCMP_CCB_CFG_IOCUTYPE_SHF 10 +#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) +#define GCMP_CCB_CFG_IOCUTYPE_CPU 0 +#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 +#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 +#define GCMP_CCB_CFG_NUMVPE_SHF 0 +#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) +#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ +#define GCMP_CCB_OTHER_CORENUM_SHF 16 +#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) +#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ +#define GCMP_CCB_RESETBASE_BEV_SHF 12 +#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) +#define GCMP_CCB_ID_OFS 0x0028 /* Identification */ +#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ +#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ + +#endif /* _ASM_GCMPREGS_H */ diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h new file mode 100644 index 000000000000..01b2f92dc33d --- /dev/null +++ b/include/asm-mips/gic.h @@ -0,0 +1,487 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * + * GIC Register Definitions + * + */ +#ifndef _ASM_GICREGS_H +#define _ASM_GICREGS_H + +#undef GICISBYTELITTLEENDIAN +#define GICISWORDLITTLEENDIAN + +/* Constants */ +#define GIC_POL_POS 1 +#define GIC_POL_NEG 0 +#define GIC_TRIG_EDGE 1 +#define GIC_TRIG_LEVEL 0 + +#define GIC_NUM_INTRS 32 + +#define MSK(n) ((1 << (n)) - 1) +#define REG32(addr) (*(volatile unsigned int *) (addr)) +#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) +#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) + +/* Accessors */ +#define GIC_REG(segment, offset) \ + REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS) +#define GIC_REG_ADDR(segment, offset) \ + REG32(_gic_base + segment##_##SECTION_OFS + offset) + +#define GIC_ABS_REG(segment, offset) \ + (_gic_base + segment##_##SECTION_OFS + offset##_##OFS) +#define GIC_REG_ABS_ADDR(segment, offset) \ + (_gic_base + segment##_##SECTION_OFS + offset) + +#ifdef GICISBYTELITTLEENDIAN +#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data) +#define GICWRITE(reg, data) (reg) = cpu_to_le32(data) +#define GICBIS(reg, bits) \ + ({unsigned int data; \ + GICREAD(reg, data); \ + data |= bits; \ + GICWRITE(reg, data); \ + }) + +#else +#define GICREAD(reg, data) (data) = (reg) +#define GICWRITE(reg, data) (reg) = (data) +#define GICBIS(reg, bits) (reg) |= (bits) +#endif + + +/* GIC Address Space */ +#define SHARED_SECTION_OFS 0x0000 +#define SHARED_SECTION_SIZE 0x8000 +#define VPE_LOCAL_SECTION_OFS 0x8000 +#define VPE_LOCAL_SECTION_SIZE 0x4000 +#define VPE_OTHER_SECTION_OFS 0xc000 +#define VPE_OTHER_SECTION_SIZE 0x4000 +#define USM_VISIBLE_SECTION_OFS 0x10000 +#define USM_VISIBLE_SECTION_SIZE 0x10000 + +/* Register Map for Shared Section */ +#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) + +#define GIC_SH_CONFIG_OFS 0x0000 + +/* Shared Global Counter */ +#define GIC_SH_COUNTER_31_00_OFS 0x0010 +#define GIC_SH_COUNTER_63_32_OFS 0x0014 + +/* Interrupt Polarity */ +#define GIC_SH_POL_31_0_OFS 0x0100 +#define GIC_SH_POL_63_32_OFS 0x0104 +#define GIC_SH_POL_95_64_OFS 0x0108 +#define GIC_SH_POL_127_96_OFS 0x010c +#define GIC_SH_POL_159_128_OFS 0x0110 +#define GIC_SH_POL_191_160_OFS 0x0114 +#define GIC_SH_POL_223_192_OFS 0x0118 +#define GIC_SH_POL_255_224_OFS 0x011c + +/* Edge/Level Triggering */ +#define GIC_SH_TRIG_31_0_OFS 0x0180 +#define GIC_SH_TRIG_63_32_OFS 0x0184 +#define GIC_SH_TRIG_95_64_OFS 0x0188 +#define GIC_SH_TRIG_127_96_OFS 0x018c +#define GIC_SH_TRIG_159_128_OFS 0x0190 +#define GIC_SH_TRIG_191_160_OFS 0x0194 +#define GIC_SH_TRIG_223_192_OFS 0x0198 +#define GIC_SH_TRIG_255_224_OFS 0x019c + +/* Dual Edge Triggering */ +#define GIC_SH_DUAL_31_0_OFS 0x0200 +#define GIC_SH_DUAL_63_32_OFS 0x0204 +#define GIC_SH_DUAL_95_64_OFS 0x0208 +#define GIC_SH_DUAL_127_96_OFS 0x020c +#define GIC_SH_DUAL_159_128_OFS 0x0210 +#define GIC_SH_DUAL_191_160_OFS 0x0214 +#define GIC_SH_DUAL_223_192_OFS 0x0218 +#define GIC_SH_DUAL_255_224_OFS 0x021c + +/* Set/Clear corresponding bit in Edge Detect Register */ +#define GIC_SH_WEDGE_OFS 0x0280 + +/* Reset Mask - Disables Interrupt */ +#define GIC_SH_RMASK_31_0_OFS 0x0300 +#define GIC_SH_RMASK_63_32_OFS 0x0304 +#define GIC_SH_RMASK_95_64_OFS 0x0308 +#define GIC_SH_RMASK_127_96_OFS 0x030c +#define GIC_SH_RMASK_159_128_OFS 0x0310 +#define GIC_SH_RMASK_191_160_OFS 0x0314 +#define GIC_SH_RMASK_223_192_OFS 0x0318 +#define GIC_SH_RMASK_255_224_OFS 0x031c + +/* Set Mask (WO) - Enables Interrupt */ +#define GIC_SH_SMASK_31_0_OFS 0x0380 +#define GIC_SH_SMASK_63_32_OFS 0x0384 +#define GIC_SH_SMASK_95_64_OFS 0x0388 +#define GIC_SH_SMASK_127_96_OFS 0x038c +#define GIC_SH_SMASK_159_128_OFS 0x0390 +#define GIC_SH_SMASK_191_160_OFS 0x0394 +#define GIC_SH_SMASK_223_192_OFS 0x0398 +#define GIC_SH_SMASK_255_224_OFS 0x039c + +/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ +#define GIC_SH_MASK_31_0_OFS 0x0400 +#define GIC_SH_MASK_63_32_OFS 0x0404 +#define GIC_SH_MASK_95_64_OFS 0x0408 +#define GIC_SH_MASK_127_96_OFS 0x040c +#define GIC_SH_MASK_159_128_OFS 0x0410 +#define GIC_SH_MASK_191_160_OFS 0x0414 +#define GIC_SH_MASK_223_192_OFS 0x0418 +#define GIC_SH_MASK_255_224_OFS 0x041c + +/* Pending Global Interrupts (RO) */ +#define GIC_SH_PEND_31_0_OFS 0x0480 +#define GIC_SH_PEND_63_32_OFS 0x0484 +#define GIC_SH_PEND_95_64_OFS 0x0488 +#define GIC_SH_PEND_127_96_OFS 0x048c +#define GIC_SH_PEND_159_128_OFS 0x0490 +#define GIC_SH_PEND_191_160_OFS 0x0494 +#define GIC_SH_PEND_223_192_OFS 0x0498 +#define GIC_SH_PEND_255_224_OFS 0x049c + +#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 + +/* Maps Interrupt X to a Pin */ +#define GIC_SH_MAP_TO_PIN(intr) \ + (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) + +#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 + +/* Maps Interrupt X to a VPE */ +#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ + (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) +#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) + +/* Polarity : Reset Value is always 0 */ +#define GIC_SH_SET_POLARITY_OFS 0x0100 +#define GIC_SET_POLARITY(intr, pol) \ + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) + +/* Triggering : Reset Value is always 0 */ +#define GIC_SH_SET_TRIGGER_OFS 0x0180 +#define GIC_SET_TRIGGER(intr, trig) \ + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) + +/* Mask manipulation */ +#define GIC_SH_SMASK_OFS 0x0380 +#define GIC_SET_INTR_MASK(intr, val) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) + +#define GIC_SH_RMASK_OFS 0x0300 +#define GIC_CLR_INTR_MASK(intr, val) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) + +/* Register Map for Local Section */ +#define GIC_VPE_CTL_OFS 0x0000 +#define GIC_VPE_PEND_OFS 0x0004 +#define GIC_VPE_MASK_OFS 0x0008 +#define GIC_VPE_RMASK_OFS 0x000c +#define GIC_VPE_SMASK_OFS 0x0010 +#define GIC_VPE_WD_MAP_OFS 0x0040 +#define GIC_VPE_COMPARE_MAP_OFS 0x0044 +#define GIC_VPE_TIMER_MAP_OFS 0x0048 +#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 +#define GIC_VPE_SWINT0_MAP_OFS 0x0054 +#define GIC_VPE_SWINT1_MAP_OFS 0x0058 +#define GIC_VPE_OTHER_ADDR_OFS 0x0080 +#define GIC_VPE_WD_CONFIG0_OFS 0x0090 +#define GIC_VPE_WD_COUNT0_OFS 0x0094 +#define GIC_VPE_WD_INITIAL0_OFS 0x0098 +#define GIC_VPE_COMPARE_LO_OFS 0x00a0 +#define GIC_VPE_COMPARE_HI 0x00a4 + +#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 +#define GIC_VPE_EIC_SS(intr) \ + (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) + +#define GIC_VPE_EIC_VEC_BASE 0x0800 +#define GIC_VPE_EIC_VEC(intr) \ + (GIC_VPE_EIC_VEC_BASE + (4 * intr)) + +#define GIC_VPE_TENABLE_NMI_OFS 0x1000 +#define GIC_VPE_TENABLE_YQ_OFS 0x1004 +#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 +#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 + +/* User Mode Visible Section Register Map */ +#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 +#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 + +#else /* CONFIG_CPU_BIG_ENDIAN */ + +#define GIC_SH_CONFIG_OFS 0x0000 + +/* Shared Global Counter */ +#define GIC_SH_COUNTER_31_00_OFS 0x0014 +#define GIC_SH_COUNTER_63_32_OFS 0x0010 + +/* Interrupt Polarity */ +#define GIC_SH_POL_31_0_OFS 0x0104 +#define GIC_SH_POL_63_32_OFS 0x0100 +#define GIC_SH_POL_95_64_OFS 0x010c +#define GIC_SH_POL_127_96_OFS 0x0108 +#define GIC_SH_POL_159_128_OFS 0x0114 +#define GIC_SH_POL_191_160_OFS 0x0110 +#define GIC_SH_POL_223_192_OFS 0x011c +#define GIC_SH_POL_255_224_OFS 0x0118 + +/* Edge/Level Triggering */ +#define GIC_SH_TRIG_31_0_OFS 0x0184 +#define GIC_SH_TRIG_63_32_OFS 0x0180 +#define GIC_SH_TRIG_95_64_OFS 0x018c +#define GIC_SH_TRIG_127_96_OFS 0x0188 +#define GIC_SH_TRIG_159_128_OFS 0x0194 +#define GIC_SH_TRIG_191_160_OFS 0x0190 +#define GIC_SH_TRIG_223_192_OFS 0x019c +#define GIC_SH_TRIG_255_224_OFS 0x0198 + +/* Dual Edge Triggering */ +#define GIC_SH_DUAL_31_0_OFS 0x0204 +#define GIC_SH_DUAL_63_32_OFS 0x0200 +#define GIC_SH_DUAL_95_64_OFS 0x020c +#define GIC_SH_DUAL_127_96_OFS 0x0208 +#define GIC_SH_DUAL_159_128_OFS 0x0214 +#define GIC_SH_DUAL_191_160_OFS 0x0210 +#define GIC_SH_DUAL_223_192_OFS 0x021c +#define GIC_SH_DUAL_255_224_OFS 0x0218 + +/* Set/Clear corresponding bit in Edge Detect Register */ +#define GIC_SH_WEDGE_OFS 0x0280 + +/* Reset Mask - Disables Interrupt */ +#define GIC_SH_RMASK_31_0_OFS 0x0304 +#define GIC_SH_RMASK_63_32_OFS 0x0300 +#define GIC_SH_RMASK_95_64_OFS 0x030c +#define GIC_SH_RMASK_127_96_OFS 0x0308 +#define GIC_SH_RMASK_159_128_OFS 0x0314 +#define GIC_SH_RMASK_191_160_OFS 0x0310 +#define GIC_SH_RMASK_223_192_OFS 0x031c +#define GIC_SH_RMASK_255_224_OFS 0x0318 + +/* Set Mask (WO) - Enables Interrupt */ +#define GIC_SH_SMASK_31_0_OFS 0x0384 +#define GIC_SH_SMASK_63_32_OFS 0x0380 +#define GIC_SH_SMASK_95_64_OFS 0x038c +#define GIC_SH_SMASK_127_96_OFS 0x0388 +#define GIC_SH_SMASK_159_128_OFS 0x0394 +#define GIC_SH_SMASK_191_160_OFS 0x0390 +#define GIC_SH_SMASK_223_192_OFS 0x039c +#define GIC_SH_SMASK_255_224_OFS 0x0398 + +/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ +#define GIC_SH_MASK_31_0_OFS 0x0404 +#define GIC_SH_MASK_63_32_OFS 0x0400 +#define GIC_SH_MASK_95_64_OFS 0x040c +#define GIC_SH_MASK_127_96_OFS 0x0408 +#define GIC_SH_MASK_159_128_OFS 0x0414 +#define GIC_SH_MASK_191_160_OFS 0x0410 +#define GIC_SH_MASK_223_192_OFS 0x041c +#define GIC_SH_MASK_255_224_OFS 0x0418 + +/* Pending Global Interrupts (RO) */ +#define GIC_SH_PEND_31_0_OFS 0x0484 +#define GIC_SH_PEND_63_32_OFS 0x0480 +#define GIC_SH_PEND_95_64_OFS 0x048c +#define GIC_SH_PEND_127_96_OFS 0x0488 +#define GIC_SH_PEND_159_128_OFS 0x0494 +#define GIC_SH_PEND_191_160_OFS 0x0490 +#define GIC_SH_PEND_223_192_OFS 0x049c +#define GIC_SH_PEND_255_224_OFS 0x0498 + +#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 + +/* Maps Interrupt X to a Pin */ +#define GIC_SH_MAP_TO_PIN(intr) \ + (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) + +#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 + +/* + * Maps Interrupt X to a VPE. This is more complex than the LE case, as + * odd and even registers need to be transposed. It does work - trust me! + */ +#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ + (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ + (((((vpe) / 32) ^ 1) - 1) * 4)) +#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) + +/* Polarity */ +#define GIC_SH_SET_POLARITY_OFS 0x0100 +#define GIC_SET_POLARITY(intr, pol) \ + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) + +/* Triggering */ +#define GIC_SH_SET_TRIGGER_OFS 0x0180 +#define GIC_SET_TRIGGER(intr, trig) \ + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) + +/* Mask manipulation */ +#define GIC_SH_SMASK_OFS 0x0380 +#define GIC_SET_INTR_MASK(intr, val) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) + +#define GIC_SH_RMASK_OFS 0x0300 +#define GIC_CLR_INTR_MASK(intr, val) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)) + +/* Register Map for Local Section */ +#define GIC_VPE_CTL_OFS 0x0000 +#define GIC_VPE_PEND_OFS 0x0004 +#define GIC_VPE_MASK_OFS 0x0008 +#define GIC_VPE_RMASK_OFS 0x000c +#define GIC_VPE_SMASK_OFS 0x0010 +#define GIC_VPE_WD_MAP_OFS 0x0040 +#define GIC_VPE_COMPARE_MAP_OFS 0x0044 +#define GIC_VPE_TIMER_MAP_OFS 0x0048 +#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 +#define GIC_VPE_SWINT0_MAP_OFS 0x0054 +#define GIC_VPE_SWINT1_MAP_OFS 0x0058 +#define GIC_VPE_OTHER_ADDR_OFS 0x0080 +#define GIC_VPE_WD_CONFIG0_OFS 0x0090 +#define GIC_VPE_WD_COUNT0_OFS 0x0094 +#define GIC_VPE_WD_INITIAL0_OFS 0x0098 +#define GIC_VPE_COMPARE_LO_OFS 0x00a4 +#define GIC_VPE_COMPARE_HI_OFS 0x00a0 + +#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 +#define GIC_VPE_EIC_SS(intr) \ + (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) + +#define GIC_VPE_EIC_VEC_BASE 0x0800 +#define GIC_VPE_EIC_VEC(intr) \ + (GIC_VPE_EIC_VEC_BASE + (4 * intr)) + +#define GIC_VPE_TENABLE_NMI_OFS 0x1000 +#define GIC_VPE_TENABLE_YQ_OFS 0x1004 +#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 +#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 + +/* User Mode Visible Section Register Map */ +#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 +#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 + +#endif /* !LE */ + +/* Masks */ +#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 +#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) + +#define GIC_SH_CONFIG_COUNTBITS_SHF 24 +#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) + +#define GIC_SH_CONFIG_NUMINTRS_SHF 16 +#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) + +#define GIC_SH_CONFIG_NUMVPES_SHF 0 +#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF) + +#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31)) +#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31)) + +#define GIC_MAP_TO_PIN_SHF 31 +#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) +#define GIC_MAP_TO_NMI_SHF 30 +#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) +#define GIC_MAP_TO_YQ_SHF 29 +#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) +#define GIC_MAP_SHF 0 +#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) + +/* GIC_VPE_CTL Masks */ +#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 +#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) +#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 +#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF) +#define GIC_VPE_CTL_EIC_MODE_SHF 0 +#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) + +/* GIC_VPE_PEND Masks */ +#define GIC_VPE_PEND_WD_SHF 0 +#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF) +#define GIC_VPE_PEND_CMP_SHF 1 +#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF) +#define GIC_VPE_PEND_TIMER_SHF 2 +#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF) +#define GIC_VPE_PEND_PERFCOUNT_SHF 3 +#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF) +#define GIC_VPE_PEND_SWINT0_SHF 4 +#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) +#define GIC_VPE_PEND_SWINT1_SHF 5 +#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) + +/* GIC_VPE_RMASK Masks */ +#define GIC_VPE_RMASK_WD_SHF 0 +#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF) +#define GIC_VPE_RMASK_CMP_SHF 1 +#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF) +#define GIC_VPE_RMASK_TIMER_SHF 2 +#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF) +#define GIC_VPE_RMASK_PERFCNT_SHF 3 +#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF) +#define GIC_VPE_RMASK_SWINT0_SHF 4 +#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) +#define GIC_VPE_RMASK_SWINT1_SHF 5 +#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) + +/* GIC_VPE_SMASK Masks */ +#define GIC_VPE_SMASK_WD_SHF 0 +#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF) +#define GIC_VPE_SMASK_CMP_SHF 1 +#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF) +#define GIC_VPE_SMASK_TIMER_SHF 2 +#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF) +#define GIC_VPE_SMASK_PERFCNT_SHF 3 +#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF) +#define GIC_VPE_SMASK_SWINT0_SHF 4 +#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) +#define GIC_VPE_SMASK_SWINT1_SHF 5 +#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) + +/* + * Set the Mapping of Interrupt X to a VPE. + */ +#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \ + GIC_SH_MAP_TO_VPE_REG_BIT(vpe)) + +struct gic_pcpu_mask { + DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS); +}; + +struct gic_pending_regs { + DECLARE_BITMAP(pending, GIC_NUM_INTRS); +}; + +struct gic_intrmask_regs { + DECLARE_BITMAP(intrmask, GIC_NUM_INTRS); +}; + +/* + * Interrupt Meta-data specification. The ipiflag helps + * in building ipi_map. + */ +struct gic_intr_map { + unsigned int intrnum; /* Ext Intr Num */ + unsigned int cpunum; /* Directed to this CPU */ + unsigned int pin; /* Directed to this Pin */ + unsigned int polarity; /* Polarity : +/- */ + unsigned int trigtype; /* Trigger : Edge/Levl */ + unsigned int ipiflag; /* Is used for IPI ? */ +}; + +extern void gic_init(unsigned long gic_base_addr, + unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, + unsigned int intrmap_size, unsigned int irqbase); + +extern unsigned int gic_get_int(void); +extern void gic_send_ipi(unsigned int intr); + +#endif /* _ASM_GICREGS_H */ diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h new file mode 100644 index 000000000000..d8ae7f95a522 --- /dev/null +++ b/include/asm-mips/mips-boards/launch.h @@ -0,0 +1,35 @@ +/* + * + */ + +#ifndef _ASSEMBLER_ + +struct cpulaunch { + unsigned long pc; + unsigned long gp; + unsigned long sp; + unsigned long a0; + unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */ + unsigned long flags; +}; + +#else + +#define LOG2CPULAUNCH 5 +#define LAUNCH_PC 0 +#define LAUNCH_GP 4 +#define LAUNCH_SP 8 +#define LAUNCH_A0 12 +#define LAUNCH_FLAGS 28 + +#endif + +#define LAUNCH_FREADY 1 +#define LAUNCH_FGO 2 +#define LAUNCH_FGONE 4 + +#define CPULAUNCH 0x00000f00 +#define NCPULAUNCH 8 + +/* Polling period in count cycles for secondary CPU's */ +#define LAUNCHPERIOD 10000 diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index 93bf4e51b8a4..c1891578fa65 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h @@ -52,6 +52,29 @@ static inline unsigned long get_msc_port_base(unsigned long reg) } /* + * GCMP Specific definitions + */ +#define GCMP_BASE_ADDR 0x1fbf8000 +#define GCMP_ADDRSPACE_SZ (256 * 1024) + +/* + * GIC Specific definitions + */ +#define GIC_BASE_ADDR 0x1bdc0000 +#define GIC_ADDRSPACE_SZ (128 * 1024) + +/* + * MSC01 BIU Specific definitions + * FIXME : These should be elsewhere ? + */ +#define MSC01_BIU_REG_BASE 0x1bc80000 +#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024) +#define MSC01_SC_CFG_OFS 0x0110 +#define MSC01_SC_CFG_GICPRES_MSK 0x00000004 +#define MSC01_SC_CFG_GICPRES_SHF 2 +#define MSC01_SC_CFG_GICENA_SHF 3 + +/* * Malta RTC-device indirect register access. */ #define MALTA_RTC_ADR_REG 0x70 diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 7461318f1cd1..cea872fc6f5c 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h @@ -39,7 +39,9 @@ #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 #define MIPSCPU_INT_MB1 3 #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 +#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ #define MIPSCPU_INT_MB2 4 +#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ #define MIPSCPU_INT_MB3 5 #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 #define MIPSCPU_INT_MB4 6 @@ -76,6 +78,31 @@ #define MSC01E_INT_PERFCTR 10 #define MSC01E_INT_CPUCTR 11 +/* GIC's Nomenclature for Core Interrupt Pins on the Malta */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ + +#define GIC_EXT_INTR(x) x + +/* Dummy data */ +#define X 0xdead + +/* External Interrupts used for IPI */ +#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 +#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 +#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18 +#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19 +#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20 +#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21 +#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 +#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 + +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) + #ifndef __ASSEMBLY__ extern void maltaint_init(void); #endif diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h new file mode 100644 index 000000000000..8d7e955d506e --- /dev/null +++ b/include/asm-mips/mips-boards/maltasmp.h @@ -0,0 +1,36 @@ +/* + * There are several SMP models supported + * SMTC is mutually exclusive to other options (atm) + */ +#if defined(CONFIG_MIPS_MT_SMTC) +#define malta_smtc 1 +#define malta_cmp 0 +#define malta_smvp 0 +#else +#define malta_smtc 0 +#if defined(CONFIG_MIPS_CMP) +extern int gcmp_present; +#define malta_cmp gcmp_present +#else +#define malta_cmp 0 +#endif +/* FIXME: should become COMFIG_MIPS_MT_SMVP */ +#if defined(CONFIG_MIPS_MT_SMP) +#define malta_smvp 1 +#else +#define malta_smvp 0 +#endif +#endif + +#include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> + +/* malta_smtc */ +#include <asm/smtc.h> +#include <asm/smtc_ipi.h> + +/* malta_cmp */ +#include <asm/cmp.h> + +/* malta_smvp */ +#include <asm/smvp.h> diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 5a2f8a3a6a1f..c9420aa97e32 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -197,8 +197,8 @@ static inline void __raw_evpe(void) " .set pop \n"); } -/* Enable multiMT if previous suggested it should be. - EMT_ENABLE to force */ +/* Enable virtual processor execution if previous suggested it should be. + EVPE_ENABLE to force */ #define EVPE_ENABLE MVPCONTROL_EVP @@ -238,8 +238,8 @@ static inline void __raw_emt(void) " .set reorder"); } -/* enable multiVPE if previous suggested it should be. - EVPE_ENABLE to force */ +/* enable multi-threaded execution if previous suggested it should be. + EMT_ENABLE to force */ #define EMT_ENABLE VPECONTROL_TE diff --git a/include/asm-mips/r4k-timer.h b/include/asm-mips/r4k-timer.h new file mode 100644 index 000000000000..a37d12b3b61c --- /dev/null +++ b/include/asm-mips/r4k-timer.h @@ -0,0 +1,30 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_R4K_TYPES_H +#define __ASM_R4K_TYPES_H + +#include <linux/compiler.h> + +#ifdef CONFIG_SYNC_R4K + +extern void synchronise_count_master(void); +extern void synchronise_count_slave(void); + +#else + +static inline void synchronise_count_master(void) +{ +} + +static inline void synchronise_count_slave(void) +{ +} + +#endif + +#endif /* __ASM_R4K_TYPES_H */ diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h index b17fdfb5d818..43c207e72a63 100644 --- a/include/asm-mips/smp-ops.h +++ b/include/asm-mips/smp-ops.h @@ -51,6 +51,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops) #endif /* !CONFIG_SMP */ extern struct plat_smp_ops up_smp_ops; +extern struct plat_smp_ops cmp_smp_ops; extern struct plat_smp_ops vsmp_smp_ops; #endif /* __ASM_SMP_OPS_H */ diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index ff3e8936b493..3639b28f80db 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h @@ -44,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot); extern void mipsmt_prepare_cpus(void); extern void smtc_smp_finish(void); extern void smtc_boot_secondary(int cpu, struct task_struct *t); +extern void smtc_cpus_done(void); /* * Sharing the TLB between multiple VPEs means that the diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h new file mode 100644 index 000000000000..0d0e80a39e8a --- /dev/null +++ b/include/asm-mips/smvp.h @@ -0,0 +1,19 @@ +#ifndef _ASM_SMVP_H +#define _ASM_SMVP_H + +/* + * Definitions for SMVP multitasking on MIPS MT cores + */ +struct task_struct; + +extern void smvp_smp_setup(void); +extern void smvp_smp_finish(void); +extern void smvp_boot_secondary(int cpu, struct task_struct *t); +extern void smvp_init_secondary(void); +extern void smvp_smp_finish(void); +extern void smvp_cpus_done(void); +extern void smvp_prepare_cpus(unsigned int max_cpus); + +/* This is platform specific */ +extern void smvp_send_ipi(int cpu, unsigned int action); +#endif /* _ASM_SMVP_H */ |