diff options
Diffstat (limited to 'include')
130 files changed, 2265 insertions, 1286 deletions
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h new file mode 100644 index 000000000000..81a8937486cb --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h @@ -0,0 +1,18 @@ +#ifndef __ASM_ARCH_PXA3XX_NAND_H +#define __ASM_ARCH_PXA3XX_NAND_H + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +struct pxa3xx_nand_platform_data { + + /* the data flash bus is shared between the Static Memory + * Controller and the Data Flash Controller, the arbiter + * controls the ownership of the bus + */ + int enable_arbiter; + + struct mtd_partition *parts; + unsigned int nr_parts; +}; +#endif /* __ASM_ARCH_PXA3XX_NAND_H */ diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h index 8816f7f9cee1..ad6bbe90616e 100644 --- a/include/asm-arm/plat-s3c/nand.h +++ b/include/asm-arm/plat-s3c/nand.h @@ -22,11 +22,14 @@ */ struct s3c2410_nand_set { + unsigned int disable_ecc : 1; + int nr_chips; int nr_partitions; char *name; int *nr_map; struct mtd_partition *partitions; + struct nand_ecclayout *ecc_layout; }; struct s3c2410_platform_nand { @@ -36,6 +39,8 @@ struct s3c2410_platform_nand { int twrph0; /* active time for nWE/nOE */ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ + unsigned int ignore_unset_ecc : 1; + int nr_sets; struct s3c2410_nand_set *sets; diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore new file mode 100644 index 000000000000..7858564a4466 --- /dev/null +++ b/include/asm-blackfin/.gitignore @@ -0,0 +1 @@ ++mach diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 5dba3a735596..716df7c85923 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -112,20 +112,10 @@ extern void init_leds(void); extern const char bfin_board_name[]; extern unsigned long wall_jiffies; -extern unsigned long ipdt_table[]; -extern unsigned long dpdt_table[]; -extern unsigned long icplb_table[]; -extern unsigned long dcplb_table[]; - -extern unsigned long ipdt_swapcount_table[]; -extern unsigned long dpdt_swapcount_table[]; - -extern unsigned long table_start, table_end; extern unsigned long bfin_sic_iwr[]; extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ extern struct file_operations dpmc_fops; -extern char _start; extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h index 41e53b29f167..6d3e11b1fc57 100644 --- a/include/asm-blackfin/bug.h +++ b/include/asm-blackfin/bug.h @@ -1,4 +1,17 @@ #ifndef _BLACKFIN_BUG_H #define _BLACKFIN_BUG_H + +#ifdef CONFIG_BUG +#define HAVE_ARCH_BUG + +#define BUG() do { \ + dump_bfin_trace_buffer(); \ + printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ + panic("BUG!"); \ +} while (0) + +#endif + #include <asm-generic/bug.h> + #endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 654375c2b746..5b0da9a69b67 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -74,32 +74,6 @@ #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* possibly 1 for L2 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ - + ASYNC_MEMORY_CPLB_COVERAGE) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* possibly 1 for L2 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) - - #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h index 282fabccf6a6..1a13c2fc3667 100644 --- a/include/asm-blackfin/dma-mapping.h +++ b/include/asm-blackfin/dma-mapping.h @@ -27,6 +27,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction); +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + return dma_map_single(dev, page_address(page) + offset, size, dir); +} + /* * Unmap a single streaming mode DMA translation. The dma_addr and size * must match what was provided for in a previous pci_map_single call. All @@ -38,6 +46,13 @@ extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction); +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction dir) +{ + dma_unmap_single(dev, dma_addr, size, dir); +} + /* * Map a set of buffers described by scatterlist in streaming * mode for DMA. This is the scather-gather version of the diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h index 16d493574ba8..c0d5259e315b 100644 --- a/include/asm-blackfin/dma.h +++ b/include/asm-blackfin/dma.h @@ -191,4 +191,7 @@ void clear_dma_irqstat(unsigned int channel); void *dma_memcpy(void *dest, const void *src, size_t count); void *safe_dma_memcpy(void *dest, const void *src, size_t count); +extern int channel2irq(unsigned int channel); +extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL]; + #endif diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h index 4f318f1fd2d9..0520d2aac8f3 100644 --- a/include/asm-blackfin/gptimers.h +++ b/include/asm-blackfin/gptimers.h @@ -22,6 +22,18 @@ # define TIMER0_GROUP_REG TIMER_ENABLE #endif /* + * BF54x: 11 timers (BF542: 8 timers): + */ +#if defined(BF548_FAMILY) +# ifdef CONFIG_BF542 +# define MAX_BLACKFIN_GPTIMERS 8 +# else +# define MAX_BLACKFIN_GPTIMERS 11 +# define TIMER8_GROUP_REG TIMER_ENABLE1 +# endif +# define TIMER0_GROUP_REG TIMER_ENABLE0 +#endif +/* * BF561: 12 timers: */ #if defined(CONFIG_BF561) @@ -44,40 +56,28 @@ #define TIMER0bit 0x0001 /* 0001b */ #define TIMER1bit 0x0002 /* 0010b */ #define TIMER2bit 0x0004 /* 0100b */ - -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER3bit 0x0008 -# define TIMER4bit 0x0010 -# define TIMER5bit 0x0020 -# define TIMER6bit 0x0040 -# define TIMER7bit 0x0080 -#endif - -#if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER8bit 0x0100 -# define TIMER9bit 0x0200 -# define TIMER10bit 0x0400 -# define TIMER11bit 0x0800 -#endif +#define TIMER3bit 0x0008 +#define TIMER4bit 0x0010 +#define TIMER5bit 0x0020 +#define TIMER6bit 0x0040 +#define TIMER7bit 0x0080 +#define TIMER8bit 0x0100 +#define TIMER9bit 0x0200 +#define TIMER10bit 0x0400 +#define TIMER11bit 0x0800 #define TIMER0_id 0 #define TIMER1_id 1 #define TIMER2_id 2 - -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER3_id 3 -# define TIMER4_id 4 -# define TIMER5_id 5 -# define TIMER6_id 6 -# define TIMER7_id 7 -#endif - -#if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER8_id 8 -# define TIMER9_id 9 -# define TIMER10_id 10 -# define TIMER11_id 11 -#endif +#define TIMER3_id 3 +#define TIMER4_id 4 +#define TIMER5_id 5 +#define TIMER6_id 6 +#define TIMER7_id 7 +#define TIMER8_id 8 +#define TIMER9_id 9 +#define TIMER10_id 10 +#define TIMER11_id 11 /* associated timers for ppi framesync: */ @@ -124,45 +124,31 @@ /* * Timer Status Register Bits */ -#define TIMER_STATUS_TIMIL0 0x0001 -#define TIMER_STATUS_TIMIL1 0x0002 -#define TIMER_STATUS_TIMIL2 0x0004 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TIMIL3 0x00000008 -# define TIMER_STATUS_TIMIL4 0x00010000 -# define TIMER_STATUS_TIMIL5 0x00020000 -# define TIMER_STATUS_TIMIL6 0x00040000 -# define TIMER_STATUS_TIMIL7 0x00080000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TIMIL8 0x0001 -# define TIMER_STATUS_TIMIL9 0x0002 -# define TIMER_STATUS_TIMIL10 0x0004 -# define TIMER_STATUS_TIMIL11 0x0008 -# endif -# define TIMER_STATUS_INTR 0x000F000F -#else -# define TIMER_STATUS_INTR 0x0007 /* any timer interrupt */ -#endif - -#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ -#define TIMER_STATUS_TOVF1 0x0020 -#define TIMER_STATUS_TOVF2 0x0040 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TOVF3 0x00000080 -# define TIMER_STATUS_TOVF4 0x00100000 -# define TIMER_STATUS_TOVF5 0x00200000 -# define TIMER_STATUS_TOVF6 0x00400000 -# define TIMER_STATUS_TOVF7 0x00800000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TOVF8 0x0010 -# define TIMER_STATUS_TOVF9 0x0020 -# define TIMER_STATUS_TOVF10 0x0040 -# define TIMER_STATUS_TOVF11 0x0080 -# endif -# define TIMER_STATUS_OFLOW 0x00F000F0 -#else -# define TIMER_STATUS_OFLOW 0x0070 /* any timer overflow */ -#endif +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL7 0x00080000 +#define TIMER_STATUS_TIMIL8 0x0001 +#define TIMER_STATUS_TIMIL9 0x0002 +#define TIMER_STATUS_TIMIL10 0x0004 +#define TIMER_STATUS_TIMIL11 0x0008 + +#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x0020 +#define TIMER_STATUS_TOVF2 0x0040 +#define TIMER_STATUS_TOVF3 0x00000080 +#define TIMER_STATUS_TOVF4 0x00100000 +#define TIMER_STATUS_TOVF5 0x00200000 +#define TIMER_STATUS_TOVF6 0x00400000 +#define TIMER_STATUS_TOVF7 0x00800000 +#define TIMER_STATUS_TOVF8 0x0010 +#define TIMER_STATUS_TOVF9 0x0020 +#define TIMER_STATUS_TOVF10 0x0040 +#define TIMER_STATUS_TOVF11 0x0080 /* * Timer Slave Enable Status : write 1 to clear @@ -170,22 +156,16 @@ #define TIMER_STATUS_TRUN0 0x1000 #define TIMER_STATUS_TRUN1 0x2000 #define TIMER_STATUS_TRUN2 0x4000 -#if (MAX_BLACKFIN_GPTIMERS > 3) -# define TIMER_STATUS_TRUN3 0x00008000 -# define TIMER_STATUS_TRUN4 0x10000000 -# define TIMER_STATUS_TRUN5 0x20000000 -# define TIMER_STATUS_TRUN6 0x40000000 -# define TIMER_STATUS_TRUN7 0x80000000 -# define TIMER_STATUS_TRUN 0xF000F000 -# if (MAX_BLACKFIN_GPTIMERS > 8) -# define TIMER_STATUS_TRUN8 0x1000 -# define TIMER_STATUS_TRUN9 0x2000 -# define TIMER_STATUS_TRUN10 0x4000 -# define TIMER_STATUS_TRUN11 0x8000 -# endif -#else -# define TIMER_STATUS_TRUN 0x7000 -#endif +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN 0xF000F000 +#define TIMER_STATUS_TRUN8 0x1000 +#define TIMER_STATUS_TRUN9 0x2000 +#define TIMER_STATUS_TRUN10 0x4000 +#define TIMER_STATUS_TRUN11 0x8000 /* The actual gptimer API */ diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index a89120445be6..735fa02fafb2 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf527/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -15,35 +15,85 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (1) -/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (1) +/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ #define ANOMALY_05000342 (1) -/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (1) +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (1) +/* Security Features Are Not Functional */ +#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* New Feature: Higher Default CCLK Rate */ +#define ANOMALY_05000368 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* Authentication Fails To Initiate */ +#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +/* Data Read From L3 Memory by USB DMA May be Corrupted */ +#define ANOMALY_05000380 (1) +/* USB Full-speed Mode not Fully Tested */ +#define ANOMALY_05000381 (1) +/* New Feature: Boot from OTP Memory */ +#define ANOMALY_05000385 (1) +/* New Feature: bfrom_SysControl() Routine */ +#define ANOMALY_05000386 (1) +/* New Feature: Programmable Preboot Settings */ +#define ANOMALY_05000387 (1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (1) +/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (1) +/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (1) +/* New Feature: Log Buffer Functionality */ +#define ANOMALY_05000394 (1) +/* New Feature: Hook Routine Functionality */ +#define ANOMALY_05000395 (1) +/* New Feature: Header Indirect Bit */ +#define ANOMALY_05000396 (1) +/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ +#define ANOMALY_05000397 (1) +/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ +#define ANOMALY_05000398 (1) +/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ +#define ANOMALY_05000399 (1) +/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ +#define ANOMALY_05000401 (1) /* Anomalies that don't exist on this proc */ -#define ANOMALY_05000323 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000198 (0) #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) -#define ANOMALY_05000273 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) -#define ANOMALY_05000230 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) + #endif diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index c0694ecd2ecd..f0ab2736a680 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h new file mode 100644 index 000000000000..0612d0c9501c --- /dev/null +++ b/include/asm-blackfin/mach-bf527/bfin_sir.h @@ -0,0 +1,133 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h index 1bd07e30781c..2891727b6176 100644 --- a/include/asm-blackfin/mach-bf527/blackfin.h +++ b/include/asm-blackfin/mach-bf527/blackfin.h @@ -64,6 +64,21 @@ #define STATUS_P1 0x02 #define STATUS_P0 0x01 +#define BFIN_UART_NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h index 3f4de5d9d4cb..9dbdbec8ea1b 100644 --- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h @@ -29,18 +29,71 @@ */ #ifndef _CDEF_BF52X_H +#define _CDEF_BF52X_H + +#include <asm/system.h> +#include <asm/blackfin.h> #include "defBF52x_base.h" +/* Include core specific register pointer definitions */ +#include <asm/mach-common/cdef_LPBlackfin.h> + /* ==== begin from cdefBF534.h ==== */ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -873,39 +926,6 @@ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) - /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h index 2dfee12864f6..49dd693223e8 100644 --- a/include/asm-blackfin/mach-bf527/dma.h +++ b/include/asm-blackfin/mach-bf527/dma.h @@ -59,7 +59,4 @@ #define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ #endif -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 98209d40abba..5a6dcc5fa36c 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -251,10 +251,18 @@ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* PPI Does Not Start Properly In Specific Mode */ +#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index b6f513bee56e..fbe88dee3e2d 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = { #define DRIVER_NAME "bfin-uart" -int nr_ports = NR_PORTS; +int nr_ports = BFIN_UART_NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h new file mode 100644 index 000000000000..cefcf8bb505b --- /dev/null +++ b/include/asm-blackfin/mach-bf533/bfin_sir.h @@ -0,0 +1,120 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART_RX, + CH_UART_RX, + CH_UART_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h index f3b240abf170..d80971b4e3aa 100644 --- a/include/asm-blackfin/mach-bf533/blackfin.h +++ b/include/asm-blackfin/mach-bf533/blackfin.h @@ -42,4 +42,19 @@ #include "cdefBF532.h" #endif +#define BFIN_UART_NR_PORTS 1 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ + #endif /* _MACH_BLACKFIN_H_ */ diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h index c803e14b529c..154655452d4c 100644 --- a/include/asm-blackfin/mach-bf533/cdefBF532.h +++ b/include/asm-blackfin/mach-bf533/cdefBF532.h @@ -43,7 +43,27 @@ /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); } /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 37134aaf9954..17e1548cec08 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h @@ -88,20 +88,25 @@ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ + +/* + * Because include/linux/serial_reg.h have defined UART_*, + * So we define blackfin uart regs to BFIN_UART_*. + */ +#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ +#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ +#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ +#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ #if 0 -#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ +#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ #endif -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ +#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index 16c672c01d80..bd9d5e94307d 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,7 +51,4 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h index 1620dae5254d..f8f31901fca9 100644 --- a/include/asm-blackfin/mach-bf533/mem_init.h +++ b/include/asm-blackfin/mach-bf533/mem_init.h @@ -29,7 +29,8 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD) #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -118,6 +119,13 @@ #define SDRAM_CL CL_3 #endif +#if (CONFIG_MEM_MT48LC32M16A2TG_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + #if (CONFIG_MEM_GENERIC_BOARD) /*SDRAM INFORMATION: Modify this for your board */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 746a794b3119..a6b08facb242 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -132,10 +132,24 @@ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) +/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ +#define ANOMALY_05000350 (__SILICON_REVISION__ < 3) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000359 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) + + /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -146,5 +160,6 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 8fc672d31057..fd100a415b98 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver header files + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h new file mode 100644 index 000000000000..0612d0c9501c --- /dev/null +++ b/include/asm-blackfin/mach-bf537/bfin_sir.h @@ -0,0 +1,133 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 53fcfa3408d0..cffc786b2a2b 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h @@ -82,8 +82,6 @@ #define STATUS_P1 0x02 #define STATUS_P0 0x01 -/* UART 0*/ - /* DMA Channnel */ #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) @@ -106,37 +104,52 @@ /* MMR Registers*/ #define bfin_read_UART_THR() bfin_read_UART0_THR() #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) -#define UART_THR UART0_THR +#define BFIN_UART_THR UART0_THR #define bfin_read_UART_RBR() bfin_read_UART0_RBR() #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) -#define UART_RBR UART0_RBR +#define BFIN_UART_RBR UART0_RBR #define bfin_read_UART_DLL() bfin_read_UART0_DLL() #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) -#define UART_DLL UART0_DLL +#define BFIN_UART_DLL UART0_DLL #define bfin_read_UART_IER() bfin_read_UART0_IER() #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) -#define UART_IER UART0_IER +#define BFIN_UART_IER UART0_IER #define bfin_read_UART_DLH() bfin_read_UART0_DLH() #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) -#define UART_DLH UART0_DLH +#define BFIN_UART_DLH UART0_DLH #define bfin_read_UART_IIR() bfin_read_UART0_IIR() #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) -#define UART_IIR UART0_IIR +#define BFIN_UART_IIR UART0_IIR #define bfin_read_UART_LCR() bfin_read_UART0_LCR() #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) -#define UART_LCR UART0_LCR +#define BFIN_UART_LCR UART0_LCR #define bfin_read_UART_MCR() bfin_read_UART0_MCR() #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) -#define UART_MCR UART0_MCR +#define BFIN_UART_MCR UART0_MCR #define bfin_read_UART_LSR() bfin_read_UART0_LSR() #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) -#define UART_LSR UART0_LSR +#define BFIN_UART_LSR UART0_LSR #define bfin_read_UART_SCR() bfin_read_UART0_SCR() #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) -#define UART_SCR UART0_SCR +#define BFIN_UART_SCR UART0_SCR #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) -#define UART_GCTL UART0_GCTL +#define BFIN_UART_GCTL UART0_GCTL + +#define BFIN_UART_NR_PORTS 2 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ /* DPMC*/ #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 78227bc855df..82de526f8097 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h @@ -44,7 +44,27 @@ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) @@ -858,39 +881,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val) +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h index 021991984e6e..7a964040870a 100644 --- a/include/asm-blackfin/mach-bf537/dma.h +++ b/include/asm-blackfin/mach-bf537/dma.h @@ -52,7 +52,4 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 850dc12eb7f2..49d3cebc5293 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -93,5 +93,6 @@ #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 7e6339f62a50..6547027cd3e6 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 4 - -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_GCTL 0x08 /* Global Control Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ -#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ -#define OFFSET_THR 0x28 /* Transmit Holding register */ -#define OFFSET_RBR 0x2C /* Receive Buffer register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) @@ -80,7 +96,7 @@ struct bfin_serial_port { #endif }; -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h new file mode 100644 index 000000000000..5e94271c7e3b --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bfin_sir.h @@ -0,0 +1,149 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v) +#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART0_RX, + CH_UART0_RX, + CH_UART0_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR1 + { + 0xFFC02000, + IRQ_UART1_RX, + CH_UART1_RX, + CH_UART1_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR2 + { + 0xFFC02100, + IRQ_UART2_RX, + CH_UART2_RX, + CH_UART2_TX, + }, +#endif +#ifdef CONFIG_BFIN_SIR3 + { + 0xFFC03100, + IRQ_UART3_RX, + CH_UART3_RX, + CH_UART3_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR2 + peripheral_request(P_UART2_TX, DRIVER_NAME); + peripheral_request(P_UART2_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_BFIN_SIR3 + peripheral_request(P_UART3_TX, DRIVER_NAME); + peripheral_request(P_UART3_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 3bd67da86053..d6ee74ac0460 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -153,17 +153,33 @@ #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) -#define UART_THR UART1_THR -#define UART_RBR UART1_RBR -#define UART_DLL UART1_DLL -#define UART_IER UART1_IER -#define UART_DLH UART1_DLH -#define UART_IIR UART1_IIR -#define UART_LCR UART1_LCR -#define UART_MCR UART1_MCR -#define UART_LSR UART1_LSR -#define UART_SCR UART1_SCR -#define UART_GCTL UART1_GCTL + +#define BFIN_UART_THR UART1_THR +#define BFIN_UART_RBR UART1_RBR +#define BFIN_UART_DLL UART1_DLL +#define BFIN_UART_IER UART1_IER +#define BFIN_UART_DLH UART1_DLH +#define BFIN_UART_IIR UART1_IIR +#define BFIN_UART_LCR UART1_LCR +#define BFIN_UART_MCR UART1_MCR +#define BFIN_UART_LSR UART1_LSR +#define BFIN_UART_SCR UART1_SCR +#define BFIN_UART_GCTL UART1_GCTL + +#define BFIN_UART_NR_PORTS 4 + +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ /* PLL_DIV Masks */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h index 308b33ab5311..60b9f77576f1 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF542.h +++ b/include/asm-blackfin/mach-bf548/cdefBF542.h @@ -123,12 +123,12 @@ #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) @@ -184,8 +184,8 @@ #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) @@ -244,7 +244,7 @@ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h index 7a2d177c8dc2..ea9b4ab496f3 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF544.h +++ b/include/asm-blackfin/mach-bf548/cdefBF544.h @@ -113,39 +113,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* CAN Controller 1 Config 1 Registers */ #define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h index d0a200b08abd..ba716277c00d 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF547.h +++ b/include/asm-blackfin/mach-bf548/cdefBF547.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h index 674be0216bff..ae971ebff6a0 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF548.h +++ b/include/asm-blackfin/mach-bf548/cdefBF548.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h index 2ab5b7c00820..92d07d961999 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF549.h +++ b/include/asm-blackfin/mach-bf548/cdefBF549.h @@ -185,39 +185,6 @@ /* Two Wire Interface Registers (TWI1) */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) -#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) -#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) - /* SPI2 Registers */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) @@ -1773,7 +1740,7 @@ #define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) #define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) -#define bfin_write_USB_DMA5COUNTLOW(val) fin_write16(USB_DMA5COUNTLOW, val) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) #define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 19ddcd83c71f..57ac8cb9b1f6 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -43,7 +43,33 @@ /* PLL Registers */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr0, iwr1, iwr2; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SIC_IWR0); iwr1 = bfin_read32(SIC_IWR1); @@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); bfin_write32(SIC_IWR2, iwr2); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) @@ -211,39 +240,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* Two Wire Interface Registers (TWI0) */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL) -#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val) -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL) -#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val) -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) - /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ @@ -323,7 +319,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD) +#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) @@ -392,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 0 Registers */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) @@ -421,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 1 Registers */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) @@ -450,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 2 Registers */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) @@ -479,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 3 Registers */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) @@ -508,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 4 Registers */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) @@ -537,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 5 Registers */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) @@ -566,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 6 Registers */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) @@ -595,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 7 Registers */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) @@ -624,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 8 Registers */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) @@ -653,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 9 Registers */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) @@ -682,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 10 Registers */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) @@ -711,23 +707,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 11 Registers */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) @@ -740,7 +736,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 0 Registers */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) @@ -803,11 +799,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) @@ -829,11 +825,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) @@ -1246,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 12 Registers */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR) +#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR) +#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY) +#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY) +#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR) +#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR) +#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) @@ -1275,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 13 Registers */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR) +#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR) +#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY) +#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY) +#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR) +#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR) +#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) @@ -1304,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 14 Registers */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR) +#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR) +#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY) +#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY) +#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR) +#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR) +#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) @@ -1333,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 15 Registers */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR) +#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR) +#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY) +#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY) +#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR) +#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR) +#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) @@ -1362,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 16 Registers */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR) +#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR) +#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY) +#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY) +#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR) +#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR) +#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) @@ -1391,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 17 Registers */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR) +#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR) +#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY) +#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY) +#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR) +#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR) +#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) @@ -1420,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 18 Registers */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR) +#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR) +#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY) +#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY) +#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR) +#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR) +#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) @@ -1449,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 19 Registers */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR) +#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR) +#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY) +#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY) +#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR) +#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR) +#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) @@ -1478,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 20 Registers */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR) +#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR) +#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY) +#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY) +#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR) +#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR) +#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) @@ -1507,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 21 Registers */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR) +#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) #define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR) +#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY) +#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY) +#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) #define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR) +#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) #define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR) +#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) @@ -1536,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 22 Registers */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR) +#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) #define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR) +#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY) +#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY) +#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) #define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR) +#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) #define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR) +#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) @@ -1565,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* DMA Channel 23 Registers */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR) +#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) #define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR) +#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY) +#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY) +#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) #define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR) +#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) #define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR) +#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) @@ -1594,23 +1590,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 2 Registers */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) #define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) @@ -1620,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) #define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) @@ -1649,23 +1645,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* MDMA Stream 3 Registers */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) #define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) @@ -1675,23 +1671,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) #define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h index 46ff31f20ae5..36a2ef7e7849 100644 --- a/include/asm-blackfin/mach-bf548/dma.h +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -73,6 +73,4 @@ #define MAX_BLACKFIN_DMA_CHANNEL 32 -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL]; #endif diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index befc2903d5a5..ab0b863eee66 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -29,16 +29,19 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) +#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) +#define DDR_CLK_HZ(x) (1000*1000*1000/x) #if (CONFIG_MEM_MT46V32M16_6T) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) -#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) #define DDR_tWTR DDR_TWTR(1) @@ -49,12 +52,13 @@ #if (CONFIG_MEM_MT46V32M16_5B) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) -#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) #define DDR_tWTR DDR_TWTR(2) @@ -65,6 +69,7 @@ #if (CONFIG_MEM_GENERIC_BOARD) #define DDR_SIZE DEVSZ_512 #define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 #define DDR_tRCD DDR_TRCD(3) #define DDR_tWTR DDR_TWTR(2) @@ -77,14 +82,15 @@ #define DDR_tREFI DDR_TREFI(1288) #endif -#if (CONFIG_SCLK_HZ <= 133333333) -#define DDR_CL CL_2 -#elif (CONFIG_SCLK_HZ <= 166666666) -#define DDR_CL CL_2_5 +#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) +# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." +#elif(CONFIG_SCLK_HZ <= 133333333) +# define DDR_CL CL_2 #else -#define DDR_CL CL_3 +# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." #endif + #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ | DDR_tMRD | DDR_tWR | DDR_tRCD) diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 0c1d46193939..82157caa96a2 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -256,10 +256,14 @@ #define ANOMALY_05000357 (1) /* Conflicting Column Address Widths Causes SDRAM Errors */ #define ANOMALY_05000362 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index b6f513bee56e..8a4e66d1db37 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -1,22 +1,38 @@ +/* + * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h + * based on: + * author: + * + * created: + * description: + * blackfin serial driver head file + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + #include <linux/serial.h> #include <asm/dma.h> #include <asm/portmux.h> -#define NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) @@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) bfin_write16(uart->port.membase + OFFSET_LSR, -1); } -struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; @@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = { #define DRIVER_NAME "bfin-uart" -int nr_ports = NR_PORTS; +int nr_ports = BFIN_UART_NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h new file mode 100644 index 000000000000..cefcf8bb505b --- /dev/null +++ b/include/asm-blackfin/mach-bf561/bfin_sir.h @@ -0,0 +1,120 @@ +/* + * Blackfin Infra-red Driver + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Licensed under the GPL-2 or later. + * + */ + +#include <linux/serial.h> +#include <asm/dma.h> +#include <asm/portmux.h> + +#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) +#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) +#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) +#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) +#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) +#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) +#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) + +#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) +#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) +#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) +#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) +#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) +#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) + +#ifdef CONFIG_SIR_BFIN_DMA +struct dma_rx_buf { + char *buf; + int head; + int tail; + }; +#endif /* CONFIG_SIR_BFIN_DMA */ + +struct bfin_sir_port { + unsigned char __iomem *membase; + unsigned int irq; + unsigned int lsr; + unsigned long clk; + struct net_device *dev; +#ifdef CONFIG_SIR_BFIN_DMA + int tx_done; + struct dma_rx_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; +#endif /* CONFIG_SIR_BFIN_DMA */ + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; +}; + +struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; + +struct bfin_sir_port_res { + unsigned long base_addr; + int irq; + unsigned int rx_dma_channel; + unsigned int tx_dma_channel; +}; + +struct bfin_sir_port_res bfin_sir_port_resource[] = { +#ifdef CONFIG_BFIN_SIR0 + { + 0xFFC00400, + IRQ_UART_RX, + CH_UART_RX, + CH_UART_TX, + }, +#endif +}; + +int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); + +struct bfin_sir_self { + struct bfin_sir_port *sir_port; + spinlock_t lock; + unsigned int open; + int speed; + int newspeed; + + struct sk_buff *txskb; + struct sk_buff *rxskb; + struct net_device_stats stats; + struct device *dev; + struct irlap_cb *irlap; + struct qos_info qos; + + iobuff_t tx_buff; + iobuff_t rx_buff; + + struct work_struct work; + int mtt; +}; + +static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) +{ + unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); + port->lsr |= (lsr & (BI|FE|PE|OE)); + return lsr | port->lsr; +} + +static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) +{ + port->lsr = 0; + bfin_read16(port->membase + OFFSET_LSR); +} + +#define DRIVER_NAME "bfin_sir" + +static void bfin_sir_hw_init(void) +{ +#ifdef CONFIG_BFIN_SIR0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + SSYNC(); +} diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h index 3a16df2c86d8..0ea8666e6764 100644 --- a/include/asm-blackfin/mach-bf561/blackfin.h +++ b/include/asm-blackfin/mach-bf561/blackfin.h @@ -69,5 +69,19 @@ #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) +#define BFIN_UART_NR_PORTS 1 + +#define OFFSET_THR 0x00 /* Transmit Holding register */ +#define OFFSET_RBR 0x00 /* Receive Buffer register */ +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_IER 0x04 /* Interrupt Enable Register */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_GCTL 0x24 /* Global Control Register */ #endif /* _MACH_BLACKFIN_H_ */ diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 1bc8d2f89ccc..b07ffccd66dd 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -47,7 +47,30 @@ /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + local_irq_restore(flags); +} #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) @@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr0, iwr1; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SICA_IWR0); iwr1 = bfin_read32(SICA_IWR1); @@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SICA_IWR0, iwr0); bfin_write32(SICA_IWR1, iwr1); + local_irq_restore(flags); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index c3c0eb13c819..366c9b9a0cb7 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -110,18 +110,23 @@ #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -#define UART_MSR 0xFFC00418 /* Modem Status Register */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* + * Because include/linux/serial_reg.h have defined UART_*, + * So we define blackfin uart regs to BFIN_UART0_*. + */ +#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ +#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ +#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ +#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ +#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */ +#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ #define SPI0_REGBASE 0xFFC00500 @@ -866,6 +871,8 @@ /* PLL_DIV Masks */ #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 766334b7d8ab..21d982003e75 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -32,7 +32,4 @@ #define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_DEST 35 -extern int channel2irq(unsigned int channel); -extern struct dma_register *base_addr[]; - #endif diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h index 0d3f650d2d99..0807b286cd9e 100644 --- a/include/asm-blackfin/portmux.h +++ b/include/asm-blackfin/portmux.h @@ -17,8 +17,8 @@ int peripheral_request(unsigned short per, const char *label); void peripheral_free(unsigned short per); -int peripheral_request_list(unsigned short per[], const char *label); -void peripheral_free_list(unsigned short per[]); +int peripheral_request_list(const unsigned short per[], const char *label); +void peripheral_free_list(const unsigned short per[]); #include <asm/gpio.h> #include <asm/mach/portmux.h> diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index 1033e5c76011..1c0040724612 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -26,9 +26,10 @@ static inline void wrusp(unsigned long usp) /* * User space process size: 1st byte beyond user address space. + * Fairly meaningless on nommu. Parts of user programs can be scattered + * in a lot of places, so just disable this by setting it to 0xFFFFFFFF. */ -extern unsigned long memory_end; -#define TASK_SIZE (memory_end) +#define TASK_SIZE 0xFFFFFFFF #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h index 0250429b736a..87951d251458 100644 --- a/include/asm-blackfin/signal.h +++ b/include/asm-blackfin/signal.h @@ -143,7 +143,7 @@ struct sigaction { #endif /* __KERNEL__ */ typedef struct sigaltstack { - void *ss_sp; + void __user *ss_sp; int ss_flags; size_t ss_size; } stack_t; diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h index 15b99cf4f50b..bc2fe5accf20 100644 --- a/include/asm-blackfin/thread_info.h +++ b/include/asm-blackfin/thread_info.h @@ -81,14 +81,11 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) #define init_stack (init_thread_union.stack) -/* How to get the thread information struct from C */ - -static inline struct thread_info *current_thread_info(void) - __attribute__ ((__const__)); - -/* Given a task stack pointer, you can find it's task structure - * just by masking it to the 8K boundary. +/* Given a task stack pointer, you can find its corresponding + * thread_info structure just by masking it to the THREAD_SIZE + * boundary (currently 8K as you can see above). */ +__attribute_const__ static inline struct thread_info *current_thread_info(void) { struct thread_info *ti; diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h new file mode 100644 index 000000000000..6e5859b6ea32 --- /dev/null +++ b/include/asm-blackfin/time.h @@ -0,0 +1,36 @@ +/* + * asm-blackfin/time.h: + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIME_H +#define _ASM_BLACKFIN_TIME_H + +/* + * The way that the Blackfin core timer works is: + * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) + * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) + * + * If you take the fastest clock (1ns, or 1GHz to make the math work easier) + * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter + * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need + * to use TSCALE, and program it to zero (which is pass CCLK through). + * If you feel like using it, try to keep HZ * TIMESCALE to some + * value that divides easy (like power of 2). + */ + +#ifndef CONFIG_CPU_FREQ +#define TIME_SCALE 1 +#else +/* + * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . + * Whenever we change the Core Clock frequency changes we immediately + * adjust the Core Timer Presale Register. This way we don't lose time. + */ +#define TIME_SCALE 4 +#endif + +#endif diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h index 828590117f51..22b0806161bb 100644 --- a/include/asm-blackfin/timex.h +++ b/include/asm-blackfin/timex.h @@ -1,18 +1,23 @@ -/* blackfin architecture timex specifications: Lineo Inc. 2001 +/* + * asm-blackfin/timex.h: cpu cycles! * - * Based on: include/asm-m68knommu/timex.h + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. */ -#ifndef _ASMBLACKFIN_TIMEX_H -#define _ASMBLACKFIN_TIMEX_H +#ifndef _ASM_BLACKFIN_TIMEX_H +#define _ASM_BLACKFIN_TIMEX_H #define CLOCK_TICK_RATE 1000000 /* Underlying HZ */ -typedef unsigned long cycles_t; +typedef unsigned long long cycles_t; static inline cycles_t get_cycles(void) { - return 0; + unsigned long tmp, tmp2; + __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); + return tmp | ((cycles_t)tmp2 << 32); } #endif diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h index ef18afbc2101..312b596b9731 100644 --- a/include/asm-blackfin/trace.h +++ b/include/asm-blackfin/trace.h @@ -62,14 +62,14 @@ extern unsigned long software_trace_buff[]; preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ dreg = [preg]; \ - [sp++] = dreg; \ + [--sp] = dreg; \ dreg = 0x1; \ [preg] = dreg; #define trace_buffer_restore(preg, dreg) \ preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ - dreg = [sp--]; \ + dreg = [sp++]; \ [preg] = dreg; #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 22a410b8003b..d928b8099056 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -133,7 +133,7 @@ static inline int bad_user_access_length(void) } #define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\ - __FILE__, __LINE__, __FUNCTION__),\ + __FILE__, __LINE__, __func__),\ bad_user_access_length(), (-EFAULT)) /* @@ -177,7 +177,7 @@ static inline int bad_user_access_length(void) default: \ x = 0; \ printk(KERN_INFO "get_user_bad: %s:%d %s\n", \ - __FILE__, __LINE__, __FUNCTION__); \ + __FILE__, __LINE__, __func__); \ _err = __get_user_bad(); \ break; \ } \ diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index c18a399f6e3e..42955d0c439b 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -265,14 +265,14 @@ /* 258 __NR_remap_file_pages */ #define __NR_set_tid_address 259 #define __NR_timer_create 260 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_timer_settime 261 +#define __NR_timer_gettime 262 +#define __NR_timer_getoverrun 263 +#define __NR_timer_delete 264 +#define __NR_clock_settime 265 +#define __NR_clock_gettime 266 +#define __NR_clock_getres 267 +#define __NR_clock_nanosleep 268 #define __NR_statfs64 269 #define __NR_fstatfs64 270 #define __NR_tgkill 271 @@ -283,11 +283,11 @@ /* 276 __NR_get_mempolicy */ /* 277 __NR_set_mempolicy */ #define __NR_mq_open 278 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_mq_unlink 279 +#define __NR_mq_timedsend 280 +#define __NR_mq_timedreceive 281 +#define __NR_mq_notify 282 +#define __NR_mq_getsetattr 283 #define __NR_kexec_load 284 #define __NR_waitid 285 #define __NR_add_key 286 diff --git a/include/asm-sparc/device.h b/include/asm-sparc/device.h index 680e51d87374..19790eb99cc6 100644 --- a/include/asm-sparc/device.h +++ b/include/asm-sparc/device.h @@ -16,6 +16,8 @@ struct dev_archdata { struct device_node *prom_node; struct of_device *op; + + int numa_node; }; #endif /* _ASM_SPARC_DEVICE_H */ diff --git a/include/asm-sparc/prom.h b/include/asm-sparc/prom.h index df5dc4422483..fd55522481cd 100644 --- a/include/asm-sparc/prom.h +++ b/include/asm-sparc/prom.h @@ -77,6 +77,11 @@ extern int of_getintprop_default(struct device_node *np, const char *name, int def); extern int of_find_in_proplist(const char *list, const char *match, int len); +#ifdef CONFIG_NUMA +extern int of_node_to_nid(struct device_node *dp); +#else +#define of_node_to_nid(dp) (-1) +#endif extern void prom_build_devicetree(void); diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h index 46325ddee23b..d7b9afcba08b 100644 --- a/include/asm-sparc64/iommu.h +++ b/include/asm-sparc64/iommu.h @@ -56,6 +56,7 @@ struct strbuf { }; extern int iommu_table_init(struct iommu *iommu, int tsbsize, - u32 dma_offset, u32 dma_addr_mask); + u32 dma_offset, u32 dma_addr_mask, + int numa_node); #endif /* !(_SPARC64_IOMMU_H) */ diff --git a/include/asm-sparc64/mmzone.h b/include/asm-sparc64/mmzone.h new file mode 100644 index 000000000000..ebf5986c12ed --- /dev/null +++ b/include/asm-sparc64/mmzone.h @@ -0,0 +1,17 @@ +#ifndef _SPARC64_MMZONE_H +#define _SPARC64_MMZONE_H + +#ifdef CONFIG_NEED_MULTIPLE_NODES + +extern struct pglist_data *node_data[]; + +#define NODE_DATA(nid) (node_data[nid]) +#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn) +#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn) + +extern int numa_cpu_lookup_table[]; +extern cpumask_t numa_cpumask_lookup_table[]; + +#endif /* CONFIG_NEED_MULTIPLE_NODES */ + +#endif /* _SPARC64_MMZONE_H */ diff --git a/include/asm-sparc64/numnodes.h b/include/asm-sparc64/numnodes.h deleted file mode 100644 index 017e7e74f5e7..000000000000 --- a/include/asm-sparc64/numnodes.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _SPARC64_NUMNODES_H -#define _SPARC64_NUMNODES_H - -#define NODES_SHIFT 0 - -#endif /* !(_SPARC64_NUMNODES_H) */ diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h index 6da197803efc..b4b951d570bb 100644 --- a/include/asm-sparc64/ptrace.h +++ b/include/asm-sparc64/ptrace.h @@ -8,6 +8,8 @@ * stack during a system call and basically all traps. */ +#define PT_REGS_MAGIC 0x57ac6c00 + #ifndef __ASSEMBLY__ struct pt_regs { @@ -16,7 +18,19 @@ struct pt_regs { unsigned long tpc; unsigned long tnpc; unsigned int y; - unsigned int fprs; + + /* We encode a magic number, PT_REGS_MAGIC, along + * with the %tt (trap type) register value at trap + * entry time. The magic number allows us to identify + * accurately a trap stack frame in the stack + * unwinder, and the %tt value allows us to test + * things like "in a system call" etc. for an arbitray + * process. + * + * The PT_REGS_MAGIC is choosen such that it can be + * loaded completely using just a sethi instruction. + */ + unsigned int magic; }; struct pt_regs32 { @@ -147,7 +161,7 @@ extern void __show_regs(struct pt_regs *); #define PT_V9_TPC 0x88 #define PT_V9_TNPC 0x90 #define PT_V9_Y 0x98 -#define PT_V9_FPRS 0x9c +#define PT_V9_MAGIC 0x9c #define PT_TSTATE PT_V9_TSTATE #define PT_TPC PT_V9_TPC #define PT_TNPC PT_V9_TNPC diff --git a/include/asm-sparc64/sparsemem.h b/include/asm-sparc64/sparsemem.h index 77bcd2bfa53c..b99d4e4b6d28 100644 --- a/include/asm-sparc64/sparsemem.h +++ b/include/asm-sparc64/sparsemem.h @@ -3,7 +3,7 @@ #ifdef __KERNEL__ -#define SECTION_SIZE_BITS 31 +#define SECTION_SIZE_BITS 30 #define MAX_PHYSADDR_BITS 42 #define MAX_PHYSMEM_BITS 42 diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h index c6b557034f68..001c04027c82 100644 --- a/include/asm-sparc64/topology.h +++ b/include/asm-sparc64/topology.h @@ -1,6 +1,77 @@ #ifndef _ASM_SPARC64_TOPOLOGY_H #define _ASM_SPARC64_TOPOLOGY_H +#ifdef CONFIG_NUMA + +#include <asm/mmzone.h> + +static inline int cpu_to_node(int cpu) +{ + return numa_cpu_lookup_table[cpu]; +} + +#define parent_node(node) (node) + +static inline cpumask_t node_to_cpumask(int node) +{ + return numa_cpumask_lookup_table[node]; +} + +/* Returns a pointer to the cpumask of CPUs on Node 'node'. */ +#define node_to_cpumask_ptr(v, node) \ + cpumask_t *v = &(numa_cpumask_lookup_table[node]) + +#define node_to_cpumask_ptr_next(v, node) \ + v = &(numa_cpumask_lookup_table[node]) + +static inline int node_to_first_cpu(int node) +{ + cpumask_t tmp; + tmp = node_to_cpumask(node); + return first_cpu(tmp); +} + +struct pci_bus; +#ifdef CONFIG_PCI +extern int pcibus_to_node(struct pci_bus *pbus); +#else +static inline int pcibus_to_node(struct pci_bus *pbus) +{ + return -1; +} +#endif + +#define pcibus_to_cpumask(bus) \ + (pcibus_to_node(bus) == -1 ? \ + CPU_MASK_ALL : \ + node_to_cpumask(pcibus_to_node(bus))) + +#define SD_NODE_INIT (struct sched_domain) { \ + .min_interval = 8, \ + .max_interval = 32, \ + .busy_factor = 32, \ + .imbalance_pct = 125, \ + .cache_nice_tries = 2, \ + .busy_idx = 3, \ + .idle_idx = 2, \ + .newidle_idx = 0, \ + .wake_idx = 1, \ + .forkexec_idx = 1, \ + .flags = SD_LOAD_BALANCE \ + | SD_BALANCE_FORK \ + | SD_BALANCE_EXEC \ + | SD_SERIALIZE \ + | SD_WAKE_BALANCE, \ + .last_balance = jiffies, \ + .balance_interval = 1, \ +} + +#else /* CONFIG_NUMA */ + +#include <asm-generic/topology.h> + +#endif /* !(CONFIG_NUMA) */ + #ifdef CONFIG_SMP #define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) #define topology_core_id(cpu) (cpu_data(cpu).core_id) @@ -10,8 +81,6 @@ #define smt_capable() (sparc64_multi_core) #endif /* CONFIG_SMP */ -#include <asm-generic/topology.h> - #define cpu_coregroup_map(cpu) (cpu_core_map[cpu]) #endif /* _ASM_SPARC64_TOPOLOGY_H */ diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h index 7208a777750e..d3cc4eff39a6 100644 --- a/include/asm-sparc64/ttable.h +++ b/include/asm-sparc64/ttable.h @@ -28,7 +28,7 @@ call routine; \ add %sp, PTREGS_OFF, %o0; \ ba,pt %xcc, rtrap; \ - clr %l6; \ + nop; \ nop; #define TRAP_7INSNS(routine) \ @@ -38,7 +38,7 @@ call routine; \ add %sp, PTREGS_OFF, %o0; \ ba,pt %xcc, rtrap; \ - clr %l6; + nop; #define TRAP_SAVEFPU(routine) \ sethi %hi(109f), %g7; \ @@ -47,7 +47,7 @@ call routine; \ add %sp, PTREGS_OFF, %o0; \ ba,pt %xcc, rtrap; \ - clr %l6; \ + nop; \ nop; #define TRAP_NOSAVE(routine) \ @@ -67,7 +67,7 @@ call routine; \ add %sp, PTREGS_OFF, %o0; \ ba,pt %xcc, rtrap; \ - clr %l6; \ + nop; \ nop; #define TRAP_ARG(routine, arg) \ @@ -78,7 +78,7 @@ call routine; \ mov arg, %o1; \ ba,pt %xcc, rtrap; \ - clr %l6; + nop; #define TRAPTL1_ARG(routine, arg) \ sethi %hi(109f), %g7; \ @@ -88,7 +88,7 @@ call routine; \ mov arg, %o1; \ ba,pt %xcc, rtrap; \ - clr %l6; + nop; #define SYSCALL_TRAP(routine, systbl) \ sethi %hi(109f), %g7; \ @@ -166,7 +166,7 @@ ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \ add %l1, 4, %l2; \ stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \ - ba,pt %xcc, rtrap_clr_l6; \ + ba,pt %xcc, rtrap; \ stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]; #ifdef CONFIG_KPROBES diff --git a/include/asm-x86/fixmap.h b/include/asm-x86/fixmap.h index 382eb271a892..5bd206973dca 100644 --- a/include/asm-x86/fixmap.h +++ b/include/asm-x86/fixmap.h @@ -1,5 +1,13 @@ +#ifndef _ASM_FIXMAP_H +#define _ASM_FIXMAP_H + #ifdef CONFIG_X86_32 # include "fixmap_32.h" #else # include "fixmap_64.h" #endif + +#define clear_fixmap(idx) \ + __set_fixmap(idx, 0, __pgprot(0)) + +#endif diff --git a/include/asm-x86/fixmap_32.h b/include/asm-x86/fixmap_32.h index eb1665125c44..4b96148e90c1 100644 --- a/include/asm-x86/fixmap_32.h +++ b/include/asm-x86/fixmap_32.h @@ -10,8 +10,8 @@ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 */ -#ifndef _ASM_FIXMAP_H -#define _ASM_FIXMAP_H +#ifndef _ASM_FIXMAP_32_H +#define _ASM_FIXMAP_32_H /* used by vmalloc.c, vsyscall.lds.S. @@ -121,9 +121,6 @@ extern void reserve_top_address(unsigned long reserve); #define set_fixmap_nocache(idx, phys) \ __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE) -#define clear_fixmap(idx) \ - __set_fixmap(idx, 0, __pgprot(0)) - #define FIXADDR_TOP ((unsigned long)__FIXADDR_TOP) #define __FIXADDR_SIZE (__end_of_permanent_fixed_addresses << PAGE_SHIFT) diff --git a/include/asm-x86/fixmap_64.h b/include/asm-x86/fixmap_64.h index f3d76858c0e6..355d26a75a82 100644 --- a/include/asm-x86/fixmap_64.h +++ b/include/asm-x86/fixmap_64.h @@ -8,8 +8,8 @@ * Copyright (C) 1998 Ingo Molnar */ -#ifndef _ASM_FIXMAP_H -#define _ASM_FIXMAP_H +#ifndef _ASM_FIXMAP_64_H +#define _ASM_FIXMAP_64_H #include <linux/kernel.h> #include <asm/apicdef.h> diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h index 62ebdec394b9..1ebaa5cd3112 100644 --- a/include/asm-x86/smp.h +++ b/include/asm-x86/smp.h @@ -199,7 +199,6 @@ static inline int hard_smp_processor_id(void) #ifdef CONFIG_HOTPLUG_CPU extern void cpu_exit_clear(void); extern void cpu_uninit(void); -extern void remove_siblinginfo(int cpu); #endif extern void smp_alloc_memory(void); diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h index 0434bd8349a7..d2d8eb5b55f5 100644 --- a/include/asm-x86/tsc.h +++ b/include/asm-x86/tsc.h @@ -18,7 +18,6 @@ extern unsigned int cpu_khz; extern unsigned int tsc_khz; extern void disable_TSC(void); -extern void enable_TSC(void); static inline cycles_t get_cycles(void) { diff --git a/include/linux/dcache.h b/include/linux/dcache.h index fabd16d03a27..cfb1627ac51c 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -301,7 +301,9 @@ extern int d_validate(struct dentry *, struct dentry *); */ extern char *dynamic_dname(struct dentry *, char *, int, const char *, ...); +extern char *__d_path(const struct path *path, struct path *root, char *, int); extern char *d_path(struct path *, char *, int); +extern char *dentry_path(struct dentry *, char *, int); /* Allocation counts.. */ diff --git a/include/linux/dvb/dmx.h b/include/linux/dvb/dmx.h index c6a2353c4e68..402fb7a8d922 100644 --- a/include/linux/dvb/dmx.h +++ b/include/linux/dvb/dmx.h @@ -39,9 +39,10 @@ typedef enum DMX_OUT_DECODER, /* Streaming directly to decoder. */ DMX_OUT_TAP, /* Output going to a memory buffer */ /* (to be retrieved via the read command).*/ - DMX_OUT_TS_TAP /* Output multiplexed into a new TS */ + DMX_OUT_TS_TAP, /* Output multiplexed into a new TS */ /* (to be retrieved by reading from the */ /* logical DVR device). */ + DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */ } dmx_output_t; diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h index adcbb05b120b..de8387b7ceb6 100644 --- a/include/linux/exportfs.h +++ b/include/linux/exportfs.h @@ -43,7 +43,7 @@ struct fid { u32 parent_ino; u32 parent_gen; } i32; - __u32 raw[6]; + __u32 raw[0]; }; }; diff --git a/include/linux/fs.h b/include/linux/fs.h index cc2be2cf7d41..6556f2f967e5 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -973,6 +973,7 @@ extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset, /* fs/locks.c */ extern void locks_init_lock(struct file_lock *); extern void locks_copy_lock(struct file_lock *, struct file_lock *); +extern void __locks_copy_lock(struct file_lock *, const struct file_lock *); extern void locks_remove_posix(struct file *, fl_owner_t); extern void locks_remove_flock(struct file *); extern void posix_test_lock(struct file *, struct file_lock *); diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index b979112f74e0..32eb8bbe4831 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -125,6 +125,7 @@ #define I2C_HW_B_CX2341X 0x010020 /* Conexant CX2341X MPEG encoder cards */ #define I2C_HW_B_INTELFB 0x010021 /* intel framebuffer driver */ #define I2C_HW_B_CX23885 0x010022 /* conexant 23885 based tv cards (bus1) */ +#define I2C_HW_B_AU0828 0x010023 /* auvitek au0828 usb bridge */ /* --- PCF 8584 based algorithms */ #define I2C_HW_P_ELEK 0x020002 /* Elektor ISA Bus inteface card */ diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index f27d11ab418b..529f301d9372 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -465,13 +465,19 @@ enum ieee80211_eid { WLAN_EID_TS_DELAY = 43, WLAN_EID_TCLAS_PROCESSING = 44, WLAN_EID_QOS_CAPA = 46, - /* 802.11s */ - WLAN_EID_MESH_CONFIG = 36, /* Pending IEEE 802.11 ANA approval */ - WLAN_EID_MESH_ID = 37, /* Pending IEEE 802.11 ANA approval */ - WLAN_EID_PEER_LINK = 40, /* Pending IEEE 802.11 ANA approval */ - WLAN_EID_PREQ = 53, /* Pending IEEE 802.11 ANA approval */ - WLAN_EID_PREP = 54, /* Pending IEEE 802.11 ANA approval */ - WLAN_EID_PERR = 55, /* Pending IEEE 802.11 ANA approval */ + /* 802.11s + * + * All mesh EID numbers are pending IEEE 802.11 ANA approval. + * The numbers have been incremented from those suggested in + * 802.11s/D2.0 so that MESH_CONFIG does not conflict with + * EXT_SUPP_RATES. + */ + WLAN_EID_MESH_CONFIG = 51, + WLAN_EID_MESH_ID = 52, + WLAN_EID_PEER_LINK = 55, + WLAN_EID_PREQ = 68, + WLAN_EID_PREP = 69, + WLAN_EID_PERR = 70, /* 802.11h */ WLAN_EID_PWR_CONSTRAINT = 32, WLAN_EID_PWR_CAPABILITY = 33, diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index 4babb2a129ac..102d928f7206 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h @@ -91,6 +91,7 @@ struct nlm_wait; */ #define NLMCLNT_OHSIZE ((__NEW_UTS_LEN) + 10u) struct nlm_rqst { + atomic_t a_count; unsigned int a_flags; /* initial RPC task flags */ struct nlm_host * a_host; /* host handle */ struct nlm_args a_args; /* arguments */ @@ -173,8 +174,10 @@ void nlmclnt_next_cookie(struct nlm_cookie *); /* * Host cache */ -struct nlm_host *nlmclnt_lookup_host(const struct sockaddr_in *, int, int, - const char *, unsigned int); +struct nlm_host *nlmclnt_lookup_host(const struct sockaddr_in *sin, + int proto, u32 version, + const char *hostname, + unsigned int hostname_len); struct nlm_host *nlmsvc_lookup_host(struct svc_rqst *, const char *, unsigned int); struct rpc_clnt * nlm_bind_host(struct nlm_host *); @@ -191,7 +194,7 @@ void nsm_release(struct nsm_handle *); * This is used in garbage collection and resource reclaim * A return value != 0 means destroy the lock/block/share */ -typedef int (*nlm_host_match_fn_t)(struct nlm_host *cur, struct nlm_host *ref); +typedef int (*nlm_host_match_fn_t)(void *cur, struct nlm_host *ref); /* * Server-side lock handling @@ -217,8 +220,13 @@ void nlmsvc_mark_resources(void); void nlmsvc_free_host_resources(struct nlm_host *); void nlmsvc_invalidate_all(void); -static __inline__ struct inode * -nlmsvc_file_inode(struct nlm_file *file) +/* + * Cluster failover support + */ +int nlmsvc_unlock_all_by_sb(struct super_block *sb); +int nlmsvc_unlock_all_by_ip(__be32 server_addr); + +static inline struct inode *nlmsvc_file_inode(struct nlm_file *file) { return file->f_file->f_path.dentry->d_inode; } @@ -226,8 +234,8 @@ nlmsvc_file_inode(struct nlm_file *file) /* * Compare two host addresses (needs modifying for ipv6) */ -static __inline__ int -nlm_cmp_addr(const struct sockaddr_in *sin1, const struct sockaddr_in *sin2) +static inline int nlm_cmp_addr(const struct sockaddr_in *sin1, + const struct sockaddr_in *sin2) { return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; } @@ -236,8 +244,8 @@ nlm_cmp_addr(const struct sockaddr_in *sin1, const struct sockaddr_in *sin2) * Compare two NLM locks. * When the second lock is of type F_UNLCK, this acts like a wildcard. */ -static __inline__ int -nlm_compare_locks(const struct file_lock *fl1, const struct file_lock *fl2) +static inline int nlm_compare_locks(const struct file_lock *fl1, + const struct file_lock *fl2) { return fl1->fl_pid == fl2->fl_pid && fl1->fl_owner == fl2->fl_owner diff --git a/include/linux/lockd/sm_inter.h b/include/linux/lockd/sm_inter.h index 22a645828f26..5a5448bdb17d 100644 --- a/include/linux/lockd/sm_inter.h +++ b/include/linux/lockd/sm_inter.h @@ -19,6 +19,7 @@ #define SM_NOTIFY 6 #define SM_MAXSTRLEN 1024 +#define SM_PRIV_SIZE 16 /* * Arguments for all calls to statd diff --git a/include/linux/meye.h b/include/linux/meye.h index 39fd9c8ddd4b..12010ace1f04 100644 --- a/include/linux/meye.h +++ b/include/linux/meye.h @@ -58,7 +58,7 @@ struct meye_params { /* V4L2 private controls */ #define V4L2_CID_AGC V4L2_CID_PRIVATE_BASE -#define V4L2_CID_SHARPNESS (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_MEYE_SHARPNESS (V4L2_CID_PRIVATE_BASE + 1) #define V4L2_CID_PICTURE (V4L2_CID_PRIVATE_BASE + 2) #define V4L2_CID_JPEGQUAL (V4L2_CID_PRIVATE_BASE + 3) #define V4L2_CID_FRAMERATE (V4L2_CID_PRIVATE_BASE + 4) diff --git a/include/linux/mnt_namespace.h b/include/linux/mnt_namespace.h index 8eed44f8ca73..830bbcd449d6 100644 --- a/include/linux/mnt_namespace.h +++ b/include/linux/mnt_namespace.h @@ -5,6 +5,7 @@ #include <linux/mount.h> #include <linux/sched.h> #include <linux/nsproxy.h> +#include <linux/seq_file.h> struct mnt_namespace { atomic_t count; @@ -14,6 +15,13 @@ struct mnt_namespace { int event; }; +struct proc_mounts { + struct seq_file m; /* must be the first element */ + struct mnt_namespace *ns; + struct path root; + int event; +}; + extern struct mnt_namespace *copy_mnt_ns(unsigned long, struct mnt_namespace *, struct fs_struct *); extern void __put_mnt_ns(struct mnt_namespace *ns); @@ -37,5 +45,9 @@ static inline void get_mnt_ns(struct mnt_namespace *ns) atomic_inc(&ns->count); } +extern const struct seq_operations mounts_op; +extern const struct seq_operations mountinfo_op; +extern const struct seq_operations mountstats_op; + #endif #endif diff --git a/include/linux/mount.h b/include/linux/mount.h index 87b24cea1863..b4836d58f428 100644 --- a/include/linux/mount.h +++ b/include/linux/mount.h @@ -56,6 +56,8 @@ struct vfsmount { struct list_head mnt_slave; /* slave list entry */ struct vfsmount *mnt_master; /* slave is on master->mnt_slave_list */ struct mnt_namespace *mnt_ns; /* containing namespace */ + int mnt_id; /* mount identifier */ + int mnt_group_id; /* peer group identifier */ /* * We put mnt_count & mnt_expiry_mark at the end of struct vfsmount * to let these frequently modified fields in a separate cache line diff --git a/include/linux/mtd/inftl.h b/include/linux/mtd/inftl.h index 6977780e548f..85fd041d44ad 100644 --- a/include/linux/mtd/inftl.h +++ b/include/linux/mtd/inftl.h @@ -57,6 +57,11 @@ extern char inftlmountrev[]; void INFTL_dumptables(struct INFTLrecord *s); void INFTL_dumpVUchains(struct INFTLrecord *s); +int inftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); +int inftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); + #endif /* __KERNEL__ */ #endif /* __MTD_INFTL_H__ */ diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index bcf2fb3fa4a7..001eec50cac6 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -43,6 +43,11 @@ struct NFTLrecord { int NFTL_mount(struct NFTLrecord *s); int NFTL_formatblock(struct NFTLrecord *s, int block); +int nftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); +int nftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); + #ifndef NFTL_MAJOR #define NFTL_MAJOR 93 #endif diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index fd0a260e070b..9aa2a9149b58 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -187,4 +187,7 @@ struct onenand_manufacturers { char *name; }; +int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops); + #endif /* __LINUX_MTD_ONENAND_H */ diff --git a/include/linux/mtd/plat-ram.h b/include/linux/mtd/plat-ram.h index 9667863bd7e3..0e37ad07bce2 100644 --- a/include/linux/mtd/plat-ram.h +++ b/include/linux/mtd/plat-ram.h @@ -21,8 +21,9 @@ #define PLATRAM_RW (1) struct platdata_mtd_ram { - char *mapname; - char **probes; + const char *mapname; + const char **map_probes; + const char **probes; struct mtd_partition *partitions; int nr_partitions; int bankwidth; diff --git a/include/linux/nfs3.h b/include/linux/nfs3.h index 7f11fa589207..539f3b550eab 100644 --- a/include/linux/nfs3.h +++ b/include/linux/nfs3.h @@ -96,7 +96,7 @@ struct nfs3_fh { #define MOUNTPROC3_UMNTALL 4 -#if defined(__KERNEL__) || defined(NFS_NEED_KERNEL_TYPES) +#if defined(__KERNEL__) /* Number of 32bit words in post_op_attr */ #define NFS3_POST_OP_ATTR_WORDS 22 diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index f4a0e4c218df..27d6a8d98cef 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -430,7 +430,6 @@ extern void nfs_unregister_sysctl(void); /* * linux/fs/nfs/namespace.c */ -extern struct list_head nfs_automount_list; extern const struct inode_operations nfs_mountpoint_inode_operations; extern const struct inode_operations nfs_referral_inode_operations; extern int nfs_mountpoint_expiry_timeout; @@ -466,9 +465,9 @@ extern int nfs_wb_page(struct inode *inode, struct page* page); extern int nfs_wb_page_cancel(struct inode *inode, struct page* page); #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) extern int nfs_commit_inode(struct inode *, int); -extern struct nfs_write_data *nfs_commit_alloc(void); +extern struct nfs_write_data *nfs_commitdata_alloc(void); extern void nfs_commit_free(struct nfs_write_data *wdata); -extern void nfs_commit_release(void *wdata); +extern void nfs_commitdata_release(void *wdata); #else static inline int nfs_commit_inode(struct inode *inode, int how) diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 3423c6761bf7..c9beacd16c00 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -32,6 +32,8 @@ struct nfs_client { const struct nfs_rpc_ops *rpc_ops; /* NFS protocol vector */ int cl_proto; /* Network transport protocol */ + struct rpc_cred *cl_machine_cred; + #ifdef CONFIG_NFS_V4 u64 cl_clientid; /* constant */ nfs4_verifier cl_confirm; @@ -93,6 +95,7 @@ struct nfs_server { unsigned int wpages; /* write size (in pages) */ unsigned int wtmult; /* server disk block size */ unsigned int dtsize; /* readdir size */ + unsigned short port; /* "port=" setting */ unsigned int bsize; /* server block size */ unsigned int acregmin; /* attr cache timeouts */ unsigned int acregmax; @@ -117,6 +120,13 @@ struct nfs_server { atomic_t active; /* Keep trace of any activity to this server */ wait_queue_head_t active_wq; /* Wait for any activity to stop */ + + /* mountd-related mount options */ + struct sockaddr_storage mountd_address; + size_t mountd_addrlen; + u32 mountd_version; + unsigned short mountd_port; + unsigned short mountd_protocol; }; /* Server capabilities */ diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index f301d0b8babc..24263bb8e0be 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -140,6 +140,7 @@ struct nfs_openres { __u32 rflags; struct nfs_fattr * f_attr; struct nfs_fattr * dir_attr; + struct nfs_seqid * seqid; const struct nfs_server *server; int delegation_type; nfs4_stateid delegation; @@ -159,6 +160,7 @@ struct nfs_open_confirmargs { struct nfs_open_confirmres { nfs4_stateid stateid; + struct nfs_seqid * seqid; }; /* @@ -175,6 +177,7 @@ struct nfs_closeargs { struct nfs_closeres { nfs4_stateid stateid; struct nfs_fattr * fattr; + struct nfs_seqid * seqid; const struct nfs_server *server; }; /* @@ -199,7 +202,9 @@ struct nfs_lock_args { }; struct nfs_lock_res { - nfs4_stateid stateid; + nfs4_stateid stateid; + struct nfs_seqid * lock_seqid; + struct nfs_seqid * open_seqid; }; struct nfs_locku_args { @@ -210,7 +215,8 @@ struct nfs_locku_args { }; struct nfs_locku_res { - nfs4_stateid stateid; + nfs4_stateid stateid; + struct nfs_seqid * seqid; }; struct nfs_lockt_args { diff --git a/include/linux/nfsd/Kbuild b/include/linux/nfsd/Kbuild index e726fc3a4375..fc972048e572 100644 --- a/include/linux/nfsd/Kbuild +++ b/include/linux/nfsd/Kbuild @@ -1,6 +1,6 @@ unifdef-y += const.h +unifdef-y += debug.h unifdef-y += export.h +unifdef-y += nfsfh.h unifdef-y += stats.h unifdef-y += syscall.h -unifdef-y += nfsfh.h -unifdef-y += debug.h diff --git a/include/linux/nfsd/cache.h b/include/linux/nfsd/cache.h index 7b5d784cc858..04b355c801d8 100644 --- a/include/linux/nfsd/cache.h +++ b/include/linux/nfsd/cache.h @@ -10,7 +10,6 @@ #ifndef NFSCACHE_H #define NFSCACHE_H -#ifdef __KERNEL__ #include <linux/in.h> #include <linux/uio.h> @@ -77,5 +76,4 @@ void nfsd_reply_cache_shutdown(void); int nfsd_cache_lookup(struct svc_rqst *, int); void nfsd_cache_update(struct svc_rqst *, int, __be32 *); -#endif /* __KERNEL__ */ #endif /* NFSCACHE_H */ diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h index 8caf4c4f64e6..41d30c9c9de6 100644 --- a/include/linux/nfsd/nfsd.h +++ b/include/linux/nfsd/nfsd.h @@ -27,7 +27,6 @@ #define NFSD_VERSION "0.5" #define NFSD_SUPPORTED_MINOR_VERSION 0 -#ifdef __KERNEL__ /* * Special flags for nfsd_permission. These must be different from MAY_READ, * MAY_WRITE, and MAY_EXEC. @@ -56,12 +55,20 @@ extern struct svc_program nfsd_program; extern struct svc_version nfsd_version2, nfsd_version3, nfsd_version4; extern struct svc_serv *nfsd_serv; + +extern struct seq_operations nfs_exports_op; + /* * Function prototypes. */ int nfsd_svc(unsigned short port, int nrservs); int nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp); +int nfsd_nrthreads(void); +int nfsd_nrpools(void); +int nfsd_get_nrthreads(int n, int *); +int nfsd_set_nrthreads(int n, int *); + /* nfsd/vfs.c */ int fh_lock_parent(struct svc_fh *, struct dentry *); int nfsd_racache_init(int); @@ -322,10 +329,8 @@ extern struct timeval nfssvc_boot; (FATTR4_WORD0_SIZE | FATTR4_WORD0_ACL ) #define NFSD_WRITEABLE_ATTRS_WORD1 \ (FATTR4_WORD1_MODE | FATTR4_WORD1_OWNER | FATTR4_WORD1_OWNER_GROUP \ - | FATTR4_WORD1_TIME_ACCESS_SET | FATTR4_WORD1_TIME_METADATA | FATTR4_WORD1_TIME_MODIFY_SET) + | FATTR4_WORD1_TIME_ACCESS_SET | FATTR4_WORD1_TIME_MODIFY_SET) #endif /* CONFIG_NFSD_V4 */ -#endif /* __KERNEL__ */ - #endif /* LINUX_NFSD_NFSD_H */ diff --git a/include/linux/phy.h b/include/linux/phy.h index 779cbcd65f62..02df20f085fe 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -379,6 +379,18 @@ struct phy_driver { }; #define to_phy_driver(d) container_of(d, struct phy_driver, driver) +#define PHY_ANY_ID "MATCH ANY PHY" +#define PHY_ANY_UID 0xffffffff + +/* A Structure for boards to register fixups with the PHY Lib */ +struct phy_fixup { + struct list_head list; + char bus_id[BUS_ID_SIZE]; + u32 phy_uid; + u32 phy_uid_mask; + int (*run)(struct phy_device *phydev); +}; + int phy_read(struct phy_device *phydev, u16 regnum); int phy_write(struct phy_device *phydev, u16 regnum, u16 val); int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id); @@ -386,8 +398,8 @@ struct phy_device* get_phy_device(struct mii_bus *bus, int addr); int phy_clear_interrupt(struct phy_device *phydev); int phy_config_interrupt(struct phy_device *phydev, u32 interrupts); struct phy_device * phy_attach(struct net_device *dev, - const char *phy_id, u32 flags, phy_interface_t interface); -struct phy_device * phy_connect(struct net_device *dev, const char *phy_id, + const char *bus_id, u32 flags, phy_interface_t interface); +struct phy_device * phy_connect(struct net_device *dev, const char *bus_id, void (*handler)(struct net_device *), u32 flags, phy_interface_t interface); void phy_disconnect(struct phy_device *phydev); @@ -427,5 +439,13 @@ void phy_print_status(struct phy_device *phydev); struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id); void phy_device_free(struct phy_device *phydev); +int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, + int (*run)(struct phy_device *)); +int phy_register_fixup_for_id(const char *bus_id, + int (*run)(struct phy_device *)); +int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, + int (*run)(struct phy_device *)); +int phy_scan_fixups(struct phy_device *phydev); + extern struct bus_type mdio_bus_type; #endif /* __PHY_H */ diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index b9e174079002..44c81c744538 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -740,13 +740,13 @@ extern void rtmsg_ifinfo(int type, struct net_device *dev, unsigned change); extern void rtnl_lock(void); extern void rtnl_unlock(void); extern int rtnl_trylock(void); +extern int rtnl_is_locked(void); extern void rtnetlink_init(void); extern void __rtnl_unlock(void); #define ASSERT_RTNL() do { \ - if (unlikely(rtnl_trylock())) { \ - rtnl_unlock(); \ + if (unlikely(!rtnl_is_locked())) { \ printk(KERN_ERR "RTNL: assertion failed at %s (%d)\n", \ __FILE__, __LINE__); \ dump_stack(); \ diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h index d65796dc26d9..5b5369c3c209 100644 --- a/include/linux/seq_file.h +++ b/include/linux/seq_file.h @@ -10,6 +10,7 @@ struct seq_operations; struct file; struct path; struct inode; +struct dentry; struct seq_file { char *buf; @@ -44,6 +45,9 @@ int seq_printf(struct seq_file *, const char *, ...) __attribute__ ((format (printf,2,3))); int seq_path(struct seq_file *, struct path *, char *); +int seq_dentry(struct seq_file *, struct dentry *, char *); +int seq_path_root(struct seq_file *m, struct path *path, struct path *root, + char *esc); int single_open(struct file *, int (*)(struct seq_file *, void *), void *); int single_release(struct inode *, struct file *); diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h index 7a69ca3bebaf..3f632182d8eb 100644 --- a/include/linux/sunrpc/auth.h +++ b/include/linux/sunrpc/auth.h @@ -26,6 +26,7 @@ struct auth_cred { uid_t uid; gid_t gid; struct group_info *group_info; + unsigned char machine_cred : 1; }; /* @@ -59,8 +60,8 @@ struct rpc_cred { /* * Client authentication handle */ -#define RPC_CREDCACHE_NR 8 -#define RPC_CREDCACHE_MASK (RPC_CREDCACHE_NR - 1) +#define RPC_CREDCACHE_HASHBITS 4 +#define RPC_CREDCACHE_NR (1 << RPC_CREDCACHE_HASHBITS) struct rpc_cred_cache { struct hlist_head hashtable[RPC_CREDCACHE_NR]; spinlock_t lock; @@ -89,7 +90,6 @@ struct rpc_auth { /* Flags for rpcauth_lookupcred() */ #define RPCAUTH_LOOKUP_NEW 0x01 /* Accept an uninitialised cred */ -#define RPCAUTH_LOOKUP_ROOTCREDS 0x02 /* This really ought to go! */ /* * Client authentication ops @@ -97,9 +97,7 @@ struct rpc_auth { struct rpc_authops { struct module *owner; rpc_authflavor_t au_flavor; /* flavor (RPC_AUTH_*) */ -#ifdef RPC_DEBUG char * au_name; -#endif struct rpc_auth * (*create)(struct rpc_clnt *, rpc_authflavor_t); void (*destroy)(struct rpc_auth *); @@ -113,6 +111,7 @@ struct rpc_credops { void (*crdestroy)(struct rpc_cred *); int (*crmatch)(struct auth_cred *, struct rpc_cred *, int); + void (*crbind)(struct rpc_task *, struct rpc_cred *); __be32 * (*crmarshal)(struct rpc_task *, __be32 *); int (*crrefresh)(struct rpc_task *); __be32 * (*crvalidate)(struct rpc_task *, __be32 *); @@ -126,9 +125,13 @@ extern const struct rpc_authops authunix_ops; extern const struct rpc_authops authnull_ops; void __init rpc_init_authunix(void); +void __init rpc_init_generic_auth(void); void __init rpcauth_init_module(void); void __exit rpcauth_remove_module(void); +void __exit rpc_destroy_generic_auth(void); +struct rpc_cred * rpc_lookup_cred(void); +struct rpc_cred * rpc_lookup_machine_cred(void); int rpcauth_register(const struct rpc_authops *); int rpcauth_unregister(const struct rpc_authops *); struct rpc_auth * rpcauth_create(rpc_authflavor_t, struct rpc_clnt *); @@ -136,8 +139,8 @@ void rpcauth_release(struct rpc_auth *); struct rpc_cred * rpcauth_lookup_credcache(struct rpc_auth *, struct auth_cred *, int); void rpcauth_init_cred(struct rpc_cred *, const struct auth_cred *, struct rpc_auth *, const struct rpc_credops *); struct rpc_cred * rpcauth_lookupcred(struct rpc_auth *, int); -struct rpc_cred * rpcauth_bindcred(struct rpc_task *); -void rpcauth_holdcred(struct rpc_task *); +void rpcauth_bindcred(struct rpc_task *, struct rpc_cred *, int); +void rpcauth_generic_bind_cred(struct rpc_task *, struct rpc_cred *); void put_rpccred(struct rpc_cred *); void rpcauth_unbindcred(struct rpc_task *); __be32 * rpcauth_marshcred(struct rpc_task *, __be32 *); diff --git a/include/linux/sunrpc/auth_gss.h b/include/linux/sunrpc/auth_gss.h index 67658e17a375..fec6899bf355 100644 --- a/include/linux/sunrpc/auth_gss.h +++ b/include/linux/sunrpc/auth_gss.h @@ -84,6 +84,7 @@ struct gss_cred { enum rpc_gss_svc gc_service; struct gss_cl_ctx *gc_ctx; struct gss_upcall_msg *gc_upcall; + unsigned char gc_machine_cred : 1; }; #endif /* __KERNEL__ */ diff --git a/include/linux/sunrpc/cache.h b/include/linux/sunrpc/cache.h index 03547d6abee5..2d8b211b9324 100644 --- a/include/linux/sunrpc/cache.h +++ b/include/linux/sunrpc/cache.h @@ -120,7 +120,6 @@ struct cache_deferred_req { struct list_head hash; /* on hash chain */ struct list_head recent; /* on fifo */ struct cache_head *item; /* cache item we wait on */ - time_t recv_time; void *owner; /* we might need to discard all defered requests * owned by someone */ void (*revisit)(struct cache_deferred_req *req, diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 129a86e25d29..6fff7f82ef12 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -127,11 +127,12 @@ int rpcb_getport_sync(struct sockaddr_in *, u32, u32, int); void rpcb_getport_async(struct rpc_task *); void rpc_call_start(struct rpc_task *); -int rpc_call_async(struct rpc_clnt *clnt, struct rpc_message *msg, - int flags, const struct rpc_call_ops *tk_ops, +int rpc_call_async(struct rpc_clnt *clnt, + const struct rpc_message *msg, int flags, + const struct rpc_call_ops *tk_ops, void *calldata); -int rpc_call_sync(struct rpc_clnt *clnt, struct rpc_message *msg, - int flags); +int rpc_call_sync(struct rpc_clnt *clnt, + const struct rpc_message *msg, int flags); struct rpc_task *rpc_call_null(struct rpc_clnt *clnt, struct rpc_cred *cred, int flags); void rpc_restart_call(struct rpc_task *); diff --git a/include/linux/sunrpc/gss_krb5.h b/include/linux/sunrpc/gss_krb5.h index 5a4b1e0206e3..a10f1fb0bf7c 100644 --- a/include/linux/sunrpc/gss_krb5.h +++ b/include/linux/sunrpc/gss_krb5.h @@ -70,8 +70,6 @@ enum seal_alg { SEAL_ALG_DES3KD = 0x0002 }; -#define KRB5_CKSUM_LENGTH 8 - #define CKSUMTYPE_CRC32 0x0001 #define CKSUMTYPE_RSA_MD4 0x0002 #define CKSUMTYPE_RSA_MD4_DES 0x0003 @@ -150,9 +148,9 @@ gss_decrypt_xdr_buf(struct crypto_blkcipher *tfm, struct xdr_buf *inbuf, s32 krb5_make_seq_num(struct crypto_blkcipher *key, int direction, - s32 seqnum, unsigned char *cksum, unsigned char *buf); + u32 seqnum, unsigned char *cksum, unsigned char *buf); s32 krb5_get_seq_num(struct crypto_blkcipher *key, unsigned char *cksum, - unsigned char *buf, int *direction, s32 * seqnum); + unsigned char *buf, int *direction, u32 *seqnum); diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index f689f02e6793..d1a5c8c1a0f1 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -11,7 +11,6 @@ #include <linux/timer.h> #include <linux/sunrpc/types.h> -#include <linux/rcupdate.h> #include <linux/spinlock.h> #include <linux/wait.h> #include <linux/workqueue.h> @@ -33,7 +32,8 @@ struct rpc_wait_queue; struct rpc_wait { struct list_head list; /* wait queue links */ struct list_head links; /* Links to related tasks */ - struct rpc_wait_queue * rpc_waitq; /* RPC wait queue we're on */ + struct list_head timer_list; /* Timer list */ + unsigned long expires; }; /* @@ -57,33 +57,25 @@ struct rpc_task { __u8 tk_cred_retry; /* - * timeout_fn to be executed by timer bottom half * callback to be executed after waking up * action next procedure for async tasks * tk_ops caller callbacks */ - void (*tk_timeout_fn)(struct rpc_task *); void (*tk_callback)(struct rpc_task *); void (*tk_action)(struct rpc_task *); const struct rpc_call_ops *tk_ops; void * tk_calldata; - /* - * tk_timer is used for async processing by the RPC scheduling - * primitives. You should not access this directly unless - * you have a pathological interest in kernel oopses. - */ - struct timer_list tk_timer; /* kernel timer */ unsigned long tk_timeout; /* timeout for rpc_sleep() */ unsigned short tk_flags; /* misc flags */ unsigned long tk_runstate; /* Task run status */ struct workqueue_struct *tk_workqueue; /* Normally rpciod, but could * be any workqueue */ + struct rpc_wait_queue *tk_waitqueue; /* RPC wait queue we're on */ union { struct work_struct tk_work; /* Async task work queue */ struct rpc_wait tk_wait; /* RPC wait */ - struct rcu_head tk_rcu; /* for task deletion */ } u; unsigned short tk_timeouts; /* maj timeouts */ @@ -123,6 +115,7 @@ struct rpc_task_setup { const struct rpc_message *rpc_message; const struct rpc_call_ops *callback_ops; void *callback_data; + struct workqueue_struct *workqueue; unsigned short flags; signed char priority; }; @@ -147,9 +140,7 @@ struct rpc_task_setup { #define RPC_TASK_RUNNING 0 #define RPC_TASK_QUEUED 1 -#define RPC_TASK_WAKEUP 2 -#define RPC_TASK_HAS_TIMER 3 -#define RPC_TASK_ACTIVE 4 +#define RPC_TASK_ACTIVE 2 #define RPC_IS_RUNNING(t) test_bit(RPC_TASK_RUNNING, &(t)->tk_runstate) #define rpc_set_running(t) set_bit(RPC_TASK_RUNNING, &(t)->tk_runstate) @@ -171,15 +162,6 @@ struct rpc_task_setup { smp_mb__after_clear_bit(); \ } while (0) -#define rpc_start_wakeup(t) \ - (test_and_set_bit(RPC_TASK_WAKEUP, &(t)->tk_runstate) == 0) -#define rpc_finish_wakeup(t) \ - do { \ - smp_mb__before_clear_bit(); \ - clear_bit(RPC_TASK_WAKEUP, &(t)->tk_runstate); \ - smp_mb__after_clear_bit(); \ - } while (0) - #define RPC_IS_ACTIVATED(t) test_bit(RPC_TASK_ACTIVE, &(t)->tk_runstate) /* @@ -192,6 +174,12 @@ struct rpc_task_setup { #define RPC_PRIORITY_HIGH (1) #define RPC_NR_PRIORITY (1 + RPC_PRIORITY_HIGH - RPC_PRIORITY_LOW) +struct rpc_timer { + struct timer_list timer; + struct list_head list; + unsigned long expires; +}; + /* * RPC synchronization objects */ @@ -204,6 +192,7 @@ struct rpc_wait_queue { unsigned char count; /* # task groups remaining serviced so far */ unsigned char nr; /* # tasks remaining for cookie */ unsigned short qlen; /* total # tasks waiting in queue */ + struct rpc_timer timer_list; #ifdef RPC_DEBUG const char * name; #endif @@ -229,9 +218,11 @@ void rpc_killall_tasks(struct rpc_clnt *); void rpc_execute(struct rpc_task *); void rpc_init_priority_wait_queue(struct rpc_wait_queue *, const char *); void rpc_init_wait_queue(struct rpc_wait_queue *, const char *); +void rpc_destroy_wait_queue(struct rpc_wait_queue *); void rpc_sleep_on(struct rpc_wait_queue *, struct rpc_task *, - rpc_action action, rpc_action timer); -void rpc_wake_up_task(struct rpc_task *); + rpc_action action); +void rpc_wake_up_queued_task(struct rpc_wait_queue *, + struct rpc_task *); void rpc_wake_up(struct rpc_wait_queue *); struct rpc_task *rpc_wake_up_next(struct rpc_wait_queue *); void rpc_wake_up_status(struct rpc_wait_queue *, int); diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index 64c97552964a..4b54c5fdcfd9 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -386,7 +386,6 @@ struct svc_serv * svc_create(struct svc_program *, unsigned int, void (*shutdown)(struct svc_serv*)); struct svc_rqst *svc_prepare_thread(struct svc_serv *serv, struct svc_pool *pool); -int svc_create_thread(svc_thread_fn, struct svc_serv *); void svc_exit_thread(struct svc_rqst *); struct svc_serv * svc_create_pooled(struct svc_program *, unsigned int, void (*shutdown)(struct svc_serv*), diff --git a/include/linux/sunrpc/svcauth.h b/include/linux/sunrpc/svcauth.h index 22e1ef8e200e..d39dbdc7b10f 100644 --- a/include/linux/sunrpc/svcauth.h +++ b/include/linux/sunrpc/svcauth.h @@ -24,6 +24,7 @@ struct svc_cred { }; struct svc_rqst; /* forward decl */ +struct in6_addr; /* Authentication is done in the context of a domain. * @@ -120,10 +121,10 @@ extern void svc_auth_unregister(rpc_authflavor_t flavor); extern struct auth_domain *unix_domain_find(char *name); extern void auth_domain_put(struct auth_domain *item); -extern int auth_unix_add_addr(struct in_addr addr, struct auth_domain *dom); +extern int auth_unix_add_addr(struct in6_addr *addr, struct auth_domain *dom); extern struct auth_domain *auth_domain_lookup(char *name, struct auth_domain *new); extern struct auth_domain *auth_domain_find(char *name); -extern struct auth_domain *auth_unix_lookup(struct in_addr addr); +extern struct auth_domain *auth_unix_lookup(struct in6_addr *addr); extern int auth_unix_forget_old(struct auth_domain *dom); extern void svcauth_unix_purge(void); extern void svcauth_unix_info_release(void *); diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h index 206f092ad4c7..8cff696dedf5 100644 --- a/include/linux/sunrpc/svcsock.h +++ b/include/linux/sunrpc/svcsock.h @@ -26,8 +26,8 @@ struct svc_sock { void (*sk_owspace)(struct sock *); /* private TCP part */ - int sk_reclen; /* length of record */ - int sk_tcplen; /* current read length */ + u32 sk_reclen; /* length of record */ + u32 sk_tcplen; /* current read length */ }; /* diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h index b3ff9a815e6f..4d80a118d538 100644 --- a/include/linux/sunrpc/xprt.h +++ b/include/linux/sunrpc/xprt.h @@ -86,6 +86,10 @@ struct rpc_rqst { unsigned long rq_majortimeo; /* major timeout alarm */ unsigned long rq_timeout; /* Current timeout value */ unsigned int rq_retries; /* # of retries */ + unsigned int rq_connect_cookie; + /* A cookie used to track the + state of the transport + connection */ /* * Partial send handling @@ -152,6 +156,9 @@ struct rpc_xprt { unsigned long connect_timeout, bind_timeout, reestablish_timeout; + unsigned int connect_cookie; /* A cookie that gets bumped + every time the transport + is reconnected */ /* * Disconnection of idle transports @@ -232,7 +239,7 @@ int xprt_unregister_transport(struct xprt_class *type); void xprt_set_retrans_timeout_def(struct rpc_task *task); void xprt_set_retrans_timeout_rtt(struct rpc_task *task); void xprt_wake_pending_tasks(struct rpc_xprt *xprt, int status); -void xprt_wait_for_buffer_space(struct rpc_task *task); +void xprt_wait_for_buffer_space(struct rpc_task *task, rpc_action action); void xprt_write_space(struct rpc_xprt *xprt); void xprt_update_rtt(struct rpc_task *task); void xprt_adjust_cwnd(struct rpc_task *task, int result); @@ -241,6 +248,7 @@ void xprt_complete_rqst(struct rpc_task *task, int copied); void xprt_release_rqst_cong(struct rpc_task *task); void xprt_disconnect_done(struct rpc_xprt *xprt); void xprt_force_disconnect(struct rpc_xprt *xprt); +void xprt_conditional_disconnect(struct rpc_xprt *xprt, unsigned int cookie); /* * Reserved bit positions in xprt->state diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 17a80177a674..c1411189ba6c 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -282,6 +282,7 @@ struct v4l2_pix_format #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */ #define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y','1','6',' ') /* 16 Greyscale */ #define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P','A','L','8') /* 8 8-bit palette */ #define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */ #define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */ @@ -308,6 +309,7 @@ struct v4l2_pix_format /* see http://www.siliconimaging.com/RGB%20Bayer.htm */ #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B','A','8','1') /* 8 BGBG.. GRGR.. */ +#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B','Y','R','2') /* 16 BGBG.. GRGR.. */ /* compressed formats */ #define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M','J','P','G') /* Motion-JPEG */ @@ -793,6 +795,7 @@ struct v4l2_ext_controls /* Values for ctrl_class field */ #define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */ #define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */ +#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */ #define V4L2_CTRL_ID_MASK (0x0fffffff) #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) @@ -849,21 +852,37 @@ struct v4l2_querymenu #define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) #define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) #define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) -#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */ #define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) #define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) #define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) #define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) #define V4L2_CID_GAMMA (V4L2_CID_BASE+16) -#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* ? Not sure */ +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */ #define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) #define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) #define V4L2_CID_GAIN (V4L2_CID_BASE+19) #define V4L2_CID_HFLIP (V4L2_CID_BASE+20) #define V4L2_CID_VFLIP (V4L2_CID_BASE+21) -#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) -#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) -#define V4L2_CID_LASTP1 (V4L2_CID_BASE+24) /* last CID + 1 */ + +/* Deprecated, use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ +#define V4L2_CID_HCENTER_DEPRECATED (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER_DEPRECATED (V4L2_CID_BASE+23) + +#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) +enum v4l2_power_line_frequency { + V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1, + V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2, +}; +#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25) +#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26) +#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27) +#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28) +#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29) +#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30) +/* last CID + 1 */ +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+31) /* MPEG-class control IDs defined by V4L2 */ #define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900) @@ -1051,6 +1070,32 @@ enum v4l2_mpeg_cx2341x_video_median_filter_type { #define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10) #define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11) +/* Camera class control IDs */ +#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) +#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) + +#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1) +enum v4l2_exposure_auto_type { + V4L2_EXPOSURE_AUTO = 0, + V4L2_EXPOSURE_MANUAL = 1, + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; +#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2) +#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3) + +#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4) +#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5) +#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6) +#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7) + +#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8) +#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9) + +#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10) +#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11) +#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12) + /* * T U N I N G */ diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h index 0c82c80b277f..2ca6bae88721 100644 --- a/include/linux/xfrm.h +++ b/include/linux/xfrm.h @@ -97,10 +97,10 @@ struct xfrm_algo { }; struct xfrm_algo_aead { - char alg_name[64]; - int alg_key_len; /* in bits */ - int alg_icv_len; /* in bits */ - char alg_key[0]; + char alg_name[64]; + unsigned int alg_key_len; /* in bits */ + unsigned int alg_icv_len; /* in bits */ + char alg_key[0]; }; struct xfrm_stats { diff --git a/include/media/ir-common.h b/include/media/ir-common.h index a4274203f252..bfee8be5d63f 100644 --- a/include/media/ir-common.h +++ b/include/media/ir-common.h @@ -107,6 +107,7 @@ extern IR_KEYTAB_TYPE ir_codes_avermedia[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_avermedia_dvbt[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_apac_viewcomp[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_pixelview[IR_KEYTAB_SIZE]; +extern IR_KEYTAB_TYPE ir_codes_pixelview_new[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_nebula[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_dntv_live_dvb_t[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_iodata_bctv7e[IR_KEYTAB_SIZE]; @@ -141,8 +142,10 @@ extern IR_KEYTAB_TYPE ir_codes_encore_enltv[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_tt_1500[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_fusionhdtv_mce[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_behold[IR_KEYTAB_SIZE]; +extern IR_KEYTAB_TYPE ir_codes_behold_columbus[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_pinnacle_pctv_hd[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_genius_tvgo_a11mce[IR_KEYTAB_SIZE]; +extern IR_KEYTAB_TYPE ir_codes_powercolor_real_angel[IR_KEYTAB_SIZE]; #endif diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h new file mode 100644 index 000000000000..6a8c8be7a1ae --- /dev/null +++ b/include/media/soc_camera.h @@ -0,0 +1,179 @@ +/* + * camera image capture (abstract) bus driver header + * + * Copyright (C) 2006, Sascha Hauer, Pengutronix + * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef SOC_CAMERA_H +#define SOC_CAMERA_H + +#include <linux/videodev2.h> +#include <media/videobuf-dma-sg.h> + +struct soc_camera_device { + struct list_head list; + struct device dev; + struct device *control; + unsigned short width; /* Current window */ + unsigned short height; /* sizes */ + unsigned short x_min; /* Camera capabilities */ + unsigned short y_min; + unsigned short x_current; /* Current window location */ + unsigned short y_current; + unsigned short width_min; + unsigned short width_max; + unsigned short height_min; + unsigned short height_max; + unsigned short y_skip_top; /* Lines to skip at the top */ + unsigned short gain; + unsigned short exposure; + unsigned char iface; /* Host number */ + unsigned char devnum; /* Device number per host */ + unsigned char buswidth; /* See comment in .c */ + struct soc_camera_ops *ops; + struct video_device *vdev; + const struct soc_camera_data_format *current_fmt; + const struct soc_camera_data_format *formats; + int num_formats; + struct module *owner; + /* soc_camera.c private count. Only accessed with video_lock held */ + int use_count; +}; + +struct soc_camera_file { + struct soc_camera_device *icd; + struct videobuf_queue vb_vidq; + spinlock_t *lock; +}; + +struct soc_camera_host { + struct list_head list; + struct device dev; + unsigned char nr; /* Host number */ + size_t msize; + struct videobuf_queue_ops *vbq_ops; + void *priv; + char *drv_name; + struct soc_camera_host_ops *ops; +}; + +struct soc_camera_host_ops { + struct module *owner; + int (*add)(struct soc_camera_device *); + void (*remove)(struct soc_camera_device *); + int (*set_fmt_cap)(struct soc_camera_device *, __u32, + struct v4l2_rect *); + int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *); + int (*reqbufs)(struct soc_camera_file *, struct v4l2_requestbuffers *); + int (*querycap)(struct soc_camera_host *, struct v4l2_capability *); + int (*try_bus_param)(struct soc_camera_device *, __u32); + int (*set_bus_param)(struct soc_camera_device *, __u32); + unsigned int (*poll)(struct file *, poll_table *); + spinlock_t* (*spinlock_alloc)(struct soc_camera_file *); + void (*spinlock_free)(spinlock_t *); +}; + +struct soc_camera_link { + /* Camera bus id, used to match a camera and a bus */ + int bus_id; + /* GPIO number to switch between 8 and 10 bit modes */ + unsigned int gpio; +}; + +static inline struct soc_camera_device *to_soc_camera_dev(struct device *dev) +{ + return container_of(dev, struct soc_camera_device, dev); +} + +static inline struct soc_camera_host *to_soc_camera_host(struct device *dev) +{ + return container_of(dev, struct soc_camera_host, dev); +} + +extern int soc_camera_host_register(struct soc_camera_host *ici); +extern void soc_camera_host_unregister(struct soc_camera_host *ici); +extern int soc_camera_device_register(struct soc_camera_device *icd); +extern void soc_camera_device_unregister(struct soc_camera_device *icd); + +extern int soc_camera_video_start(struct soc_camera_device *icd); +extern void soc_camera_video_stop(struct soc_camera_device *icd); + +struct soc_camera_data_format { + char *name; + unsigned int depth; + __u32 fourcc; + enum v4l2_colorspace colorspace; +}; + +struct soc_camera_ops { + struct module *owner; + int (*probe)(struct soc_camera_device *); + void (*remove)(struct soc_camera_device *); + int (*init)(struct soc_camera_device *); + int (*release)(struct soc_camera_device *); + int (*start_capture)(struct soc_camera_device *); + int (*stop_capture)(struct soc_camera_device *); + int (*set_fmt_cap)(struct soc_camera_device *, __u32, + struct v4l2_rect *); + int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *); + unsigned long (*query_bus_param)(struct soc_camera_device *); + int (*set_bus_param)(struct soc_camera_device *, unsigned long); + int (*get_chip_id)(struct soc_camera_device *, + struct v4l2_chip_ident *); +#ifdef CONFIG_VIDEO_ADV_DEBUG + int (*get_register)(struct soc_camera_device *, struct v4l2_register *); + int (*set_register)(struct soc_camera_device *, struct v4l2_register *); +#endif + int (*get_control)(struct soc_camera_device *, struct v4l2_control *); + int (*set_control)(struct soc_camera_device *, struct v4l2_control *); + const struct v4l2_queryctrl *controls; + int num_controls; +}; + +static inline struct v4l2_queryctrl const *soc_camera_find_qctrl( + struct soc_camera_ops *ops, int id) +{ + int i; + + for (i = 0; i < ops->num_controls; i++) + if (ops->controls[i].id == id) + return &ops->controls[i]; + + return NULL; +} + +#define SOCAM_MASTER (1 << 0) +#define SOCAM_SLAVE (1 << 1) +#define SOCAM_HSYNC_ACTIVE_HIGH (1 << 2) +#define SOCAM_HSYNC_ACTIVE_LOW (1 << 3) +#define SOCAM_VSYNC_ACTIVE_HIGH (1 << 4) +#define SOCAM_VSYNC_ACTIVE_LOW (1 << 5) +#define SOCAM_DATAWIDTH_8 (1 << 6) +#define SOCAM_DATAWIDTH_9 (1 << 7) +#define SOCAM_DATAWIDTH_10 (1 << 8) +#define SOCAM_PCLK_SAMPLE_RISING (1 << 9) +#define SOCAM_PCLK_SAMPLE_FALLING (1 << 10) + +#define SOCAM_DATAWIDTH_MASK (SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_9 | \ + SOCAM_DATAWIDTH_10) + +static inline unsigned long soc_camera_bus_param_compatible( + unsigned long camera_flags, unsigned long bus_flags) +{ + unsigned long common_flags, hsync, vsync, pclk; + + common_flags = camera_flags & bus_flags; + + hsync = common_flags & (SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_LOW); + vsync = common_flags & (SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_LOW); + pclk = common_flags & (SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING); + + return (!hsync || !vsync || !pclk) ? 0 : common_flags; +} + +#endif diff --git a/include/media/tuner-types.h b/include/media/tuner-types.h index b201371416a0..ab03c5344209 100644 --- a/include/media/tuner-types.h +++ b/include/media/tuner-types.h @@ -6,10 +6,11 @@ #define __TUNER_TYPES_H__ enum param_type { - TUNER_PARAM_TYPE_RADIO, \ - TUNER_PARAM_TYPE_PAL, \ - TUNER_PARAM_TYPE_SECAM, \ - TUNER_PARAM_TYPE_NTSC + TUNER_PARAM_TYPE_RADIO, + TUNER_PARAM_TYPE_PAL, + TUNER_PARAM_TYPE_SECAM, + TUNER_PARAM_TYPE_NTSC, + TUNER_PARAM_TYPE_DIGITAL, }; struct tuner_range { @@ -105,6 +106,7 @@ struct tuner_params { the SECAM-L/L' standards. Range: -16:+15 */ signed int default_top_secam_high:5; + u16 iffreq; unsigned int count; struct tuner_range *ranges; @@ -114,6 +116,13 @@ struct tunertype { char *name; unsigned int count; struct tuner_params *params; + + u16 min; + u16 max; + u32 stepsize; + + u8 *initdata; + u8 *sleepdata; }; extern struct tunertype tuners[]; diff --git a/include/media/tuner.h b/include/media/tuner.h index 1bf24a6ed8f1..77068fcc86bd 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -78,7 +78,7 @@ #define TUNER_HITACHI_NTSC 40 #define TUNER_PHILIPS_PAL_MK 41 -#define TUNER_PHILIPS_ATSC 42 +#define TUNER_PHILIPS_FCV1236D 42 #define TUNER_PHILIPS_FM1236_MK3 43 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */ diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index 032bb75f69c2..0ea0bd85c036 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -153,6 +153,12 @@ enum { V4L2_IDENT_MSP4428G = 44287, V4L2_IDENT_MSP4448G = 44487, V4L2_IDENT_MSP4458G = 44587, + + /* Micron CMOS sensor chips: 45000-45099 */ + V4L2_IDENT_MT9M001C12ST = 45000, + V4L2_IDENT_MT9M001C12STM = 45005, + V4L2_IDENT_MT9V022IX7ATC = 45010, /* No way to detect "normal" I77ATx */ + V4L2_IDENT_MT9V022IX7ATM = 45015, /* and "lead free" IA7ATx chips */ }; #endif diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index f2114459995d..a807d2f86ee8 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -318,6 +318,10 @@ struct video_device int (*vidioc_g_chip_ident) (struct file *file, void *fh, struct v4l2_chip_ident *chip); + /* For other private ioctls */ + int (*vidioc_default) (struct file *file, void *fh, + int cmd, void *arg); + #ifdef OBSOLETE_OWNER /* to be removed soon */ /* obsolete -- fops->owner is used instead */ diff --git a/include/media/videobuf-core.h b/include/media/videobuf-core.h index 99033945cdee..5b39a22533fe 100644 --- a/include/media/videobuf-core.h +++ b/include/media/videobuf-core.h @@ -13,6 +13,9 @@ * the Free Software Foundation; either version 2 */ +#ifndef _VIDEOBUF_CORE_H +#define _VIDEOBUF_CORE_H + #include <linux/poll.h> #ifdef CONFIG_VIDEO_V4L1_COMPAT #include <linux/videodev.h> @@ -123,7 +126,8 @@ struct videobuf_queue_ops { struct videobuf_qtype_ops { u32 magic; - void* (*alloc) (size_t size); + void *(*alloc) (size_t size); + void *(*vmalloc) (struct videobuf_buffer *buf); int (*iolock) (struct videobuf_queue* q, struct videobuf_buffer *vb, struct v4l2_framebuffer *fbuf); @@ -151,7 +155,9 @@ struct videobuf_qtype_ops { struct videobuf_queue { struct mutex vb_lock; spinlock_t *irqlock; - void *dev; /* on pci, points to struct pci_dev */ + struct device *dev; + + wait_queue_head_t wait; /* wait if queue is empty */ enum v4l2_buf_type type; unsigned int inputs; /* for V4L2_BUF_FLAG_INPUT */ @@ -183,9 +189,13 @@ int videobuf_iolock(struct videobuf_queue* q, struct videobuf_buffer *vb, void *videobuf_alloc(struct videobuf_queue* q); +/* Used on videobuf-dvb */ +void *videobuf_queue_to_vmalloc (struct videobuf_queue* q, + struct videobuf_buffer *buf); + void videobuf_queue_core_init(struct videobuf_queue *q, struct videobuf_queue_ops *ops, - void *dev, + struct device *dev, spinlock_t *irqlock, enum v4l2_buf_type type, enum v4l2_field field, @@ -231,10 +241,4 @@ int videobuf_mmap_free(struct videobuf_queue *q); int videobuf_mmap_mapper(struct videobuf_queue *q, struct vm_area_struct *vma); -/* --------------------------------------------------------------------- */ - -/* - * Local variables: - * c-basic-offset: 8 - * End: - */ +#endif diff --git a/include/media/videobuf-dma-sg.h b/include/media/videobuf-dma-sg.h index 38105031db23..be8da269ee33 100644 --- a/include/media/videobuf-dma-sg.h +++ b/include/media/videobuf-dma-sg.h @@ -1,5 +1,5 @@ /* - * helper functions for PCI DMA video4linux capture buffers + * helper functions for SG DMA video4linux capture buffers * * The functions expect the hardware being able to scatter gatter * (i.e. the buffers are not linear in physical memory, but fragmented @@ -68,9 +68,6 @@ struct videobuf_dmabuf { /* for kernel buffers */ void *vmalloc; - /* Stores the userspace pointer to vmalloc area */ - void *varea; - /* for overlay buffers (pci-pci dma) */ dma_addr_t bus_addr; @@ -81,7 +78,7 @@ struct videobuf_dmabuf { int direction; }; -struct videbuf_pci_sg_memory +struct videobuf_dma_sg_memory { u32 magic; @@ -103,11 +100,11 @@ int videobuf_dma_sync(struct videobuf_queue* q,struct videobuf_dmabuf *dma); int videobuf_dma_unmap(struct videobuf_queue* q,struct videobuf_dmabuf *dma); struct videobuf_dmabuf *videobuf_to_dma (struct videobuf_buffer *buf); -void *videobuf_pci_alloc (size_t size); +void *videobuf_sg_alloc(size_t size); -void videobuf_queue_pci_init(struct videobuf_queue* q, +void videobuf_queue_sg_init(struct videobuf_queue* q, struct videobuf_queue_ops *ops, - void *dev, + struct device *dev, spinlock_t *irqlock, enum v4l2_buf_type type, enum v4l2_field field, @@ -117,6 +114,6 @@ void videobuf_queue_pci_init(struct videobuf_queue* q, /*FIXME: these variants are used only on *-alsa code, where videobuf is * used without queue */ -int videobuf_pci_dma_map(struct pci_dev *pci,struct videobuf_dmabuf *dma); -int videobuf_pci_dma_unmap(struct pci_dev *pci,struct videobuf_dmabuf *dma); +int videobuf_sg_dma_map(struct device *dev, struct videobuf_dmabuf *dma); +int videobuf_sg_dma_unmap(struct device *dev, struct videobuf_dmabuf *dma); diff --git a/include/media/videobuf-dvb.h b/include/media/videobuf-dvb.h index 8233cafdeef6..b77748696329 100644 --- a/include/media/videobuf-dvb.h +++ b/include/media/videobuf-dvb.h @@ -27,7 +27,8 @@ struct videobuf_dvb { int videobuf_dvb_register(struct videobuf_dvb *dvb, struct module *module, void *adapter_priv, - struct device *device); + struct device *device, + short *adapter_nr); void videobuf_dvb_unregister(struct videobuf_dvb *dvb); /* diff --git a/include/media/videobuf-vmalloc.h b/include/media/videobuf-vmalloc.h index ec63ab0fab93..aed39460c154 100644 --- a/include/media/videobuf-vmalloc.h +++ b/include/media/videobuf-vmalloc.h @@ -12,6 +12,8 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 */ +#ifndef _VIDEOBUF_VMALLOC_H +#define _VIDEOBUF_VMALLOC_H #include <media/videobuf-core.h> @@ -39,3 +41,5 @@ void videobuf_queue_vmalloc_init(struct videobuf_queue* q, void *videobuf_to_vmalloc (struct videobuf_buffer *buf); void videobuf_vmalloc_free (struct videobuf_buffer *buf); + +#endif diff --git a/include/mtd/Kbuild b/include/mtd/Kbuild index 4d46b3bdebd8..8eb018f96002 100644 --- a/include/mtd/Kbuild +++ b/include/mtd/Kbuild @@ -3,5 +3,4 @@ header-y += jffs2-user.h header-y += mtd-abi.h header-y += mtd-user.h header-y += nftl-user.h -header-y += ubi-header.h header-y += ubi-user.h diff --git a/include/mtd/ubi-header.h b/include/mtd/ubi-header.h deleted file mode 100644 index 292f916ea564..000000000000 --- a/include/mtd/ubi-header.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * Copyright (c) International Business Machines Corp., 2006 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - * the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Authors: Artem Bityutskiy (Битюцкий Артём) - * Thomas Gleixner - * Frank Haverkamp - * Oliver Lohmann - * Andreas Arnez - */ - -/* - * This file defines the layout of UBI headers and all the other UBI on-flash - * data structures. May be included by user-space. - */ - -#ifndef __UBI_HEADER_H__ -#define __UBI_HEADER_H__ - -#include <asm/byteorder.h> - -/* The version of UBI images supported by this implementation */ -#define UBI_VERSION 1 - -/* The highest erase counter value supported by this implementation */ -#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF - -/* The initial CRC32 value used when calculating CRC checksums */ -#define UBI_CRC32_INIT 0xFFFFFFFFU - -/* Erase counter header magic number (ASCII "UBI#") */ -#define UBI_EC_HDR_MAGIC 0x55424923 -/* Volume identifier header magic number (ASCII "UBI!") */ -#define UBI_VID_HDR_MAGIC 0x55424921 - -/* - * Volume type constants used in the volume identifier header. - * - * @UBI_VID_DYNAMIC: dynamic volume - * @UBI_VID_STATIC: static volume - */ -enum { - UBI_VID_DYNAMIC = 1, - UBI_VID_STATIC = 2 -}; - -/* - * Volume flags used in the volume table record. - * - * @UBI_VTBL_AUTORESIZE_FLG: auto-resize this volume - * - * %UBI_VTBL_AUTORESIZE_FLG flag can be set only for one volume in the volume - * table. UBI automatically re-sizes the volume which has this flag and makes - * the volume to be of largest possible size. This means that if after the - * initialization UBI finds out that there are available physical eraseblocks - * present on the device, it automatically appends all of them to the volume - * (the physical eraseblocks reserved for bad eraseblocks handling and other - * reserved physical eraseblocks are not taken). So, if there is a volume with - * the %UBI_VTBL_AUTORESIZE_FLG flag set, the amount of available logical - * eraseblocks will be zero after UBI is loaded, because all of them will be - * reserved for this volume. Note, the %UBI_VTBL_AUTORESIZE_FLG bit is cleared - * after the volume had been initialized. - * - * The auto-resize feature is useful for device production purposes. For - * example, different NAND flash chips may have different amount of initial bad - * eraseblocks, depending of particular chip instance. Manufacturers of NAND - * chips usually guarantee that the amount of initial bad eraseblocks does not - * exceed certain percent, e.g. 2%. When one creates an UBI image which will be - * flashed to the end devices in production, he does not know the exact amount - * of good physical eraseblocks the NAND chip on the device will have, but this - * number is required to calculate the volume sized and put them to the volume - * table of the UBI image. In this case, one of the volumes (e.g., the one - * which will store the root file system) is marked as "auto-resizable", and - * UBI will adjust its size on the first boot if needed. - * - * Note, first UBI reserves some amount of physical eraseblocks for bad - * eraseblock handling, and then re-sizes the volume, not vice-versa. This - * means that the pool of reserved physical eraseblocks will always be present. - */ -enum { - UBI_VTBL_AUTORESIZE_FLG = 0x01, -}; - -/* - * Compatibility constants used by internal volumes. - * - * @UBI_COMPAT_DELETE: delete this internal volume before anything is written - * to the flash - * @UBI_COMPAT_RO: attach this device in read-only mode - * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its - * physical eraseblocks, don't allow the wear-leveling unit to move them - * @UBI_COMPAT_REJECT: reject this UBI image - */ -enum { - UBI_COMPAT_DELETE = 1, - UBI_COMPAT_RO = 2, - UBI_COMPAT_PRESERVE = 4, - UBI_COMPAT_REJECT = 5 -}; - -/* Sizes of UBI headers */ -#define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr) -#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr) - -/* Sizes of UBI headers without the ending CRC */ -#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(__be32)) -#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(__be32)) - -/** - * struct ubi_ec_hdr - UBI erase counter header. - * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC) - * @version: version of UBI implementation which is supposed to accept this - * UBI image - * @padding1: reserved for future, zeroes - * @ec: the erase counter - * @vid_hdr_offset: where the VID header starts - * @data_offset: where the user data start - * @padding2: reserved for future, zeroes - * @hdr_crc: erase counter header CRC checksum - * - * The erase counter header takes 64 bytes and has a plenty of unused space for - * future usage. The unused fields are zeroed. The @version field is used to - * indicate the version of UBI implementation which is supposed to be able to - * work with this UBI image. If @version is greater then the current UBI - * version, the image is rejected. This may be useful in future if something - * is changed radically. This field is duplicated in the volume identifier - * header. - * - * The @vid_hdr_offset and @data_offset fields contain the offset of the the - * volume identifier header and user data, relative to the beginning of the - * physical eraseblock. These values have to be the same for all physical - * eraseblocks. - */ -struct ubi_ec_hdr { - __be32 magic; - __u8 version; - __u8 padding1[3]; - __be64 ec; /* Warning: the current limit is 31-bit anyway! */ - __be32 vid_hdr_offset; - __be32 data_offset; - __u8 padding2[36]; - __be32 hdr_crc; -} __attribute__ ((packed)); - -/** - * struct ubi_vid_hdr - on-flash UBI volume identifier header. - * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC) - * @version: UBI implementation version which is supposed to accept this UBI - * image (%UBI_VERSION) - * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC) - * @copy_flag: if this logical eraseblock was copied from another physical - * eraseblock (for wear-leveling reasons) - * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE, - * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) - * @vol_id: ID of this volume - * @lnum: logical eraseblock number - * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be - * removed, kept only for not breaking older UBI users) - * @data_size: how many bytes of data this logical eraseblock contains - * @used_ebs: total number of used logical eraseblocks in this volume - * @data_pad: how many bytes at the end of this physical eraseblock are not - * used - * @data_crc: CRC checksum of the data stored in this logical eraseblock - * @padding1: reserved for future, zeroes - * @sqnum: sequence number - * @padding2: reserved for future, zeroes - * @hdr_crc: volume identifier header CRC checksum - * - * The @sqnum is the value of the global sequence counter at the time when this - * VID header was created. The global sequence counter is incremented each time - * UBI writes a new VID header to the flash, i.e. when it maps a logical - * eraseblock to a new physical eraseblock. The global sequence counter is an - * unsigned 64-bit integer and we assume it never overflows. The @sqnum - * (sequence number) is used to distinguish between older and newer versions of - * logical eraseblocks. - * - * There are 2 situations when there may be more then one physical eraseblock - * corresponding to the same logical eraseblock, i.e., having the same @vol_id - * and @lnum values in the volume identifier header. Suppose we have a logical - * eraseblock L and it is mapped to the physical eraseblock P. - * - * 1. Because UBI may erase physical eraseblocks asynchronously, the following - * situation is possible: L is asynchronously erased, so P is scheduled for - * erasure, then L is written to,i.e. mapped to another physical eraseblock P1, - * so P1 is written to, then an unclean reboot happens. Result - there are 2 - * physical eraseblocks P and P1 corresponding to the same logical eraseblock - * L. But P1 has greater sequence number, so UBI picks P1 when it attaches the - * flash. - * - * 2. From time to time UBI moves logical eraseblocks to other physical - * eraseblocks for wear-leveling reasons. If, for example, UBI moves L from P - * to P1, and an unclean reboot happens before P is physically erased, there - * are two physical eraseblocks P and P1 corresponding to L and UBI has to - * select one of them when the flash is attached. The @sqnum field says which - * PEB is the original (obviously P will have lower @sqnum) and the copy. But - * it is not enough to select the physical eraseblock with the higher sequence - * number, because the unclean reboot could have happen in the middle of the - * copying process, so the data in P is corrupted. It is also not enough to - * just select the physical eraseblock with lower sequence number, because the - * data there may be old (consider a case if more data was added to P1 after - * the copying). Moreover, the unclean reboot may happen when the erasure of P - * was just started, so it result in unstable P, which is "mostly" OK, but - * still has unstable bits. - * - * UBI uses the @copy_flag field to indicate that this logical eraseblock is a - * copy. UBI also calculates data CRC when the data is moved and stores it at - * the @data_crc field of the copy (P1). So when UBI needs to pick one physical - * eraseblock of two (P or P1), the @copy_flag of the newer one (P1) is - * examined. If it is cleared, the situation* is simple and the newer one is - * picked. If it is set, the data CRC of the copy (P1) is examined. If the CRC - * checksum is correct, this physical eraseblock is selected (P1). Otherwise - * the older one (P) is selected. - * - * Note, there is an obsolete @leb_ver field which was used instead of @sqnum - * in the past. But it is not used anymore and we keep it in order to be able - * to deal with old UBI images. It will be removed at some point. - * - * There are 2 sorts of volumes in UBI: user volumes and internal volumes. - * Internal volumes are not seen from outside and are used for various internal - * UBI purposes. In this implementation there is only one internal volume - the - * layout volume. Internal volumes are the main mechanism of UBI extensions. - * For example, in future one may introduce a journal internal volume. Internal - * volumes have their own reserved range of IDs. - * - * The @compat field is only used for internal volumes and contains the "degree - * of their compatibility". It is always zero for user volumes. This field - * provides a mechanism to introduce UBI extensions and to be still compatible - * with older UBI binaries. For example, if someone introduced a journal in - * future, he would probably use %UBI_COMPAT_DELETE compatibility for the - * journal volume. And in this case, older UBI binaries, which know nothing - * about the journal volume, would just delete this volume and work perfectly - * fine. This is similar to what Ext2fs does when it is fed by an Ext3fs image - * - it just ignores the Ext3fs journal. - * - * The @data_crc field contains the CRC checksum of the contents of the logical - * eraseblock if this is a static volume. In case of dynamic volumes, it does - * not contain the CRC checksum as a rule. The only exception is when the - * data of the physical eraseblock was moved by the wear-leveling unit, then - * the wear-leveling unit calculates the data CRC and stores it in the - * @data_crc field. And of course, the @copy_flag is %in this case. - * - * The @data_size field is used only for static volumes because UBI has to know - * how many bytes of data are stored in this eraseblock. For dynamic volumes, - * this field usually contains zero. The only exception is when the data of the - * physical eraseblock was moved to another physical eraseblock for - * wear-leveling reasons. In this case, UBI calculates CRC checksum of the - * contents and uses both @data_crc and @data_size fields. In this case, the - * @data_size field contains data size. - * - * The @used_ebs field is used only for static volumes and indicates how many - * eraseblocks the data of the volume takes. For dynamic volumes this field is - * not used and always contains zero. - * - * The @data_pad is calculated when volumes are created using the alignment - * parameter. So, effectively, the @data_pad field reduces the size of logical - * eraseblocks of this volume. This is very handy when one uses block-oriented - * software (say, cramfs) on top of the UBI volume. - */ -struct ubi_vid_hdr { - __be32 magic; - __u8 version; - __u8 vol_type; - __u8 copy_flag; - __u8 compat; - __be32 vol_id; - __be32 lnum; - __be32 leb_ver; /* obsolete, to be removed, don't use */ - __be32 data_size; - __be32 used_ebs; - __be32 data_pad; - __be32 data_crc; - __u8 padding1[4]; - __be64 sqnum; - __u8 padding2[12]; - __be32 hdr_crc; -} __attribute__ ((packed)); - -/* Internal UBI volumes count */ -#define UBI_INT_VOL_COUNT 1 - -/* - * Starting ID of internal volumes. There is reserved room for 4096 internal - * volumes. - */ -#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096) - -/* The layout volume contains the volume table */ - -#define UBI_LAYOUT_VOLUME_ID UBI_INTERNAL_VOL_START -#define UBI_LAYOUT_VOLUME_TYPE UBI_VID_DYNAMIC -#define UBI_LAYOUT_VOLUME_ALIGN 1 -#define UBI_LAYOUT_VOLUME_EBS 2 -#define UBI_LAYOUT_VOLUME_NAME "layout volume" -#define UBI_LAYOUT_VOLUME_COMPAT UBI_COMPAT_REJECT - -/* The maximum number of volumes per one UBI device */ -#define UBI_MAX_VOLUMES 128 - -/* The maximum volume name length */ -#define UBI_VOL_NAME_MAX 127 - -/* Size of the volume table record */ -#define UBI_VTBL_RECORD_SIZE sizeof(struct ubi_vtbl_record) - -/* Size of the volume table record without the ending CRC */ -#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(__be32)) - -/** - * struct ubi_vtbl_record - a record in the volume table. - * @reserved_pebs: how many physical eraseblocks are reserved for this volume - * @alignment: volume alignment - * @data_pad: how many bytes are unused at the end of the each physical - * eraseblock to satisfy the requested alignment - * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME) - * @upd_marker: if volume update was started but not finished - * @name_len: volume name length - * @name: the volume name - * @flags: volume flags (%UBI_VTBL_AUTORESIZE_FLG) - * @padding: reserved, zeroes - * @crc: a CRC32 checksum of the record - * - * The volume table records are stored in the volume table, which is stored in - * the layout volume. The layout volume consists of 2 logical eraseblock, each - * of which contains a copy of the volume table (i.e., the volume table is - * duplicated). The volume table is an array of &struct ubi_vtbl_record - * objects indexed by the volume ID. - * - * If the size of the logical eraseblock is large enough to fit - * %UBI_MAX_VOLUMES records, the volume table contains %UBI_MAX_VOLUMES - * records. Otherwise, it contains as many records as it can fit (i.e., size of - * logical eraseblock divided by sizeof(struct ubi_vtbl_record)). - * - * The @upd_marker flag is used to implement volume update. It is set to %1 - * before update and set to %0 after the update. So if the update operation was - * interrupted, UBI knows that the volume is corrupted. - * - * The @alignment field is specified when the volume is created and cannot be - * later changed. It may be useful, for example, when a block-oriented file - * system works on top of UBI. The @data_pad field is calculated using the - * logical eraseblock size and @alignment. The alignment must be multiple to the - * minimal flash I/O unit. If @alignment is 1, all the available space of - * the physical eraseblocks is used. - * - * Empty records contain all zeroes and the CRC checksum of those zeroes. - */ -struct ubi_vtbl_record { - __be32 reserved_pebs; - __be32 alignment; - __be32 data_pad; - __u8 vol_type; - __u8 upd_marker; - __be16 name_len; - __u8 name[UBI_VOL_NAME_MAX+1]; - __u8 flags; - __u8 padding[23]; - __be32 crc; -} __attribute__ ((packed)); - -#endif /* !__UBI_HEADER_H__ */ diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 49c48983019f..e0a612bc9c4e 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -383,6 +383,15 @@ static inline int ipv6_addr_orchid(const struct in6_addr *a) == htonl(0x20010010)); } +static inline void ipv6_addr_set_v4mapped(const __be32 addr, + struct in6_addr *v4mapped) +{ + ipv6_addr_set(v4mapped, + 0, 0, + htonl(0x0000FFFF), + addr); +} + /* * find the first different bit between two addresses * length of address must be a multiple of 32bits diff --git a/include/net/xfrm.h b/include/net/xfrm.h index b56b6a10fe5e..baa9f372cfd1 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -436,6 +436,9 @@ struct xfrm_tmpl /* May skip this transfomration if no SA is found */ __u8 optional; +/* Skip aalgos/ealgos/calgos checks. */ + __u8 allalgs; + /* Bit mask of algos allowed for acquisition */ __u32 aalgos; __u32 ealgos; diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h index 01480581f825..049edc5e6461 100644 --- a/include/sound/ac97_codec.h +++ b/include/sound/ac97_codec.h @@ -397,6 +397,7 @@ #define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */ #define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */ #define AC97_HAS_NO_AUX (1<<18) /* no standard AC97 AUX volume and mute */ +#define AC97_HAS_8CH (1<<19) /* supports 8-channel output */ /* rates indexes */ #define AC97_RATES_FRONT_DAC 0 diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h index 4e80d3fe7381..d293d36a66b8 100644 --- a/include/sound/ak4114.h +++ b/include/sound/ak4114.h @@ -182,6 +182,7 @@ struct ak4114 { unsigned char rcs0; unsigned char rcs1; struct delayed_work work; + unsigned int check_flags; void *change_callback_private; void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1); }; diff --git a/include/sound/ak4xxx-adda.h b/include/sound/ak4xxx-adda.h index 6153b91cdc3e..891cf1aea8b1 100644 --- a/include/sound/ak4xxx-adda.h +++ b/include/sound/ak4xxx-adda.h @@ -68,7 +68,7 @@ struct snd_akm4xxx { enum { SND_AK4524, SND_AK4528, SND_AK4529, SND_AK4355, SND_AK4358, SND_AK4381, - SND_AK5365, NON_AKM + SND_AK5365 } type; /* (array) information of combined codecs */ diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h index 024ce62f7d16..a6e0facf8a37 100644 --- a/include/sound/asoundef.h +++ b/include/sound/asoundef.h @@ -112,6 +112,14 @@ #define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */ #define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /* 50 ppm */ #define IEC958_AES3_CON_CLOCK_VARIABLE (2<<4) /* variable pitch */ +#define IEC958_AES4_CON_MAX_WORDLEN_24 (1<<0) /* 0 = 20-bit, 1 = 24-bit */ +#define IEC958_AES4_CON_WORDLEN (7<<1) /* mask - sample word length */ +#define IEC958_AES4_CON_WORDLEN_NOTID (0<<1) /* not indicated */ +#define IEC958_AES4_CON_WORDLEN_20_16 (1<<1) /* 20-bit or 16-bit */ +#define IEC958_AES4_CON_WORDLEN_22_18 (2<<1) /* 22-bit or 18-bit */ +#define IEC958_AES4_CON_WORDLEN_23_19 (4<<1) /* 23-bit or 19-bit */ +#define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /* 24-bit or 20-bit */ +#define IEC958_AES4_CON_WORDLEN_21_17 (6<<1) /* 21-bit or 17-bit */ /***************************************************************************** * * diff --git a/include/sound/control.h b/include/sound/control.h index e79baa63912f..3dc1291f52db 100644 --- a/include/sound/control.h +++ b/include/sound/control.h @@ -169,4 +169,11 @@ int snd_ctl_boolean_mono_info(struct snd_kcontrol *kcontrol, int snd_ctl_boolean_stereo_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); +/* + * virtual master control + */ +struct snd_kcontrol *snd_ctl_make_virtual_master(char *name, + const unsigned int *tlv); +int snd_ctl_add_slave(struct snd_kcontrol *master, struct snd_kcontrol *slave); + #endif /* __SOUND_CONTROL_H */ diff --git a/include/sound/core.h b/include/sound/core.h index 4fc0235ad784..695ee53488a3 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -277,8 +277,8 @@ int snd_minor_info_done(void); int snd_minor_info_oss_init(void); int snd_minor_info_oss_done(void); #else -#define snd_minor_info_oss_init() /*NOP*/ -#define snd_minor_info_oss_done() /*NOP*/ +static inline int snd_minor_info_oss_init(void) { return 0; } +static inline int snd_minor_info_oss_done(void) { return 0; } #endif /* memory.c */ @@ -310,7 +310,7 @@ int snd_card_file_add(struct snd_card *card, struct file *file); int snd_card_file_remove(struct snd_card *card, struct file *file); #ifndef snd_card_set_dev -#define snd_card_set_dev(card,devptr) ((card)->dev = (devptr)) +#define snd_card_set_dev(card, devptr) ((card)->dev = (devptr)) #endif /* device.c */ @@ -373,7 +373,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) * snd_printd - debug printk * @fmt: format string * - * Compiled only when Works like snd_printk() for debugging purpose. + * Works like snd_printk() for debugging purposes. * Ignored when CONFIG_SND_DEBUG is not set. */ #define snd_printd(fmt, args...) \ @@ -417,7 +417,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) * snd_printdd - debug printk * @format: format string * - * Compiled only when Works like snd_printk() for debugging purpose. + * Works like snd_printk() for debugging purposes. * Ignored when CONFIG_SND_DEBUG_DETECT is not set. */ #define snd_printdd(format, args...) snd_printk(format, ##args) diff --git a/include/sound/mpu401.h b/include/sound/mpu401.h index d45218b44dfe..68b634b75068 100644 --- a/include/sound/mpu401.h +++ b/include/sound/mpu401.h @@ -103,6 +103,21 @@ struct snd_mpu401 { #define MPU401D(mpu) (mpu)->port /* + * control register bits + */ +/* read MPU401C() */ +#define MPU401_RX_EMPTY 0x80 +#define MPU401_TX_FULL 0x40 + +/* write MPU401C() */ +#define MPU401_RESET 0xff +#define MPU401_ENTER_UART 0x3f + +/* read MPU401D() */ +#define MPU401_ACK 0xfe + + +/* */ diff --git a/include/sound/version.h b/include/sound/version.h index fac66c49445a..ed6fb2eb1eac 100644 --- a/include/sound/version.h +++ b/include/sound/version.h @@ -1,3 +1,3 @@ /* include/version.h. Generated by alsa/ksync script. */ -#define CONFIG_SND_VERSION "1.0.16rc2" -#define CONFIG_SND_DATE " (Thu Jan 31 16:40:16 2008 UTC)" +#define CONFIG_SND_VERSION "1.0.16" +#define CONFIG_SND_DATE "" |