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2012-07-03ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400MJason Liu
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00174124: Revert "[USB Host]change the default wakeup value of RH"Peter Chen
This patch creates two bugs at current i.mx usb framework. - The high speed device can't be recognized at the first time. - The usb device can't be recognized after system resume with usb vbus. The reason why it creates bugs that it changes (auto)suspend/resume process for usb core. This reverts commit e5c4318450e1fe7c61950214e779658c6cea0da7. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-07-03ENGR00174103 [usb hsic] add usb hsic support for mx6dlTony LIU
- change the pad setting Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-03ENGR00174037-3 Add HSIC suspend/resume featureTony LIU
head file Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-03ENGR00174037-2 Add HSIC suspend/resume featureTony LIU
device part - implement reset_device interface for HSIC host Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-03ENGR00174037-1 Add HSIC suspend/resume featureTony LIU
MSL part - For HSIC, not connect nor disconnect, then WKCN, WKDC must not be set during suspend - For HSIC, must set bit 21 in host control registry after device connected to host controller - USB PHY 480M clock output must turn on to avoid about 10ms delay before sending out resume signal - HW_ANA_MISC clkgate delay must be set to 2 or 3 to avoid 24M OSCI not stable issue Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-03ENGR00172342-2 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-07-03ENGR00172342-1 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-07-03ENGR00171353 MIPI_DSI: mipi display blank and unblank fail fixedWayne Zou
mipi display blank and unblank fail on HW board: MX6Q_ARM2 1G SN 0112 The host processor sends PCLK, HS and VS information to display modules two frames before sleep-out command is sent. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-03ENGR00174054-2: imx6_defconfig: enable CONFIG_COMPACTIONJason Liu
Enable CONFIG_COMPACTION on imx6_defconfig to reduce the external memory fragementation Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00174054-1: i.mx6_defconfig: sync imx6_defconfig with v3.0.15Jason Liu
After upgrade kernel to 3.0.15, the defconfig also need be updated to sync with the kernel version change Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173962 Added HDMI enable functionSandor Yu
Whenever IPU clock change or gating, the HDMI PHY should reset or config again, otherwise the HDMI PHY will not work. It is the root cause for Ubuntu can't show GUI to HDMI device when bootup and GPU application tutorial4_es20 no output to HDMI device. Added enable function in mxcfb_set_par() to fix aboved two issue. Added HDMI initialization check, only one HDMI instanse supported. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-03ENGR00174039 camera: modify camera driversYuxi Sun
Modify ov3640 ov5640 ov5642 driver according to sensor data structure change for dual camera switch Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-03ENGR00173864 MX6Q ipu capture: add multi camera switchYuxi Sun
Add IOCTRL command V4L2_CID_MXC_SWITCH_CAM for multi camera switch Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-03ENGR00173845 MX6Q SABRESD camera: add camera power down functionYuxi Sun
Add camera power down function and change default camera to ov5642 for parallel interface camera Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-03ENGR00174038 [mx6 mmc]fix build errTony Lin
fix build error: incompatible pointer type Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-07-03ENGR00174031 [MX6Q] Support AR6003 SDIO wifi on kernel v3.0Ryan QIAN
- add macros and struct used in new ath6kl. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-03Add ath6kl cleaned up driverKalle Valo
Last May we started working on cleaning up ath6kl driver which is currently in staging. The work has happened in a separate ath6kl-cleanup tree: http://git.kernel.org/?p=linux/kernel/git/kvalo/ath6kl-cleanup.git;a=summary After over 1100 (!) patches we have now reached a state where I would like to start discussing about pushing the driver to the wireless trees and replacing the staging driver. The driver is now a lot smaller and looks like a proper Linux driver. The size of the driver (measured with simple wc -l) dropped from 49 kLOC to 18 kLOC and the number of the .c and .h files dropped from 107 to 22. Most importantly the number of subdirectories reduced from 26 to zero :) There are two remaining checkpatch warnings in the driver which we decided to omit for now: drivers/net/wireless/ath/ath6kl/debug.c:31: WARNING: printk() should include KERN_ facility level drivers/net/wireless/ath/ath6kl/sdio.c:527: WARNING: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt The driver has endian annotations for all the hardware specific structures and there are no sparse errors. Unfortunately I don't have any big endian hardware to test that right now. We have been testing the driver both on x86 and arm platforms. The code is also compiled with sparc and parisc cross compilers. Notable missing features compared to the current staging driver are: o HCI over SDIO support o nl80211 testmode o firmware logging o suspend support Testmode, firmware logging and suspend support will be added soon. HCI over SDIO support will be more difficult as the HCI driver needs to share code with the wifi driver. This is something we need to research more. Also I want to point out the changes I did for signed endian support. As I wasn't able to find any support for signed endian annotations I decided to follow what NTFS has done and added my own. Grep for sle16 and sle32, especially from wmi.h. Various people have been working on the cleanup, the hall of fame based on number of patches is: 543 Vasanthakumar Thiagarajan 403 Raja Mani 252 Kalle Valo 16 Vivek Natarajan 12 Suraj Sumangala 3 Joe Perches 2 Jouni Malinen Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com> Signed-off-by: Raja Mani <rmani@qca.qualcomm.com> Signed-off-by: Vivek Natarajan <nataraja@qca.qualcomm.com> Signed-off-by: Suraj Sumangala <surajs@qca.qualcomm.com> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jouni Malinen <jouni@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-07-03ENGR00171642 [MX6Q_Lite]Power:suspend and resume stress test failedTony Lin
add bus suspend/resume function to prevent SDMMC suspend/resume stess test fail Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-07-03ENGR00173947-2 MX6Q/ARCH : enable the BBT support to ARM2Huang Shijie
enable the BBT support to ARM2 board. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173947-1 mtd/gpmi : add BBT support to gpmi nand driverHuang Shijie
Add a new field to gpmi_nand_platform_data{}. Make the BBT support to board specific. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.Fugang Duan
Default use RMII 50MHz clock for ts_clk. Test result: Enet work fine at 100/1000Mbps in TO1.1 and Rigel. IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz timestamp clock. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-07-03ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.Fugang Duan
- Fix GPIO_16 IOMUX config. - Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: Enet work fine at 100/1000Mbps in TO1.1. IEEE 1588 timestamp is convergent. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-07-03ENGR00174021 MX6Q/ARCH : fix the section mismatchHuang Shijie
add __init to the gpmi_nand_platform_init() to make this function store in the init.text section. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173926 Support eMMC ddr modeRyan QIAN
- support 4bit/8bit ddr mode - change cpu_is_mx6q() || cpu_is_mx6dl() to cpu_is_mx6() Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-03ENGR00174018 MX6Q/perfmon : fix the compiling errorHuang Shijie
reduce one parameter to fix the built error. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173869-9: i.mx6dl: add the misc drivers supportJason Liu
This patch change is very trivial and simply just add cpu_is_mx6dl() or using cpu_is_mx6 to replace cpu_is_mx6q each driver owner will check it and adjust it accordingly later, such as sdhc etc. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-8: i.mx6: ARM2: add i.mx6dl supportJason Liu
i.mx6dl and i.mx6q share the same ARM2 board due to the pin-pin compatible between them. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-7: i.mx6: sdma: add i.mx6dl supportJason Liu
add i.mx6dl support for sdma Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-6: i.mx6: gpio: add the i.mx6dl supportJason Liu
add the i.mx6dl support for gpio Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-5: i.mx6: don't turn off MMDC clock on i.mx6dlJason Liu
MMDC clock is from pll2_pfd_400M, thus we can't turn it off Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-4: i.mx6: add the i.mx6dl iomux supportJason Liu
externally, i.mx6dl is pin-pin compatible with i.mx6dq internally, i.mx6dl is totally different with iomux setting Checkpatch will throw some warnings in iomux-mx6dl.h file as: WARNING: line over 80 characters But for the readable, I intend not to fix these warnings, and linux upstream also has so many such kind of cases Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() supportJason Liu
In order to support one image for i.mx6q and i.mx6dl, we introduce the below functions by diff the value reading from ANATOP ID register. cpu_is_mx6q() and cpu_is_mx6dl() The layout for the register defines: Major Minor i.MX6Q1.1: 6300 01 i.MX6Q1.0: 6300 00 i.MX6DL1.0: 6100 00 For the common bits shared across all i.mx6 ports, we can use: cpu_is_mx6() for it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-2: i.mx6: add the i.mx6dl memory map and irq definionJason Liu
i.mx6dl shares with almost the same memory layout with i.mx6d/q except it adds some new fetures such as pxp/epdc etc. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173869-1: i.mx6: cosmetic the codeJason Liu
This is the cosmetic patch for the i.mx6 and make the prepartion for the coming i.mx6dl support. Why cosmetic? It's due to the code is a little bit mess and want to make it clean and clear. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-03ENGR00173731-7 MX6Q/GPMI : add gpmi for mx6qHuang Shijie
add gpmi support to mx6q for the imx_3.0.15. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-6 MX6Q/DMA : enable the mxs-dma for mx6qHuang Shijie
enable the mxs-dma for mx6q. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-5 MX6Q/ARCH :rename gpmi-nfc to gpmi-nandHuang Shijie
rename the gpmi-nfc to gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-4 MX6Q/ARCH : add mxs_reset_block()Huang Shijie
add mxs_reset_block() for mx6q. In order to keep the same code as the community, I reduce the parameters to one. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-3 mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()Huang Shijie
[1] Background : The GPMI does ECC read page operation with a DMA chain consist of three DMA Command Structures. The middle one of the chain is used to enable the BCH, and read out the NAND page. The WAIT4END(wait for command end) is a comunication signal between the GPMI and MXS-DMA. [2] The current DMA code sets the WAIT4END bit at the last one, such as: +-----+ +-----+ +-----+ | cmd | ------------> | cmd | ------------------> | cmd | +-----+ +-----+ +-----+ ^ | | set WAIT4END here This chain works fine in the mx23/mx28. [3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should be set not only at the last DMA Command Structure, but also at the middle one, such as: +-----+ +-----+ +-----+ | cmd | ------------> | cmd | ------------------> | cmd | +-----+ +-----+ +-----+ ^ ^ | | | | set WAIT4END here too set WAIT4END here If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state. In the next ECC write page operation, a DMA-timeout occurs. This has been catched in the MX6Q board. [4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(), and use the dma_ctrl_flags: --------------------------------------------------------- DMA_PREP_INTERRUPT : append a new DMA Command Structrue. DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure. --------------------------------------------------------- [5] changes to the relative drivers: For gpmi-nand driver: use the new flags. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-2 mxs-dma : use the new mxs-dma.hHuang Shijie
use the new header : mxs-dma.h. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173731-1 mxs-dma : rename the dma.h for mxs-dmaHuang Shijie
Move the header to a more common place. The mxs dma engine is not only used in mx23/mx28, but also used in mx50/mx6q. It will also be used in the future chips. rename it to mxs-dma.h Acked-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-03ENGR00173615 [mx5 mmc]fix mx5 build errorTony Lin
fix build error on mx5 platforms Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-07-03ENGR00173615-2 [mx6q mmc]remove software workaround for TO1.1 and laterTony Lin
the card interrupt status bit workaround and TC interrupt comes earlier than DMA interrupt workaround are not necessary for i.MX6Q TO1.1 and later Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-07-03ENGR00173615-1 [mx6q]add mx6q_revision to common header fileTony Lin
the common API is needed by drivers to distinguish TO version Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-07-03ENGR00173939 [MX6Q]: Skip sending S18R on SD slots doesnt support 1.8VRyan QIAN
- checking whether host support MMC_VDD_165_195, before query UHS mode supported by host controller. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-03ENGR00173846 MX6DQ_SD: add touch support for LVDS0 and LVDS1Frank Li
Add touch support. Signed-off-by: Frank Li <Frank.Li@freescale.com>
2012-07-03ENGR00173288-02 merge "[MX6Q]add SDHC3.0 support on uSDHC controller"Ryan QIAN
ENGR152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller add voltage switch function due to SDHC3.0 spec requirement add tuning function due to SDHC3.0 spec requirement extend some functions to support SDR50 & SDR104 speed mode - adjust the sequence of current_limit and bus_speed_mode - add FSL specific tuning procedure Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-03ENGR00173288-01 merge "[MX6Q]add SDHC3.0 support on uSDHC controller"Ryan QIAN
ENGR152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller add voltage switch function due to SDHC3.0 spec requirement add tuning function due to SDHC3.0 spec requirement extend some functions to support SDR50 & SDR104 speed mode - add support for SD3.0. - add workaround for accessing non-exist registers on FSL SDHC. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-03ENGR00173639 mx6q: clock: PLL3's power can be off at runtime at TO1.1Peter Chen
It is the fix for Design PDM TKT064178, IC has already verified it, and no more power consumption for setting/clear this bit. With this bit, the power of pll3 can be off even the power bit for pll3 is on. In order to support USB wakeup, the power bit for pll3 should be always on, and the power of pll3 is controller by USB hardware and this new added bit at runtime. Signed-off-by: Peter Chen <peter.chen@freescale.com>
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