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At chipidea revision 2.40a, there is a below errata:
9000531823 B2-Medium Adding a dTD to a Primed Endpoint May Not Get Recognized
Title: Adding a dTD to a Primed Endpoint May Not Get Recognized
Impacted Configuration: All device mode configurations.
Description:
There is an issue with the add dTD tripwire semaphore (ATDTW bit in USBCMD register)
that can cause the controller to ignore a dTD that is added to a primed endpoint.
When this happens, the software can read the tripwire bit and the status bit at '1'
even though the endpoint is unprimed.
After executing a dTD, the device controller endpoint state machine executes a final
read of the dTD terminate bit to check if the application added a dTD to the linked
list at the last moment. This read is done in the finpkt_read_latest_next_td (44) state.
After the read is performed, if the terminate bit is still set, the state machine moves
to unprime the endpoint. The decision to unprime the endpoint is done in the
checkqh_decision (59) state, based on the value of the terminate bit.
Before reaching the checkqh_decision state, the state machine traverses the
writeqhtd_status (57), writeqh_status (56), and release_prime_mask (42) states.
As shown in the waveform, the ep_addtd_tripwire_clr signal is not set to clear
the tripwire bit in these states.
Workaround:
The software must implement a periodic poll cycle, and check for each dTD
pending on execution (Active = 1), if the enpoint is primed. It can do this by reading
the corresponding bits in the ENDPTPRIME and ENDPTSTAT registers. If these bits are
read at 0, the software needs to re-prime the endpoint by writing 1 to the corresponding
bit in the ENDPTPRIME register. This can be done for every microframe, every frame or
with a larger interval, depending on the urgency of transfer execution for the application.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Define ci_get_revision API to know the controller revision
information according to chipidea 1.1a, 2.0a, 2.4 and 2.5a
spec. Besides, add one entry in struct ci_hdrc to indicate
revision information. This can be used for adding different
code for revisions, implementing erratas.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Using hw_write_id_reg and hw_read_id_reg to write and read
identification registers contents. This can be used to get
controller information, change some system configurations
and so on.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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This reverts commit 068ecdab500e551f313cd6b08dccc32c9d55e137.
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Currently the Vybrid USB client does not work reliably
with usb gadget ethernet. This patch forces usage of
only a single transfer descriptor for the dTD list which
seems to work reliably well for now. Does not fix the
underlying issue and is only temporary.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add proper device tree support for SEMA4 driver. Also rename the
source and header file to the mainline SoC name "vf610_".
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Extend the MSCM driver with CPU2CPU interrupt support. Those
interrupts are mainly used for the external MCC kernel module
which uses the functionality to pass messages to the secondary
Cortex-M4 core.
In Timesys version (at least up to 1.06), the interrupt handling
was directly done in the MCC kernel module. However, because newer
kernels use virtual interrupt numbers, it is not possible to use
hardcoded hardware IRQ number by default. By requesting the
interupts within the MSCM driver and exporting some helper
functions.
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Add the CPU2CPU interrupt to the MSCM module.
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Add SEMA4 module which is used by the SEMA4 arch driver which in
turn is needed for the MCC out-of-tree kernel module.
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Currently there is no driver which uses SRAM. Also, loading of the
external MCC kernel module fails when SRAM locations are already
in use.
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Since we only support STOP mode, SRAM is currently not required
for suspend mode. Move the pm_info struct to DDR RAM and don't try
to allocate SRAM.
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Add TouchRevolution multitouch controller driver which is connectable
over I2C bus. The driver supports the 7" and 10" multitouch variant
by TouchRev.
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The pixel clock polarity setting was still wrong: In contrast what
earlier mentioned, the reference manual is correct! But the kernel
display flags are rather somewhat confusing: The flags specify the
edge where the data should be driven by the controller (and hence not
sampled by the display!). We convert the display flag to the display
centric DCU notation when getting the videomode from device tree.
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Conflicts:
drivers/input/touchscreen/Makefile
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Use level triggered interrupt which makes sure that even we miss a
rising edge (due to latencies in the kernel), the interrupt still
will be handled later, and doesn't freeze the input device.
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Add device tree integration and add the device to the dtb.
i2c device, interrupt and reset GPIO can be specified in the dts as follows:
Note that additionally you may have to set the pinmuxing for the pins to
be GPIO.
&i2c1 {
status = "okay";
pcap@10 {
/* TouchRevolution Fusion 7 and 10 multi-touch controller */
compatible = "touchrevolution,fusion-f0710a";
reg = <0x10>;
gpios = <&gpio6 10 0 /* MXM-11, Pen down interrupt */
&gpio6 9 0 /* MXM-13, Reset interrupt */
>;
};
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Use platform independent description for requested GPIOs.
(cherry picked from commit c300f3a605f8984449c1a5324fd3edda6f2fd8ff)
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Fix chip reset by sleeping long enought after reset. Do proper error
handling (free GPIO on failure). Use dev_* for message logging to get
similar messages for all fusion driver related errors and warnings.
(cherry picked from commit 63b293000723e61a880470f093fbe82e86ebd81b)
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To avoid warnings use the new I2C power management function for
suspend and resume.
(cherry picked from commit 9d996316a470d37fb71c521f27106b014f3f0b23)
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Added platform data struct to define interrupt and reset GPIO. This
allows to initialize the touchscreen controller inside the driver
rather then in each platform and use the driver as a module.
(cherry picked from commit cb82730b70f31af3b43041ac4e47de69c18016c9)
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When the next interrupt request apeares between the confirmation of
the previous (a write via I2C, fusion_F0710A_write_complete) and
the reenable of the GPIO interrupt, the driver hangs and no more
touch inputs are reported.
This patch moves the confirmation after the reenabling of the GPIO
interrupt.
(cherry picked from commit e95019a4f20b8cdfbe03658e4f73b69cdcf97540)
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Recent evdev X-Server input driver implementation complain when
only multitouch axes have been reported ("found only multitouch-axes.
That shouldn't happen."). Therefor also report the primary touch
detection with default axis.
(cherry picked from commit dda7a631ac901e4d140e8a6612c5c6b5506b6a91)
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This patch adds the multi-touch input driver for the TouchRevolution
Fusion 7 and 10 panels (See Fusion 7 and 10 drivers for Linux.pdf and
Linux Drivers Fusion 10.zip) as downloaded in 07.2014
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- Remove unnecessary PMIC drivers
- Remove debug configs
- Add Overlay FS by default
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Linux 3.18
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This driver controls the hardware sema4 on the Vybrid Tower. The MCC kernel
module uses this driver to control access to shared RAM.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Conflicts:
arch/arm/boot/dts/vf500.dtsi
arch/arm/boot/dts/vfxxx.dtsi
arch/arm/configs/imx_v6_v7_defconfig
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To enable proper routable interrupt controller support for
the GIC driver, the routable-irqs need to be specified.
Hence add the routable-irqs property with the amount of
IRQs supported by the GIC controller on the Vybrid SoC.
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mach-imx directly references to the irq field in
struct irq_data, and uses this to directly poke hardware register.
But irq is the *virtual* irq number, something that has nothing
to do with the actual HW irq (stored in the hwirq field). And once
we put the stacked domain code in action, the whole thing explodes,
as these two values are *very* different.
Just replacing all instances of irq with hwirq fixes the issue.
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
arch/arm/mach-imx/gpc.c
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This adds support for Vybrids interrupt router for the shared
peripherals. The interrupt router is between the peripherals
and the GIC (IRQ controller of the Cortex-A5 CPU) or NVIC (IRQ
controller of the Cortex-M4 CPU) respectively. Hence, for every
IRQ we enable, we need to make sure the interrupt router routes
the IRQ to the current CPU. This driver currently only support
MSCM on the Cortex-A5 (in conjunction with GIC). Also, most
U-Boot versions for Vybrid configure the MSCM to route all
interupts to Cortex-A5 by default.
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Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoCs. This module contains the peripheral
interrupt router, which is handling the routing of the interrupts
between the two cores.
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In order to allow wake support in STOP sleep mode, clocks are
needed. Use imx_clk_gate2_cgr to disable automatic clock gating
in low power mode STOP. This allows to enable wake by UART using:
echo enabled > /sys/class/tty/ttyLP0/power/wakeup
However, if wake is not enabled, the driver should disable the
clocks explicitly to save power.
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When entering suspend while the device is in runtime PM, the
sdhci_[suspend|resume]_host function are called without taking
care of runtime PM. On the Vybrid SoC, this leads to external
abort because during runtime suspend, the clocks required for
bus access are disabled.
[ 37.772967] Unhandled fault: imprecise external abort (0x1c06) at 0x76f5f000
[ 37.780304] Internal error: : 1c06 [#1] ARM
[ 37.784670] Modules linked in:
[ 37.787908] CPU: 0 PID: 428 Comm: sh Not tainted 3.18.0-rc5-00119-geefd097-dirty #1540
[ 37.796142] task: 8e246c00 ti: 8ca6c000 task.ti: 8ca6c000
[ 37.801785] PC is at esdhc_writel_le+0x40/0xec
[ 37.806431] LR is at sdhci_set_card_detection+0xe0/0xe4
[ 37.811877] pc : [<803f0584>] lr : [<803eaaa0>] psr: 400f0013
[ 37.811877] sp : 8ca6dd28 ip : 00000001 fp : 8ca6dd3c
[ 37.823766] r10: 807a233c r9 : 00000000 r8 : 8e8b7210
[ 37.829194] r7 : 802d8a08 r6 : 8082e928 r5 : 00000000 r4 : 00000002
[ 37.835974] r3 : 8ea34e90 r2 : 00000038 r1 : 00000000 r0 : 8ea32ac0
...
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This patch adds initial suspend/resume support for Vybrid SoC.
The standby sleep state puts the module in STOP mode which
allows to the SoC to be woken by a regular interrupt. To save
power the main PLL1 is bypassed and uses the 24MHz on-chip
oscillator. However, memory clock need to be at full speed,
hence use PLL2 only to keep memory clock. This provides the
best balance between low-power requirement while have the
ability to use any IRQ as wake-up source.
The mem sleep state (Suspend-to-RAM) is currently not supported.
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The 2-bit gates found i.MX and Vybrid SoC support different clock
configuration:
0b00: clk disabled
0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
0b11: clk enabled in RUN and WAIT mode
For some clocks, we might want to configure different behaviour,
e.g. a memory clock should be on even in STOP mode. Add a new
function imx_clk_gate2_cgr which allow to configure specific
gate values through the cgr_val parameter.
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Support Vybrid SoC which has a similar global power controller
found in i.MX6 SoC's. The extension for the GIC interrupt
controller can be reused. However, Vybrid's GPC has no CPU
powerdown flag, hence we write this conditional.
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Enable GPIO wakeup key on Vybrid PAD 41 which is routed to the
Colibri default wakeup pin SO-DIMM 45.
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Add global power controller module (GPC) to Vybrid device tree.
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The alarm interrupt handler also reads registers which are part of SNVS and
need clocks enabled. However, the resume function is called after IRQ's
have been enabled, hence this leads to a abort:
[ 90.755222] Unhandled fault: external abort on non-linefetch (0x1008)
at 0x908c604c
[ 90.762892] Internal error: : 1008 [#1] ARM
[ 90.767082] Modules linked in:
[ 90.770174] CPU: 0 PID: 421 Comm: sh Not tainted 3.18.0-rc5-00135-g0689c67-dirty #1592
[ 90.778100] task: 8e03e800 ti: 8cad8000 task.ti: 8cad8000
[ 90.783530] PC is at snvs_rtc_irq_handler+0x14/0x74
[ 90.788424] LR is at handle_irq_event_percpu+0x3c/0x144
Fix this by using the .{suspend/resume}_noirq callbacks instead of
.{suspend/resume} .
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add suspend and resume support which disables the panel completely.
Tested with the main frame buffer instance (fb0).
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