summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-08-24MGS-2302-1 [#imx-225] fix the gpu1 hang with independent modeXianzhong
when the app is killed, the kernel driver will free database from the gpu0. if the app is running on gpu1, its database may be freed by gpu0 unexpectely. need check kernel pointer in record to prevent the incorrect database free. Date: Oct 17, 2016 Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MGS-2388 [#ccc] integrate 6.2.0 post patchXianzhong
apply the gpu hang patch for multiple instances 001-IMX101-15870-04-cl81286-Fixed-ES31-CTS.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_write_calls-hang.patch apply the debug patch for gpu module clock 0014-cl83047-added-debug-control-for-new-module-s-clock-gating.patch Date: Nov 11, 2016 Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2018-08-24MGS-1972 [#imx-142] Enable GPU MMU flat mapping to cover CMA range on DVYong Gan
Limited baseAddress offset only for GPU without MC20 feature. Date: Oct 14, 2016 Signed-off-by: Yong Gan <yong.gan@nxp.com>
2018-08-24MLK-13442: mmc: sdhci-esdhc-imx: release bus frequency when usdhc removeHaibo Chen
When usdhc driver remove, also need to release bus frequency. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2018-08-24MLK-13287 ARM: dts: imx: support for epop 6sxscm evb boardAlejandro Sierra
Add support for the epop i.MX6SX SCM EVB board The epop variant contains an eMMC(512MB) within the POP package. Support the next features for epop 6sxscm EVB: - Regular epop board - M4 support Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13286 ARM: dts: imx: support emmc on 6sxscm platformsAlejandro Sierra
Add the generic dtsi configuration to support EMMC on the i.MX6SX SCM platforms Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13284 ARM: dts: imx: generic support for 6sxscm 512mb evbJuan Gutierrez
Add the generic dtsi configuration support for the i.MX6SX SCM platforms with 512MB of DDR memory mapping. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13283 ARM: dts: imx: support for 1gb 6sxscm evb boardAlejandro Sierra
Add support for the 1gb i.MX6SX SCM EVB board Support the next features for 1Gb 6sxscm EVB: - Regular 1gb board - M4 support - MQS - SAI sound card - LCD and HDMI with sii902x support - Bluetooth and Wifi Murata ZP SDIO dongle Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13282 ARM: dts: imx: generic dts support for 6sxscm evbJuan Gutierrez
Add the generic dts configuration support, including BT and Wifi for the i.MX6SX SCM Evaluation Board (EVB) - Generic DTS for 6SXSCM EVB - Bluetooth and Wifi - LDO enabled Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13421 ARM: dts: imx6sll: correct the wrong compatible name in imx6sll.dtsiRobin Gong
The initial version is wrong, fix it. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2018-08-24MLK-13281 ARM: imx: add micrel phy init for 6sxscm evb boardAlejandro Sierra
Add Micrel phy initialization for imx6sxscm evb platform Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13280 ARM: imx: missing mmdc read fifo reset on resumeJuan Gutierrez
When a device like (USB, CAMM, tty, etc) prevents the megamix domain to power down during the suspend process (by enabling a wakeup source) the resume process goes through a path where the MMDC context should not be restored. However this resume path does not reset the read fifo MMDCx_MPDGCTRL0[RST_RD_FIFO] for the platforms with LPDDR2 causing a bad resuming and reset of the device due to an exception. This patch adds the reset_read_fifo on the No-restoring-MMDC path to fix the bad resuming. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2018-08-24MLK-13279 rpmsg: imx: make vring address configurable by dtsJuan Gutierrez
vring memory address was hardcoded at the top of the 1GB RAM. For systems with a memory map with less or different than 1GB, the hardcoded value might be not correct and cause issues. This patch add the support to pass the vring address from device tree configuration on the reg platform argument in the following format: reg = <vring_address vring_size> For example, for a 512MB system, with the rpmgs vring placed at top of the memory the configuration will look like below: &rpmsg{ reg = <0x9FFF0000 0x8000>; }; Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13413 ARM: imx6sll-evk: add Murata Type ZP (BCM4339) module supportAndy Duan
Add Murata Type ZP (BCM4339) module support on i.MX6SLL platforms: - i.MX6SLL EVK (SD3 slot + BT connector) + Murata adapter V2.0 Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2018-08-24Revert "ARM: imx: Added perf functionality to mmdc driver"Jason Liu
This reverts commit 3d7dd5ec903bc867c0274ac871b707839712f832. This commit is wrongly pushed and also it breaks build, revert it. Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2018-08-24MLK-13248 ARM: dts: imx: add support for 1gb evb boardAlejandro Sierra
Add support for SCM i.MX6DQ 1Gb Evaluation Board (EVB). Support the next features for 1Gb EVB boards: - Support for fix and interleave mode - For fix mode additional dts are provided for: - hdcp - enetirq - bluetooth and wifi for Murata ZP SDIO dongle Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13247 ARM: dts: imx: add support for 1gb qwks boardJuan Gutierrez
Add support for SCM i.MX6DQ 1Gb Quick Start Board (QWKS). Support the next features for 1Gb QWKS boards: - Support for fix and interleave mode - For fix mode additional dts are provided for - hdcp - Wifi with Murata ZP SDIO dongle Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13246 ARM: dts: imx: generic support for 6dqscm 1gb boardJuan Gutierrez
Add the generic dtsi configuration support for the SCM i.MX6DQ QWKS and EVB board with 1GB of DDR memory mapping Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13245 ARM: dts: imx: generic dtsi support for qwks boardJuan Gutierrez
Add the generic dtsi configuration support, including Wifi, for the SCM i.MX6DQ Quick Start Board (QWKS) Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24MLK-13244 input: touchscreen: add support for vtl touchscreenAlejandro Lozano
Add the support for a CT36X based touchscreens using the CT36X controller and i2c touchscreen interface. Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com> Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
2018-08-24ARM: imx: Added perf functionality to mmdc driverZhengyu Shen
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but this driver only supports i.MX6 Quad at the moment. MMDC provides registers for performance counters which read via this driver to help debug memory throughput and similar issues. $ perf stat -a -e mmdc/busy-cycles/,mmdc/read-accesses/,mmdc/read-bytes/,mmdc/total-cycles/,mmdc/write-accesses/,mmdc/write-bytes/ dd if=/dev/zero of=/dev/null bs=1M count=5000 Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=5000': 898021787 mmdc/busy-cycles/ 14819600 mmdc/read-accesses/ 471.30 MB mmdc/read-bytes/ 2815419216 mmdc/total-cycles/ 13367354 mmdc/write-accesses/ 427.76 MB mmdc/write-bytes/ 5.334757334 seconds time elapsed Signed-off-by: Zhengyu Shen <zhengyu.shen@nxp.com> Signed-off-by: Frank Li <frank.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-08-24MLK-13409 ARM: config: add imx6sll support in imx_v7 mfg defconfigBai Ping
Add i.MX6SLL support in imx_v7_mfg_defconfig. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13358 mmc: sdhci-esdhc-imx: make sure usdhc clock enabled while doing ↵Haibo Chen
suspend When suspend usdhc, it will access usdhc register. So usdhc clock should be enabled, otherwise the access usdhc register will return error or cause system. Take this into consideration, if system enable a usdhc and do not connect any SD/SDIO/MMC card, after system boot up, this usdhc will do runtime suspend, and close all usdhc clock. At this time, if suspend the system, due to no card persent, usdhc runtime resume will not be called. So usdhc clock still closed, then in suspend, once access usdhc register, system hung or bus error return. This patch make sure usdhc clock always enabled while doing usdhc suspend. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2018-08-24MLK-13387-4 ARM: imx: gpcv2: correct pcie phy reg notifierRichard Zhu
1.8v of imx7d pcie phy, should be turned on after the 1p0d(1.0v) of pcie phy is turned on. And turned off before the 1p0d(1.0v) of pcie phy is turned off Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-13387-3 regulator: consumer: add new event macroRichard Zhu
Add one new regulator events macro 'REGULATOR_EVENT_AFT_DO_ENABLE'. 1.8v of imx7d pcie phy, should be turned on after the 1p0d(1.0v) of pcie phy is turned on. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-13387-2 regulator: consumer: add new event macroRichard Zhu
Add the AFT_ENABLE event macros, because that 1.8v of imx7d pcie phy, should be turned on after the 1p0d(1.0v) of pcie phy is turned on. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-13387-1 ARM: dts: imx7d: use enable bit of 1p0dRichard Zhu
Do not set the override bit of 1p0d regulator. Because, the 1p0d and the vdd1.8v should be turned on separately by the requirements of the imx7d pcie phy. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-13365 pci: imx: fix imx6dl ep rc validation failureRichard Zhu
The ep rc validation is failed on imx6dl. Root cause: The ref clk of imx6dl pcie is 100M(bit20 of PLL_ENET). But the driver doesn't enable it. Solution: enable pci_bus clock in ep rc validation system, since the parent of the pci_bus is the 100M. The connection between ep and rc only have the TX/RX parirs, there is no impaction when enable the pcie_bus in pcie ep rc validation system. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2018-08-24MLK-13390 ARM: dts: imx6sll: add V4L2 output supportRobby Cai
Add PXP V4L2 output support Signed-off-by: Robby Cai <robby.cai@nxp.com>
2018-08-24MLK-13389 ARM: imx6sll-evk: enable USBOTG1Peter Chen
Enable USBOTG1 Signed-off-by: Peter Chen <peter.chen@nxp.com>
2018-08-24MLK-13384 ARM: imx: remove ldo bypass check on imx6sllBai Ping
As on i.MX6SLL, there is no ARM LDO, the code for ARM LDO bypass check is unnecessary, remove these piece of code in i.MX6SLL low power idle. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13366 mmc: sdhci-esdhc-imx: no need busfreq for imx6qdlHaibo Chen
This reverts commit 2c01452f4d7c0f65553b365adc27a1b7b6ba8644. Besides, add other SoC request high bus freq. This is because only imx6qdl do not implement low bus idle, so imx6qdl can work well under low power mode without request high bus freq which also can save power. For other SoC, need to request high bus freq when usdhc is active. Also can refer to commit 312979d1fcbd.
2018-08-24MLK-13361-3 arm: imx6q: busfreq: restore mmdc timing settings for 100MHzJuan Gutierrez
The timing settings for 100MHz are almost the same as the ones for 400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be set to 2 cycles. For the 100MHz case the restoration of the mmdc setting should be performed in 2 steps: restore the mmdc setting and then overwrite the RALAT setting for 2 cycles. A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added to go to the "equal to 100MHz" or to the "lower to 100MHz" case Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com>
2018-08-24MLK-13361-2 arm: imx6q: busfreq: wrap ralat settings on a macroJuan Gutierrez
Setting the Read Additional Latency (RALAT) to 2 cycles, MMDCx_MDMISC[RALAT] = 2, is needed for 24MHz operation point. Currently this is set within the "set_timings_below_100MHz_operation" macro, which is use for the 24MHz case. In order to provide a generic way for setting RALAT=2 the code is wrapped in this new macro: "set_mmdc_misc_ralat_2_cycles", so other set points (besides the below 100MHz case) can reuse this code. As an example, for 100Mhz operation the RALAT should be set to 2 cycles, however, the rest of the MMDCFG parameter are not the same as in the "below_100MHz" case. So, this macro can be reused for its RALAT part. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13361-1 arm: imx6q: busfreq: rename 100MHz-related macrosJuan Gutierrez
Two macros are renamed: 1) set_timings_above_100MHz_operation as restore_mmdc_settings_info 2) mmdc_clk_lower_100MHz as mmdc_clk_lower_equal_100MHz For (1) the operation is generic to several cases and not just related (at least on a semantic way) with the operations "above" 100MHz Renamed as restore_mmdc_settings_info the macro can be reused for the other cases like equal to 100MHz and possibly other intermediate operation points. For (2), the macro is renamed as mmdc_clk_lower_equal_100MHz to reflect that this macro handles both the "lower than 100 MHz" case and the "equal to 100MHz" case. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13340 dts: mx6ul-lpddr2-arm2: fix sd gpio polarityDong Aisheng
system can't detect SD card due to wrong gpio polarity. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
2018-08-24MLK-13369-2: ARM: dts: Add more parameters for gpr property of soundShengjiu Wang
The new parameter description is: gpr = <gpr-node, register-offset, mask, value>; Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2018-08-24MLK-13369-1: ASoC: fsl: fix the hard code gpr address in machine driverShengjiu Wang
There is hard code for gpr address in machine driver, imx-wm8960 and imx-wm8958, when the sai interface changed to sai1 or sai3, there will be issue, so remove the hard code, use the property from the device tree. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
2018-08-24MLK-13362 ARM: imx: fix audio bus mode hang on imx6sx/ul/sllBai Ping
When MMDC runs at a low frequency, it is not recommended to perform "force measurement", the MMDC measure unit may return a wrong measurement value when running below 100MHz. Additionally, the double MU count operations should be only done when changing the MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz). Otherwise, the MU count may overflow and lead to system hang issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13344-05 ARM: imx: Add cpuidle support on imx6sllBai Ping
Add low power idle support on i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13344-04 ARM: imx: Add busfreq support on imx6sllBai Ping
Add bufreq driver support on i.MX6SLL. For i.MX6SLL, it only support LPDDR2 and LPDDR3. the DDR clock change flow is same on these two type of DDR. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13344-03 ARM: dts: imx: add busfreq node on imx6sllBai Ping
Add busfreq device node for i.MX6SLL. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13344-02 ARM: dts: imx: update the setpoints on imx6sllBai Ping
According to datasheet Rev.B,06/2016 of i.MX6SLL. It has below setpoints support: 996MHz 1.2V 792MHz 1.15V 396MHz 1.05V 198MHz 0.95V We add a 25mV margin to cover the IR drop and board tolerance. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13344-01 ARM: imx: Change AXI and AHB clock rate on imx6sllBai Ping
Increase the AXI and AHB clock rate on i.MX6SLL according to the RM to improve the system bus performance. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13308-2 usb: phy: phy-mxs-usb: handle USB PHY eventPeter Chen
For mxs PHY, if there is a vbus but the bus is not enumerated, force the dp/dm as SE0 from the consider side. If not, there is possible USB wakeup due to unstable dp/dm, since there is possible no pull on dp/dm, eg, there is a USB charger on the port. Note, the vbus event is only occurred at device mode, and sent by udc driver. Signed-off-by: Peter Chen <peter.chen@nxp.com>
2018-08-24MLK-13308-1 usb: chipidea: udc: add USB PHY eventPeter Chen
Add USB PHY event for below situation: - vbus connect - vbus disconnect - gadget driver is enumerated USB PHY driver can get the last event after above situation occurs. Signed-off-by: Peter Chen <peter.chen@nxp.com>
2018-08-24MLK-13347 dts: mx6sll: enable DCP and hardware RNG for i.mx6sllye li
Add DCP and RNG node in imx6sll.dtsi to enable them. Signed-off-by: ye li <ye.li@nxp.com>
2018-08-24MLK-13359 ARM: dts: imx: Add imx6sll evk board dtsBai Ping
Add i.MX6SLL EVK board dts file. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13334 ARM: dts: imx: Add lpddr2 arm2 dts for imx6sllBai Ping
For i.MX6SLL LPDDR2 and LPDDR3 ARM2 board, they share the same board design but using different DDR chip. So we can reuse the LPDDR3 ARM2 board dts on LPDDR2 ARM2 board. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-13341 IPU: mxc_vout: fix the potential uninitalized variable usageGuoniu.Zhou
Fix coverity CID 17624 uninitialized scalar variable The 'fb_fmt' variable may be used before uninitialized So initialize it at the begining. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-09 14:15:56 +0000