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This commit intends to implement the flowchart and details
documented in the HDMI Transmitter Controller User Guide
section entitled "Programming Model".
Some input is also from the Synopsys API code.
The HDMI specification requires HDMI to set itself to VGA DVI mode
before reading the EDID.
So follow this sequence when HDMI is hotplugged:
1. Hdmi connector is plugged in, HDMI video gets an interrupt.
2. Clear out video mode list. Add only VGA DVI mode to list.
3. Request VGA DVI mode (call fb_set_var())
4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
call mxc_hdmi_setup() to set up HDMI.
5. Read the edid and add video modes from edid. Select the video
mode that is similar to the command line default.
6. Request VGA DVI mode (call fb_set_var())
7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
do mxc_hdmi_setup().
Also included is a workaround for an overflow condition in the HDMI.
The frame composer has an arithmetic unit that gets updated every time
we write to one of the FC registers. But sometimes, depending on the
relation between the tmds and sfr clocks, it may happen that this unit
doesn't get updated, even though the registers are holding correct
values. The workaround for this is, after completing the controller
configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF)
three or four times with the same value, and then follow it up by a SW
reset to the TMDS clock domain (MC_SWRSTZ).
We clear the overflow condition as described above every time we
change video mode. Also an overflow interupt handler will clear the
overflow condition if it happens again. This overflow condition is
expected (and not a problem) when we are in DVI (non-HDMI) mode, so
we do not worry about it in that case.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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This commit intends to implement the flowchart and details
documented in the HDMI Transmitter Controller User Guide
section entitled "Programming Model".
Some input is also from the Synopsys API code.
The HDMI specification requires HDMI to set itself to VGA DVI mode
before reading the EDID.
So follow this sequence when HDMI is hotplugged:
1. Hdmi connector is plugged in, HDMI video gets an interrupt.
2. Clear out video mode list. Add only VGA DVI mode to list.
3. Request VGA DVI mode (call fb_set_var())
4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
call mxc_hdmi_setup() to set up HDMI.
5. Read the edid and add video modes from edid. Select the video
mode that is similar to the command line default.
6. Request VGA DVI mode (call fb_set_var())
7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and
do mxc_hdmi_setup().
Also included is a workaround for an overflow condition in the HDMI.
The frame composer has an arithmetic unit that gets updated every time
we write to one of the FC registers. But sometimes, depending on the
relation between the tmds and sfr clocks, it may happen that this unit
doesn't get updated, even though the registers are holding correct
values. The workaround for this is, after completing the controller
configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF)
three or four times with the same value, and then follow it up by a SW
reset to the TMDS clock domain (MC_SWRSTZ).
We clear the overflow condition as described above every time we
change video mode. Also an overflow interupt handler will clear the
overflow condition if it happens again. This overflow condition is
expected (and not a problem) when we are in DVI (non-HDMI) mode, so
we do not worry about it in that case.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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* imx6sareauto fix i2c iomux pad settings
* On sabreaauto the i2c pad settings are missing in iomux-mx6q.h
* update i2c pad seetings and SD2 control pads
* Set correct i2c address for io expanders (expander A and B)
* explicit assert io expander reset line for normal operation mode
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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This reverts commit 6565023ad182d3347972aad3f1a13ba57266e81a.
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Allow UART to be a source for wakeup from low power mode.
Tested on a mx6sabrelite (where ttymxc1 is the console) by doing:
echo enabled > /sys/devices/platform/imx-uart.1/tty/ttymxc1/power/wakeup
echo mem > /sys/power/state
and then pressing a key in the console will wakeup the sytem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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On mx6qsabrelite there is a total of 1GB of RAM.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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On Audio class, the wLength field of the Setup
packet, contains the data payload size of the
following Data phase. Instead of harcoding values,
use wLength.
This also fixes a bug where Gadget driver had to
receive 3 bytes, but it was queueing a ZLP.
Signed-off-by: Felipe Balbi <balbi@ti.com>
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While testing g_audio with HighSpeed UDC on a
FS Hub, we had no configurations to present to
the host. That's because both speeds where
mutually exclusive.
Signed-off-by: Felipe Balbi <balbi@ti.com>
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In may gadgets bind and bind like functions were in a init section
as they were only run during initialisation. However, being
callback functions they were referenced from structures in “normal”
sections. Changing the tag from “__init” to “__ref” fixes the
warnings.
Signed-off-by: Michal Nazarewicz <m.nazarewicz@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Root cause is:
Ipu driver use msleep to wait for smfc idle, msleep isn't a
Accurate timer, but CSI SMFC is a real-time channel, so use
Interrupt handler to replace msleep.
Signed-off-by: Even Xu <b21019@freescale.com>
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outer_clean_range
dma_sync_single_for_device can only used for kernel physical memory,
while in gpu, we will also clean user physical memory for pixmap,
direct texture, etc. outer_clean_range can operate on both.
Signed-off-by: Wu Guoxing <b39297@freescale.com>
Acked-by: Lily Zhang <r58066@freescale.com>
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Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Read the silicon version stored in ROM at address ox48.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix incorrect frequencies reported from /proc/cpuinfo.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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* Update spdif config options for sabreauto platform
* Correct pad settings
* Only SPDIF RX in sabreauto, unset SPDIF TX support.
* spdif and i2c3 doesn't conflict in sabreauto platform
remove spdif early param and logic that set either pads.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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request cable detect pin when real init
Signed-off-by: Jason Chen <b02280@freescale.com>
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when use pan display, the case could be:
1. a small window wrap in a big frame buffer
2. a frame switch in a serial buffers
the ipuv3 fb driver used to support case 1, and for case 2,
if the fb format is interleaved, there is no problem, but for
non-interleaved format (like I420), there will be a display bug.
Signed-off-by: Jason Chen <b02280@freescale.com>
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when use pan display, the case could be:
1. a small window wrap in a big frame buffer
2. a frame switch in a serial buffers
the ipuv3 fb driver used to support case 1, and for case 2,
if the fb format is interleaved, there is no problem, but for
non-interleaved format (like I420), there will be a display bug.
Signed-off-by: Jason Chen <b02280@freescale.com>
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The chip document says the counter counts up to period_cycles + 1
and then is reset to 0, so the actual period of the PWM wave is
period_cycles + 2
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
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1. if the DAC volume is largest, output is harsh.
so reduce the DAC volume.
2. increase ADC volume
Signed-off-by: Gary Zhang <b13634@freescale.com>
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The change impact the mx5 bbg and loco build.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Need to push and pop all registers, otherwise, some registers
will be modified in the function call, add protection to avoid
this scenario.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- Add CONFIG_HOSTAP as CONFIG_WIRELESS_EXT's dependency
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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When dvfs-core is enabled along with "debug" in command line, CPUFREQ
printed too many debug messages.
Fix this by changing the threshold settings for DVFS-CORE and
make the transitions more conservative and infrequent.
Also use the CPUFREQ debug flag.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support for MX6 Sabre-auto (ARD) board
Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@freescale.com>
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Reserve the overlay fb triple buffer when we have a valid
resource for start and end.
Clear the GB fb buffers when we reserve memory for it.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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We have already had framebuffer reservation for BG display
by set the base/size resource in fb platform data.
But we may also have FG fb buffer reserve requirement.
So add addtional base/size resource in fb plaform data,
add a IORESROUCE_MEM resource when fb device register
to meet such requirement.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add remote wakeup test method to udc doc
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Meanwhile, fix the bug that there is no prime for GetStatus at
status phase
About how to test remote wakeup, please see:
Documentation/arm/imx/udc.txt
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Change dvfs driver and cpufreq driver to use regulator API to set cpu voltage.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Renaming to correct function and variable names from ARM2 to SABRE AUTO
Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@freescale.com>
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Signed-off-by: Jason Liu <r64343@freescale.com>
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since smp_lock.h has been removed on v3.0
Signed-off-by: Jason Liu <r64343@freescale.com>
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Signed-off-by: Wayne Zou <b36644@freescale.com>
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Signed-off-by: Jason Liu <jason.hui@linaro.org>
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Signed-off-by: Jason Liu <jason.hui@linaro.org>
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This reverts commit 9f26eaa231cf2a19064c5589a3515bdd60af596a.
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This reverts commit b35268ca923a8785ab311170b0a84210b3c7863e.
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This reverts commit 70c73cd0dde38fd44b4c019cb7288cbea90008f3.
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This reverts commit 7da674ed743b6feb9471fc290e10fc21194f09be.
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This reverts commit e3f2cd88631b667173047e66d311ba0f815f8a35.
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This reverts commit bcc0edfb10bfd8ab2974b0cf108490be72281146.
Conflicts:
drivers/mmc/host/sdhci-esdhc-imx.c
drivers/mmc/host/sdhci.h
Signed-off-by: Jason Liu <jason.hui@linaro.org>
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This reverts commit dee9bc3d9c98bc45ad42960a6650dffc66140d19.
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Signed-off-by: Jason Liu <jason.hui@linaro.org>
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