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2016-05-23MLK-12509-1 video: mipi_dsi_samsung: create a new dts for mipi dsi.Fancy Fang
Create a new dts for the 'TFT3P5079E' mipi panel on imx7d sabresd revb board. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
2016-05-23MLK-12449: mtd: gpmi: fix integer overflow issueHan Xu
fix the potential integer overflow issue found by coverify. Signed-off-by: Han Xu <han.xu@nxp.com>
2016-05-23MLK-12448: mtd: gpmi: fix nand double free issueHan Xu
fix the raw_buffer pointer double free issue found by coverify. Signed-off-by: Han Xu <han.xu@nxp.com>
2016-05-23MLK-12371: ARM: imx: suspend-imx7: correct HW_ANADIG_SNVS_MISC_CTRL setRobin Gong
To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register , and correct the bit29 setting: --before: write 1 to toggle DDR power pin to high before enter DDR retention, and write 1 again to pull pin to low when exit from DDR retention. --now: write 1 to pull DDR power pin to high and write 0 to low. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2016-05-19MLK-12420 fix potential head list corruption.Fancy Fang
The head list may be corrupted when two requests from the same 'pxp_chan' are issued sequentially. So change the issue_pending function to strictly serialized the requests to avoid this kind of issue. Signed-off-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit 3ed71dcdd8ceeb3725399053f31c1930d2e7a08d)
2016-05-16MLK-12731-2 ARM: dts: Makefile: add dts entry for imx6q-arm2-hsicPeter Chen
This dts is only for USB HSIC controller test which needs Validation Port Card on it. Disable controller 3 due to strange signal on it at arm2 board. Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 8bd0739d81719ed8a09ca4e45393bb1c5ce3de83)
2016-05-16MLK-12731-1 usb: chipidea: imx: add missing HSIC initialization for imx6qdl/slPeter Chen
This piece of code is existed at imx_3.10, but missing at imx_3.14 and imx_4.1, port it from imx_3.10. Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 901f278a08baf6e5109bcf538f1f78cdbbccd389)
2016-05-11MLK-12688-02: arm dts: Add csis-clk-settle propertySandor Yu
Add csis-clk-settle property to imx7D SDB mipi csi. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> (cherry picked from commit 01365628fdfadc4f8343722a2d5c69d5d8037540)
2016-05-11MLK-12688-01: mipi csi: Add clk_settle settingSandor Yu
Add clk_settle variable to compliance more mipi sensor. Mipi controller should setting by followed value according mipi sensor support D-phy version. Slave Clock Lane Control Register for TCLK-SETTLE. 2'b0x = 110 ns to 280ns (v0.87 to v1.00) 2'b10 = 150 ns to 430ns (v0.83 to v0.86) 2'b11 = 60 ns to 140ns (v0.82) Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> (cherry picked from commit 928103ba7d28a7dbddf950892cb9d49ec2b192d3)
2016-05-11MLK-12432-03: arm: dts: Replace ov5647 mipi sensor with ov5640Sandor Yu
ov5647 mipi camera sensor is replaced by ov5640 on imx7D SDB RevB board. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> (cherry picked from commit aef2ab14e91ccd173086a9849cf64619e078ed6f)
2016-05-11MLK-12432-02: capture: Add support for mipi inputSandor Yu
Combine csi image setting function for 32-bit,16-bit,8-bit format. For parallel 8-bit sensor input, when bit per pixel is 16, csi image width should been doubled. But for mipi input, the csi image width and height should align with mipi whatever data width. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> (cherry picked from commit caa8725e713691b42aa112a6e51f12e7d595f139)
2016-05-11MLK-12432-01: ov5640 mipi: support more platform and reduce support modeSandor Yu
-Support no power and reset pins platform. -Remove specific power and reset pin setting for ov5640 daughter card. -Put sensor in software power down state when streamoff. -Remove unsupported video modes, keep 640x480, 720x480, 720p, 1080p 30fps video modes in driver. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> (cherry picked from commit 6a6c44e2406dcd9481e3103ca2710a319265c52a)
2016-05-11MLK-12763 ARM: imx7d: iomux: correct uart input sel option valueAndy Duan
GPIO0~GPIO7 part: - Commit(c8cabda5ab07) add some wrong input sel value for uart, return them to origin setting. - Add uart DTE pin mode setting. UART2_TX_DATA pin part: - RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass) updated input sel define for UART2_RX_DATA, then set the correct input sel for the pin. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9)
2016-05-09MLK-12765 ARM: imx: make sure DLL is locked on i.MX7DAnson Huang
On i.MX7D, per design team's require, need to make sure DLL is locked after DDR frequency scaled done. Although normally there should be no issue, but it is better to add it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-05-09MLK-12748-3 ARM: imx: adjust imx7d lpddr3 retention exit flowAnson Huang
On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-05-08MLK-12748-2 ARM: imx: remove IOMUXC GPR setting for i.mx7d TO1.2Anson Huang
i.MX7D TO1.2 removes the DDR PAD retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-05-08MLK-12748-1 ARM: dts: imx7d: correct usdhc1 cd pin settingAnson Huang
i.MX7D 19x19 LPDDR2 ARM2 board's uSDHC1 CD pin should be LOW active, correct it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-05-06MLK-12761 ARM: imx: add mu as wakeup source for i.mx7dAnson Huang
When A7 platform is in low power mode while M4 is NOT, M4 should be able to send message to wake up A7, so MU must be always as wake up source. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-05-06 MLK-11262-5: ARM: imx: Change A7 MU ready timingTeo Hall
Change when A7 signal M4 to make sure busfreq is always up when the M4 send high bus release. This prevents race condition for Low Power Demo Signed-off-by: Teo Hall <teo.hall@nxp.com>
2016-05-04MLK-12722: ASoC: fsl_spdif: clear the validity bit for TXShengjiu Wang
Validity bit is set in default, which means the data is not reliable, The receive device may drop this data. So clear it in default, and provide a mixer interface for user to control this bit. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> (cherry picked from commit 48293e6bf7793de01678ee1426cccc9119998ba1)
2016-05-04MLK-12607: ASoC: fsl-asrc: Add the support of 12kHz and 24kHzShengjiu Wang
Remove the pre-processing and post-processing table. use proc_autosel() to select proper parameters. Unify the supported input and output rate. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> (cherry picked from commit 8353ec20bd9950ec98d76423c62321a7ea0c7190)
2016-05-04MLK-12464-2: ASoC: wm8960: fix clock is not correct after suspend/resumeShengjiu Wang
After the suspend/resume, hw_params may be called in bias_level is not BIAS_ON, then the PLL is not disable/enabled, if the sample rate is changed, the output clock is not correct. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> (cherry picked from commit cced8358c2202824dfdc1780609539655ae5fec5)
2016-05-04MLK-12464-1: ASoC: fsl: imx-wm8960: Fix no clock after suspend/resume randomlyShengjiu Wang
After suspend and resume, the wm8960 codec will change the state from BIAS_OFF to BIAS_ON, in this time, the hw_free is called, the PLL will be diabled, and next instance is started in rapid sequence, hw_params is called But PLL is not enabled, because the bias state is not BIAS_ON. As PLL is disabled in BIAS_ON->BIAS_STANDBY, so don't need to disable pll in hw_free of machine driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> (cherry picked from commit 9b6063efd3966266a1a7616c11b818139933497e)
2016-04-29MLK-12620 ARM: imx: correct i.MX7D fuse MAC1_ADDR offset addressFugang Duan
i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d, otherwise read un-correct MAC address. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f)
2016-04-29MLK-12706-3 arm: imx_v7_defconfig: build in bcmdhdHaibo Chen
Set bcmdhd as build in type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2016-04-29MLK-12706-2 net: bcmdhd: set the bcmdhd driver default build inHaibo Chen
Bcmdhd wifi driver default build as module, now default build in this wifi driver. To support this build in feature, this patch add flag ENABLE_INSMOD_NO_FW_LOAD, and use extern function sdio_reset_comm() as instead. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2016-04-29MLK-12706-1 mmc: sdio: add sdio reset function for bcmdhd wifiHaibo Chen
This patch add function sdio_reset_comm() to support bcmdhd wifi dirver build-in type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2016-04-29MLK-12705 ARM: imx: add support for i.mx7d TO1.2 busfreqAnson Huang
i.MX7D TO1.2 fix the CKE issue, need to follow TO1.0's precedure for DRAM frequency scaling. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-04-20MLK-12685 ARM: dts: imx6sx-sabreauto.dts: improve usdhc4 pad drive strengthHaibo Chen
For imx6sx-sabreauto board, the usdhc4 is used for the sd slot locate on the base board, so need to improve the pad drive strength, otherwise we will meet many CRC error or timeout error when insert a sd card. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> (cherry picked from commit 1cbfce01e4e076d7f7e3b879c2c41d217d8afa48)
2016-04-19MLK-12675 ARM: dts: imx: keep RTC enabled for software poweroffAnson Huang
SRTC needs to be kept enabled during system poweroff, SNVS_LP control register bit 0 SRTC_ENV must be set to enable RTC, for software poweroff, kernel just read the register offset and value from dtb and write to SNVS_LP control register to poweroff system, need to make sure bit 0 SRTC_ENV is set to enable RTC during system poweroff. Previous setting did NOT enable it which will cause RTC stop running if using software poweroff. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-04-19MLK-12671 ARM: imx: support single soc configAnson Huang
Need to make sure build pass with single SOC config, in current build for single SOC config, if both SOC_IMX7D and SOC_IMX6SX are NOT selected, below build error will occur, add MU module config to fix this build issue. LD init/built-in.o arch/arm/mach-imx/built-in.o: In function `busfreq_probe': :(.text+0x5370): undefined reference to `imx_mu_lpm_ready' arch/arm/mach-imx/built-in.o: In function `bus_freq_pm_notify': :(.text+0x5d50): undefined reference to `imx_mu_lpm_ready' :(.text+0x5d68): undefined reference to `imx_mu_lpm_ready' make: *** [vmlinux] Error 1 Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2016-04-14MLK-12617 mmc: Fix compile error when CONFIG_MMC=mHaibo Chen
When CONFIG_MMC=m, compile error shows up ERROR: "of_alias_max_index" [drivers/mmc/core/mmc_core.ko] undefined! ERROR: "mmc_get_reserved_index" [drivers/mmc/card/mmc_block.ko] undefined! ERROR: "mmc_first_nonreserved_index" [drivers/mmc/card/mmc_block.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 make: *** Waiting for unfinished jobs.... This patch export the upper three symbol for module runtime load. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2016-04-12MLK-12623-03 ARM: imx: Add cpu speed grading check for imx6ulBai Ping
In the OCOTP fuse map, the speed grading[1:0] define the MAX CPU speed the chip can run. The detailed definition is below: 2b'00: Reserved; 2b'01: 528000000Hz; 2b'10: 696000000Hz; 2b'11: Reserved; We need to disable the illegal setpoints according to the fuse map. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 1fc5419ba08a8da302cfcddb0ea76226d7bdc8c3)
2016-04-12MLK-12623-02 ARM: dts: imx: Add 700MHz setpoint define in dtsBai Ping
According to the latest datasheet(Rev. 0, 12/2015), When the chip is run at LDO enabled mode, the highest setpoint can be set to 700MHz in overdrive mode. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 9838ff4b9dfaaacdea01b2bf5f54020ccf991f23)
2016-04-12MLK-12623-01 cpufreq: imx: Add support for 700MHz setpoint in cpufreqBai Ping
On i.MX6UL EVK board, we use a external GPIO DC regulator to control the VDD_ARM_SOC_IN voltage, if default voltage is 1.4V when the system is bootup. Per design team, when the highest setpoint freq is not bigger than 528MHz, we can decrease this regulator voltage to 1.3V. On i.MX6UL TO1.1, we add a 700MHz setpoint. When the highest setpoint freq is 700MHz, the DC regulator should be at 1.4V to to cover the IR drop. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 0e3293e53f4bd5b122abc250b610dd61850e3ce9)
2016-03-31MLK-12277 media: camera: add check for width and height against 0rel_imx_4.1.15_1.1.0_gaRobby Cai
when do vte test it meets follow dump in small probability. Add against-0 check to resovle this. $ v4l_emma.sh 1 1 $ v4l_emma.sh 1 9 ------------[ cut here ]------------ : /dev/video1 Set PARM sucessfulWARNING: CPU: 0 PID: 1123 at /home/bamboo/build/4.1.X-1.0.0_ga/fsl- imx-fb/temp_build_dir/build_fsl-imx-fb/tmp/work-shared/imx6qdlsolo/kernel-source/mm/page_alloc.c:266 5 __alloc_pages_nodemask+0x3c8/0x894() ly v4l_capture_testapp 0 TINModules linked in:FO : /dev/video1 input formatti mx6s_captureng pass v4l_capture_testapp 0 ov5640_camera TINFO : PRP_ENC_ON_D gpRGBcon evbugv_buf malloc pass! CPU: 0 PID: 1123 Comm: v4l2_capture_em Not tainted 4.1.8-1.0.0+g87e6c2f #1 Hardware name: Freescale i.MX6 Ultralite (Device Tree) [<80015d84>] (unwind_backtrace) from [<80012728>] (show_stack+0x10/0x14) [<80012728>] (show_stack) from [<80750a54>] (dump_stack+0x84/0xc4) [<80750a54>] (dump_stack) from [<80032f3c>] (warn_slowpath_common+0x80/0xb0) [<80032f3c>] (warn_slowpath_common) from [<80033008>] (warn_slowpath_null+0x1c/0x24) [<80033008>] (warn_slowpath_null) from [<800b2cc4>] (__alloc_pages_nodemask+0x3c8/0x894) [<800b2cc4>] (__alloc_pages_nodemask) from [<8001ba3c>] (__dma_alloc_buffer.isra.3+0x2c/0x84) [<8001ba3c>] (__dma_alloc_buffer.isra.3) from [<8001bab0>] (__alloc_remap_buffer.isra.6+0x1c/0x8c) [<8001bab0>] (__alloc_remap_buffer.isra.6) from [<8001bd1c>] (__dma_alloc+0x1fc/0x228) [<8001bd1c>] (__dma_alloc) from [<8001be78>] (arm_dma_alloc+0x8c/0xa0) [<8001be78>] (arm_dma_alloc) from [<804cd934>] (vb2_dc_alloc+0x68/0x100) [<804cd934>] (vb2_dc_alloc) from [<804c7df8>] (__vb2_queue_alloc+0x134/0x4d0) [<804c7df8>] (__vb2_queue_alloc) from [<804ca794>] (__reqbufs.isra.17+0x1a8/0x304) [<804ca794>] (__reqbufs.isra.17) from [<804b7ac0>] (__video_do_ioctl+0x2b0/0x324) [<804b7ac0>] (__video_do_ioctl) from [<804b753c>] (video_usercopy+0x1b8/0x480) [<804b753c>] (video_usercopy) from [<804b3f34>] (v4l2_ioctl+0x118/0x150) [<804b3f34>] (v4l2_ioctl) from [<800f8360>] (do_vfs_ioctl+0x3e8/0x608) [<800f8360>] (do_vfs_ioctl) from [<800f85b4>] (SyS_ioctl+0x34/0x5c) [<800f85b4>] (SyS_ioctl) from [<8000f480>] (ret_fast_syscall+0x0/0x3c) ---[ end trace 55ed68f89eca4805 ]--- mx6s-csi 21c4000.csi: dma_alloc_coherent of size 0 failed Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit 2c1fa9347a50e05c79b76de35f84192af796f677)
2016-03-31MLK-12573 ARM: dts: set LCD_nPWREN low to make VLCD_3V3 output 3V3.Robby Cai
Q901 (IRLML6401) is p-channel MOSET, need set pin1 (LCD_nPWREN) to low to let pin3 output be 3V3. Normally when pin1 is high, then pin3 output should be gated. It was working previously due to some leakage. Correct the enable logic from the software viewpoint. Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit c70398a0b2e860d0bd9478d956d077eff8e7ea4f)
2016-03-28MLK-10934 mtd: use memcpy to replace the memcpy_fromioHuang Shijie
During the read of NOR, the kernel actually calls the inline_map_copy_from() to read the data out. And inline_map_copy_from() will use the memcpy_fromio() to do the real job. The memcpy_fromio macro maps _memcpy_fromio() in the current code. But the _memcpy_fromio() will use readb() to do the copy work one byte by one byte. This makes the read performance of NOR very slow(about 2~3MB/s). A similiar discussion could be found in: http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.html This patch replace the memcpy_fromio with memcpy which is optimized by the kernel. The following is the result from mtd_speedtest with M29W256GL7AN6E: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 4194304, eraseblock size 131072, page size 512, count of eraseblocks 32, pages per eraseblock 256, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 845 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19504 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 845 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 19140 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 846 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 19320 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 233 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 225 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 224 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 225 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 225 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 225 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 224 KiB/s mtd_speedtest: finished ================================================= (cherry-picked from: f1e5914ffd82d5326cbd30507d4f37d02a0da099) Signed-off-by: Huang Shijie <b32955@freescale.com>
2016-03-25MGS-1678 [#2269] memleak in GPU driver sysfs interfacegan
Add missing .release callback in file_operations of vidmem_operations in order to release the allocated memory. Date: Mar 18, 2016 Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com> (cherry picked from commit bf8499286426bd48f00e83a7e794b2309da502bc)
2016-03-25MA-7715 fix GPU kernel panic reported by android CTSRichard Liu
The patch removes the dependence between cache flush operation and node. Node is not used anymore when flush cache. Cache flush can work with only logical address passed into underlying functions does not need physical address. Signed-off-by: Richard Liu <r66033@freescale.com> (cherry picked from commit ad65770512d2baeb45f5d0622d985f9856b7cc1e)
2016-03-25MGS-1630 5.0.11.p8 driver can't pass build with kernel 4.1 on Android M6.0Richard Liu
It has converted sync to fence api in kernel_imx/drivers/staging/android/sync.h, so make it done in gpu driver to match kernel. Signed-off-by: Meng Mingming <b51843@freescale.com> Signed-off-by: Richard Liu <xuegang.liu@freescale.com> (cherry picked from commit d69c57557a2ef782d0daa617a30945f41a608fd5)
2016-03-21MLK-12466 ARM: dts: imx6ul-14x14-evk-usb-certi: add USB certification dtsPeter Chen
Below are the differences between standard evk: - Enable tpl - Enable software control vbus for otg2 (hardware rework is needed) - Disable TSC due to the pin conflict with above vbus regulator Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit e4a5f2e763d5c9df8b97b01ee38879a9bee66f0d)
2016-03-17usb: chipidea: add system interface for ttctrl.tthaPeter Chen
In chipidea IP RTL, there is a very limited design for siTD, the detail like below: There is no Max Packet Size at siTD, so it uses one constant for both Max Packet Size for packet and the packet size for the last transaction when considering schedule. If the ttctrl.ttha does not match against Hub Address field in siTD, this constant is 188 bytes, else this constant is 1023 bytes. If the ttctrl.ttha is non-zero value, RTL will use 188 as this constant, so it will lose the data if the packet size is larger than 188 bytes, eg, if we playback a wav which format is 48khz, 16 bits, 2 channels, the packet size will be 192bytes, but the controller will only send 188 bytes for this packet, the noise will be heared using USB audio card. The use case is single transaction, but higher frame rate. If the ttctr.ttha is zero value, we can send 1023 bytes within one transaction, but the controller will not accept the coming tranaction if it considers the schedule time is less than 1023 bytes. So the limitation is we can't schedule as many as transactions within frame. If the total bytes is already 256 bytes for previous transactions within frame, it can't accept another transaction. The use case is multiple transactions, but less frame rate. Signed-off-by: Peter Chen <peter.chen@kernel.org> Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 5e07ea7f812f2216263da2acd4f5e677de97fd62)
2016-03-17doc: usb: ci-hdrc-usb2: add property non-zero-ttctrl-tthaPeter Chen
If this property is not set, the max packet size is 1023 bytes, and if the total of packet size for pervious transactions are more than 256 bytes, it can't accept any transactions within this frame. The use case is single transaction, but higher frame rate. If this property is set, the max packet size is 188 bytes, it can handle more transactions than above case, it can accept transactions until it considers the left room size within frame is less than 188 bytes, software needs to make sure it does not send more than 90% maximum_periodic_data_per_frame. The use case is multiple transactions, but less frame rate. Signed-off-by: Peter Chen <peter.chen@kernel.org> Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 7f3ee45c71d27ffaf1fb11f002b414ec9a323382)
2016-03-17Revert "usb: chipidea: imx: enable CI_HDRC_SET_NON_ZERO_TTHA"Peter Chen
This reverts commit e765bfb73ff7. In the most of cases, we only use one transaction per frame and the frame rate may be high, If the platforms want to support multiple transactions but less frame rate cases like [1] and [2], it can set "non-zero-ttctrl-ttha" at dts. [1] http://www.spinics.net/lists/linux-usb/msg123125.html [2] http://www.spinics.net/lists/linux-usb/msg118679.html Signed-off-by: Peter Chen <peter.chen@kernel.org> Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 9e1a14ec6dfe34ae92e9754bbb1a5c470acbcdf1)
2016-03-15MLK-12556 dts: i.mx6ul: configure the CMA region by defaultJason Liu
CMA region is a must to avoid the multile memory mapping for the DMAed memory and also benifit the large continious phisical memory allocation. The default value is depend on the target system design and user cases definition. This is not suitable to put this into the soc.dtsi, thus we put it into the board DTS. customer can override the value by changing cma size in DTS file. Again, customer need set the CMA size correctly according to the target system. The incorrectly CMA size can cause Linux kernel fail to boot up.CMA disabled or CMA size set to zero is also not allowed. Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2016-03-11crypto: testmgr - Disable rfc4543 testHerbert Xu
Because the old rfc4543 implementation always injected an IV into the AD, while the new one does not, we have to disable the test while it is converted over to the new AEAD interface. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-03-11 MLK-12475 CAAM: sg pointer updated instead of local copyDan Douglass
Correct error in CAAM driver port. dma_map_sg_chained() had a patch applied to traverse the sg list using a local copy to prevent changing the value of the passed in sg list pointer. Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
2016-03-09MLK-12496 bcmdhd: update driver to Broadcom official released version 141.88Dong Aisheng
Some major fixes delivered by Broadcom. 1. Initialize nd_config parameter of cfg80211_wowlan to NULL 2. Avoid using hardcoded dummy channel number while creating p2p interface 3. Avoid creation of multiple instance of wl_event_handler thread. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> (cherry picked from commit 934f70e3af6af4e887a2c3027e19db2122efd1cb)
2016-03-04MLK-12478-2 dts: imx7d-lpddr3-arm2: add lpsr mode state for flexcan pinsDong Aisheng
add lpsr mode state for flexcan pins Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> (cherry picked from commit 535699f47fbd7fb22a435ca2047560ee20687392)
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