| Age | Commit message (Collapse) | Author |
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The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg vbus wakeup system will be supported
Signed-off-by: make shi <b15407@freescale.com>
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MSL headfile part change.
Signed-off-by: make shi <b15407@freescale.com>
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Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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ESAI playback and ASRC P2P playback use difference codec_dai while using
the same codec. Thus they can't work together.
In this patch, add mutual protection between ESAI playback and ASRC P2P
playback.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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[MX6X] Fix BogoMIPS value is not correct
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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At pc sends suspend/resume case, the udc_controller->usb_state should
keep unchange during the suspend/resume process, at former code, the
fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED
unconditionally. In fact, USB_STATE_ATTACHED stands for initial state
and should be set when we try to run controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Since Logitech Quickcam E3500 is defaultly listed in usb_quirk_list on current
linux kernel. So the USB camera only supports reset resume, but doesn't support
normal usb suspend/resume. Actually, the USB camera works abnormally after USB
reset resume, but it works well after doing normal suspend/resume.
Signed-off-by: make shi <b15407@freescale.com>
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config audio pads to avoid pop-noise
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Vsync-pre irq is invalid for IPU overlay channel. The fb driver code
wrongly registers Vsync-pre for overlay channel with an un-initialized
irq number(0), which is conflict with CSI EOF irq number and causes
capture function broken. This patch avoids registering vsync-pre irq
for overlay channel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Move spin_unlock_irqrestore to avoid calling mutex at atomic
environment, as dr_wake_up_enable will call mutex_lock
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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[MX6SL]MMDC: DDR Controller's measure unit may return an incorrect
value when operating below 100 MHz
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Disable GPU IRQ trigger for CPU governor to save power
Current GPU trigger will let CPU work at 1G no matter any 3D draw
that make much power waste, to balance power and performance
we desire to disable GPU trigger for CPU governor, this change
will impact some benchmark performance but the drop is acceptable,
android will add performance mode, for any demo or customer who care
performance more than power please select performance mode.
Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Lily Zhang
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When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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IPU: Clean up dead code
Signed-off-by: Wayne Zou <b36644@freescale.com>
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If we use the late_initcall(), then there is a time slot between
the exit of early uart console and the real console:
-->late_initcall(mxc_early_uart_console_disable)
......
-->imx_startup()
In this time slot, the clock will be closed, so the log printed during
the time slot is buffered, this is why we can not see the NFS's log.
Change the late_initcall() to late_initcall_sync() which eliminates the
time slot.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
Signed-off-by: Rong Dian <b38775@freescale.com>
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Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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SOC/PU voltage need to following some rules according to latest
datasheet:
1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V;
2. SOC and PU must be same as they don't have level shift;
3. Adjust previous wrong voltage setting.
If SOC/PU voltage is too low, may cause system crash on some
chips, we have a board that easily crash with GPU working and
doing some tar operation, with this voltage adjust, this issue
fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix not able to set high bus frequency from low bus frequency.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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System will report oops as below. To fix it we will move mx6_timer_rate to
clock.c, so that we can avoid use clk_get_sys which cause schedule after
spin_lock.
oops log:
BUG: scheduling while atomic: kinteractiveup/1403/0x00000002
Modules linked in:
(unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0)
(__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208)
(__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c)
mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec)
(clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c)
(mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c)
(_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40)
(clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec)
(_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20)
(_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8)
(_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68)
(clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160)
(set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c)
(mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60)
Signed-off-by: Robin Gong <b38343@freescale.com>
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1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
but now 498Mhz seems not stable enough, comment now, test enough to
add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 67c2bd5edef363412a074e9b4130b5207dac8a7f)
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ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
From schematic of ARM2 board, epdc and spi share this pin if plug epdc
daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
well firstly. So we make sure SPI-NOR work successfully by default. But if
enable epdc , SPI-NOR on ARM2 will work fail.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Disable LDB DI clock when suspend.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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EDID read will failed sometimes on some boards.
Read EDID twice if first one failed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
- Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
Signed-off-by: make shi <b15407@freescale.com>
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If we use the late_initcall(), then there is a time slot between
the exit of early uart console and the real console:
-->late_initcall(mxc_early_uart_console_disable)
......
-->imx_startup()
In this time slot, the clock will be closed, so the log printed during
the time slot is buffered, this is why we can not see the NFS's log.
Change the late_initcall() to late_initcall_sync() which eliminates the
time slot.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>
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export thermal hot variable for GPU
Signed-off-by: Rong Dian <b38775@freescale.com>
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1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
Signed-off-by: Rong Dian <b38775@freescale.com>
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This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.
PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
by hw_anadig_ana_misc2_control0 bit.
Signed-off-by: make shi <b15407@freescale.com>
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The ENABLE bit is not set for all PLLs by default. Ensure
that the pll_enable() function sets this bit for all PLLs.
The pll_disable() function should not clear this bit
for PLL1, PLL2, PLL3 and PLL7. The output of these PLLs
maybe used even if they are bypassed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The problem is caused because the board init routine don't add the
corresponding device node. Problem resolved after add them
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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The problem is caused because "mx6_sabrelite_board_init" don't add the
corresponding device node. Problem resolved after add them.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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There is channel swap happened when playing stereo wav. According to the spec,
the initial words should be written to the ETDR register, at least one word
per enabled transmitter slot, to avoid any potential problem.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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