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2012-07-30ENGR00218013-6 SDMA:Add HDMI script in SDMA firmwareChen Liangjun
Add support for hdmi-sdma script content in sdma firmware. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-5 HDMI: Add SDMA to help HDMI audio support multi bufferChen Liangjun
For chip version easily than TO1.1, HDMI use internel DMA enginue for audio tranfer. Due to capability of HDMI module, FIFO underrun is unavoidable. For chip TO 1.2, introducing SDMA to help HDMI audio DMA. With the help of SDMA, HDMI audio can use ping-pong buffer mechanism and FIFO underrun can be avoid. In this path: Add SDMA support for i.MX6Q later than TO1.2. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-4 MX6Q ARM2: Set HDMI event as event 2 of SDMA eventChen Liangjun
Select external SDMA request as SDMA event 2 for MX6Q ARM2 board. SDMA event 2 can be configured HDMI or IPU. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-3 SDMA:Add support for HDMI_SDMAChen Liangjun
1 Add support for HDMI_SDMA config. 2 Add support for HDMI_SDMA interrupt handler. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-2 SDMA:Add script address for HDMIChen Liangjun
Add hdmi-sdma script enum type for SDMA script. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218013-1 DMA:Add HDMI DMA type and priv data for imx_dma_dataChen Liangjun
1 Add HDMI sdma periphal enum type. 2 Add private data type for imx_dma_data. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-30ENGR00218754: mx6: fix build warning for sd pad configurationRyan QIAN
- fix build warning about uninitialization of sd_pads_50mhz, sd_pads_100mhz, and sd_pads_200mhz. affected soc: - mx6q arm2/sabreauto/sabrelite - mx6sl arm2 Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-27ENGR00218624 ASRC: set dma_data to 0 before config SDMAChen Liangjun
To allocate an SDMA channel, imx_dma_data struct is need. However, if the member dma_request_p2p is not set to 0 before configuration, SDMA driver would treat the channel as p2p(periphal to periphal) DMA and set SDMA channel context in p2p way. In the worst case, SDMA would access some unexisted address cause of mis configuration above and thus cause kernel panic or hang. In this patch, set imx_dma_data struct to 0 once it is allocated from stack. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-07-27ENGR00182743-4 V4L2 output: Add non-interleaved YUV444 pixel format supportWayne Zou
Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-27ENGR00182743-3 FB MXC: Add non-interleaved YUV444 pixel format supportWayne Zou
Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-27ENGR00182743-2 IPU: Add non-interleaved YUV444 pixel format supportWayne Zou
Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-27ENGR00182743-1 IPU: Add non-interleaved YUV444 pixel format supportWayne Zou
Define IPU_PIX_FMT_YUV444P macro for non-interleaved YUV444 pixel format Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-27ENGR00218466 WM8962: remove unused variableGary Zhang
remove unused variable Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-07-27ENGR00218579-2 Update dynamically change GPU clock implementationLoren Huang
It fixed the issue which causes gpu driver can't enter suspend and idle mode. Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Lily Zhang
2012-07-27ENGR00218579-1 Update dynamically change GPU clock implementationLoren Huang
This patch from vivante. It fixed the stress test failure issue by disabling all internal clock before clock updating. Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Lily Zhang
2012-07-27ENGR00214565 MX6x, IPUv3: Display lack last horizontal pixelSandor Yu
Update IPU micro code to show the last horizontal line pixel. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-27ENGR00218412-2 OV5642:Power down after checking dev idLiu Ying
This patch powers down camera after checking camera device id to save power. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit eb280a7182cd8c71d698b57a720447f9d9b1174a)
2012-07-27ENGR00218412-1 OV5640 mipi:Power down after checking dev idLiu Ying
This patch powers down camera after checking camera device id to save power. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit a73b70b3d425825b4f4ba99c4c38c23bde227a9a)
2012-07-26ENGR00172083 SPI-NOR mx6: fix failed erase uboot ENV on SPI-NOR by MFG toolRobin Gong
In MFG tool will use "flash_eraseall /dev/mtd0" command to erase whole mtd0 partition, but u-boot environment params are stored in offset 0xc0000 which exceed the u-boot patition 0x40000, it means the "flash_eraseall" command only erase u-boot partition, but not environment area. So we need increase the size of u-boot partition to 0x100000 as what we remain 1MB for u-boot. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-07-26ENGR00215520-04 Mx6:USB host: USB Host1 modulizationmake shi
Disable the host wakeup and put phy to low power mode When the module be removed, and the requested pre irq should be free. Signed-off-by: make shi <b15407@freescale.com>
2012-07-26ENGR00215520-03 Mx6:USB host: USB Host1 modulizationmake shi
- remove mx6_usb_h1_init() in board specific initialization files - Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c to support the usb_h1 modulization - Export necessary function which is used in usb_h1.c Signed-off-by: make shi <b15407@freescale.com>
2012-07-26ENGR00215520-02 Mx6:USB host:USB Host1 modulizationmake shi
MSL headfile part change -Add and remove some function define in usb.h Signed-off-by: make shi <b15407@freescale.com>
2012-07-26ENGR00215520-01 Mx6:USB host: USB Host1 modulizationmake shi
- Add USB_EHCI_ARC_H1 configuration to imx6_defconfig and imx6s_defconfig, the default configuration is selected as "y" - add related USB_EHCI_ARC_H1 configuration to Makefile - add related USB_EHCI_ARC_H1 configuration to Kconfig Signed-off-by: make shi <b15407@freescale.com>
2012-07-26ENGR00217633 Add force contiguous memory pool in gpu driverRichard Liu
Add force contiguous memory pool in gpu driver Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Lily Zhang
2012-07-26ENGR00215346: mmc: esdhc: change to use sdma instead of adma due to ic limit.Ryan QIAN
Due to ic issue, adma2 failed to work when ahb freq is slow (<50Mhz), while SDMA does not have issue. workaround: - use SDMA instead. performance comparison between SDMA & ADMA: | | SDMA | ADMA | --------------------------------------------------------------------- | wifi downlink* | ~38Mbps | ~38Mbps | | memory card** | ~20MBps(r)/~4MBps(w) | ~20MBps(r)/~9MBps(w) | * wifi downlink throughput is tested by iperf in open air. ** writing performance for SDMA is much slower than ADMA, it might be an issue which needs further investigation. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-26ENGR00216848 MX6 DL dual display failed on HDMI and LVDSSandor Yu
HDMI output video mode is 1080p, LVDS output is XGA. The IPU bandwidth is not enough to support the two display output when IPU HSP clock setting to 200MHz, increase the IPU HSP clock to 270MHz and dual display can work. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-07-26ENGR00218274 CPUFREQ: fix conservative governor bugLin Fuzhen
When system not boot up all cores, such as adding max_cpus=n, n<NR_CPUS, then the conservative governor will increase the cpu frequncy to the highest freq and never get to down. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-07-25ENGR00182061-4 MXC v4l2 capture:Remove inappropriate msleep codeLiu Ying
msleep() after camera power down should not be called in mxc v4l2 capture core code. Instead, this should be handled by camera power down function. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-25ENGR00182061-3 MX6 SabreSD:Correct camera pwdn functionLiu Ying
This patch adds 2ms sleep after camera power down signal is set to high or to low to ensure power down or up is successful. OV5640/OV5642 camera specs say that they require this condtion to be true - for PWDN to go low, power must first become stable(DVDD to PWDN>=1ms), so this patch simply use 2ms which should be enough. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-25ENGR00182061-2 OV5640 mipi camera:Check dev id before registerLiu Ying
This patch checks camera device id via i2c bus before register v4l2 internal device. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-25ENGR00182061-1 OV5642 camera:Check dev id before registerLiu Ying
This patch checks camera device id via i2c bus before register v4l2 internal device. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-25ENGR00218070 imx6 battery: fix charger led first wrong indication statusRong Dian
because boot time gap between led framwork and battery driver init,when system boots with charger attatched, charger led framwork loses the first charger online event,add once extra power_supply_changed can fix this issure Signed-off-by: Rong Dian <b38775@freescale.com>
2012-07-25ENGR00217936-02 mmc: esdhc: fix unknown controller version for usdhcRyan QIAN
- Add cpu_is_mx6dq, cpu_is_mx6dl to strengthen the condition. Note: mx6sl has no such issue because it's fixed by IC, in other word, mx6sl aligns with sdhc specification. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-25ENGR00217936-01 mmc: esdhc: fix unknown controller version for usdhcRyan QIAN
SVN value (0x3) defined in fsl host controller on mx6dq/mx6dl differs from the one (0x2) defined in sdhc specification. - original 0x11 is an incorrect value, it should be 0x3 Note: mx6sl has no such issue because it's fixed by IC, in other word, mx6sl aligns with sdhc specification. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-07-25ENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by defaultRobin Gong
To validate LDO bypass function fully, enable CONFIG_MX6_INTER_LDO_BYPASS on u-boot and kernel, only for mx6sl. Signed-off-by: Robin Gong <b38343@freescale.com>
2012-07-25ENGR00182271-3 V4L2 OVERLAY: Add IPU2 overaly support for fore groundYuxi Sun
When vf_rotation > IPU_ROTATE_VERT_FLIP, canncel the MEM_ROT_VF_MEM - MEM_FG_SYNC channel link and using IPU_IRQ_PRP_VF_ROT_OUT_EOF irq to trigger double buffer switch. When vf_rotation <= IPU_ROTATE_VERT_FLIP,cannel the CSI_PRP_VF_MEM - MEM_FG_SYNC channel link, and using IPU_IRQ_PRP_VF_OUT_EOF to trigger double buffer switch. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-25ENGR00182271-2 V4L2 OVERLAY: Add IPU2 overlay support of back groundYuxi Sun
Get the ipu device which the display frame buffer is on before start preview, then request the correspondding display channel irq. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-25ENGR00182271-1 V4L2 capture: Add IPU2 overlay supportYuxi Sun
Add 3 overlay output item for IPU2: DISP4 BG, DISP4 BG - DI1, DISP4 FG. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-07-25ENGR00217857: Changed iomux ID pinAlejandro Sierra
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID This fix was already implemented on CR ENGR00180424. Somehow this was not included on newer releases. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-07-25ENGR00214404-1 Merge vivante 4.6.9_p4 kernel part codeLoren Huang
Merge vivante 4.6.9 kernel part code Updated clock management code Updated gpu reset code Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Lily Zhang
2012-07-25ENGR00217721-5 usb gadget random transfer failTony LIU
usb driver part - After USB driver prime a bulk transfer(whatever IN or OUT, take OUT for example) on ep1, only one dTD is primed, an USB Interrupt (bit 0 of USBSTS) will be issued, and find that endptcomplete register is 0x2 which means an OUT transfer on ep1 is completed, at this time the ep1 out queue head status is 0x1e18000, and next dtd pointer is 0x1 which means transfer is done and everything is OK, while the dTD token status is 0x2008080 which means this dTD is still active, not completed yet. - Audio SDMA and Ethernet have the similar issue - root cause is not found yet - work around: change the non-cacheable bufferable memory to non-cacheable non-bufferable memory to make this issue disappear. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217721-4 implement dma_pool_alloc_nonbufferable interfaceTony LIU
mm core part - After USB driver prime a bulk transfer(whatever IN or OUT, take OUT for example) on ep1, only one dTD is primed, an USB Interrupt (bit 0 of USBSTS) will be issued, and find that endptcomplete register is 0x2 which means an OUT transfer on ep1 is completed, at this time the ep1 out queue head status is 0x1e18000, and next dtd pointer is 0x1 which means transfer is done and everything is OK, while the dTD token status is 0x2008080 which means this dTD is still active, not completed yet. - Audio SDMA and Ethernet have the similar issue - root cause is not found yet - work around: change the non-cacheable bufferable memory to non-cacheable non-bufferable memory to make this issue disappear. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217721-3 implement dma_alloc_noncacheable interfaceTony LIU
arch/arm/mm part - After USB driver prime a bulk transfer(whatever IN or OUT, take OUT for example) on ep1, only one dTD is primed, an USB Interrupt (bit 0 of USBSTS) will be issued, and find that endptcomplete register is 0x2 which means an OUT transfer on ep1 is completed, at this time the ep1 out queue head status is 0x1e18000, and next dtd pointer is 0x1 which means transfer is done and everything is OK, while the dTD token status is 0x2008080 which means this dTD is still active, not completed yet. - Audio SDMA and Ethernet have the similar issue - root cause is not found yet - work around: change the non-cacheable bufferable memory to non-cacheable non-bufferable memory to make this issue disappear. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217721-2 add dma_pool_alloc_nonbufferable interfaceTony LIU
include/linux head file part - After USB driver prime a bulk transfer(whatever IN or OUT, take OUT for example) on ep1, only one dTD is primed, an USB Interrupt (bit 0 of USBSTS) will be issued, and find that endptcomplete register is 0x2 which means an OUT transfer on ep1 is completed, at this time the ep1 out queue head status is 0x1e18000, and next dtd pointer is 0x1 which means transfer is done and everything is OK, while the dTD token status is 0x2008080 which means this dTD is still active, not completed yet. - Audio SDMA and Ethernet have the similar issue - root cause is not found yet - work around: change the non-cacheable bufferable memory to non-cacheable non-bufferable memory to make this issue disappear. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217721-1 add dma_alloc_noncacheable interfaceTony LIU
arch/arm/include part - After USB driver prime a bulk transfer(whatever IN or OUT, take OUT for example) on ep1, only one dTD is primed, an USB Interrupt (bit 0 of USBSTS) will be issued, and find that endptcomplete register is 0x2 which means an OUT transfer on ep1 is completed, at this time the ep1 out queue head status is 0x1e18000, and next dtd pointer is 0x1 which means transfer is done and everything is OK, while the dTD token status is 0x2008080 which means this dTD is still active, not completed yet. - Audio SDMA and Ethernet have the similar issue - root cause is not found yet - work around: change the non-cacheable bufferable memory to non-cacheable non-bufferable memory to make this issue disappear. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217128 MX6: support for binding and unbinding console driverWayne Zou
Enable CONFIG_VT_HW_CONSOLE_BINDING to support for binding and unbinding console driver Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-25ENGR00217717 mfgtool firmware will crash during mfgtool runningTony LIU
- the root cause of this issue is there is no protection for the resource which will be accessed by multiple thread Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217719 usb gadget msc may enumeration fail if msc storage response slowTony LIU
- communication between the usb driver and msc class driver is using raise_exception/handle_excpetion, such mechaism can only have two events(exceptions) at most, one is on processing and another is store to be executed after the current one completed. If the first one processing is very slow, and the third one occur, then the second one will be overwriten by the third one and then the second event is lost and then enumeration failed - since it is the linux community code, it is hard to change the whole frame work, currently only a work around is provided - because this issue is brought in when the first reset event, when this event occur, a lun sync will happen and it will cost much time, but in fact this lun sync is not necessary for the first reset event, the work around is to skip this lun sync. Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217716 mfgtool host frequently reset bus during transferTony LIU
- the response in csw to request sense will be 1 due to UTP change some storage information - host will reset the bus if response to request sense is 1 - change the response to 0 if CONFIG_FSL_UTP is defined Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-07-25ENGR00217732-2: Add dummy clock for DCP/RNGB.Terry Lv
Add dummy clock for DCP/RNGB. Signed-off-by: Terry Lv <r65388@freescale.com>
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