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LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.
Bug 827199
Change-Id: I8ec066d8c38c34b0bd9314abe20b2e01b4a3a293
Reviewed-on: http://git-master/r/42113
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 2b96783fd25eb2153cab2fb6ff92b2bacc809bed.
Recovery process is hanging because of this change.
Bug 848403
Bug 800107
Change-Id: I1b7d3f6c08d6db40eda077e5f128c4bf3be681ac
Reviewed-on: http://git-master/r/41818
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Kaushik Sen <ksen@nvidia.com>
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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CTS File permission test expects there shouldn't be any writable
permission for Group and Others for any file in kernel.
Bug 840409
Change-Id: Ia31aa02e9e49840823ec080ab7d42c2c197f0602
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/41540
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
Tested-by: Manoj Gangwal <mgangwal@nvidia.com>
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Changed dev_err to pr_err because 'dd' can be NULL.
Added NULL checking before clock disable of engine->pclk
Reviewed-on: http://git-master/r/37857
(cherry picked from commit 851ffd0a30cbe67a5033a9792825b319f0bcd7ed)
Change-Id: Ib6d688432b89d37eb9b388b364303850afe94d53
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41510
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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- reset intr_status if error occur while encrypt/decrypt
- rename iram variables to _phys and _virt
- use bsea for rng
- remove unwanted macros from the header file
Bug 833165
Bug 778258
Reviewed-on: http://git-master/r/35830
(cherry picked from commit b3c905c825c16cfff9fe43681f616aa4a0314a8d)
Change-Id: I4c76bc87ae4dbf5cab7a49ff070cf95323124537
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41509
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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instead of checking for NULL, IS_ERR_OR_NULL() should
be used to check the validity of a clock handle
Reviewed-on: http://git-master/r/35619
(cherry picked from commit f69d9be1947af12d634bf6a8da4fd44bdf58193d)
Change-Id: Id33535b01e8591b0ab580def009c737278b72717
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41508
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Required to pass android.net.cts tests.
Bug 789868
Change-Id: Ie43c02b4c4b03d929744678c399bbad980658ed3
Reviewed-on: http://git-master/r/41234
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Tested-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add "Capture" keyword in capture controls of WM8903
Required for correct identification of capture switch control
in nvaudioalsamixer
Bug 789860
Change-Id: I39cf7f6edd3552bba2c042edc3859a81b30e88af
Reviewed-on: http://git-master/r/40835
Tested-by: Viraj Karandikar <vkarandikar@nvidia.com>
Reviewed-by: Gautam Moharir <gmoharir@nvidia.com>
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set_clk_rate for sclk which is parent of avp clock.
Bug 843725
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/39772
(cherry picked from commit 7ca01f6ae2071c5adac467552bdedb54d158d51b)
Change-Id: I8549554b1515be39722fe5c0da5a2ad037e3d2f2
Reviewed-on: http://git-master/r/40598
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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AVP wants to know the clock freq of the modules like
VDE and AVP itself.
Added interface to handle the get clock message from AVP.
Bug 843882
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/38506
(cherry picked from commit 7ab89380014b5b5f368548615f5ab2e144b3e57a)
Change-Id: I83e06877f36ed2901e7bd481915d3b38929cd52a
Reviewed-on: http://git-master/r/40597
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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AVP service driver responds error to AVP for invalid or unsupported
service IDs.
Bug 843473
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/39225
(cherry picked from commit 11237d6a408d6ca7aea619e47b02ddf7e158945d)
Change-Id: I53d185b8b5a7cd720723a51ad7f0ad4aeafe3b3d
Reviewed-on: http://git-master/r/40596
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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this change will allow clock rate control from AVP.
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/31839
(cherry picked from commit 82f7aa65a57b808a5b028918c7b1b997f8a76db7)
Change-Id: I218d0661d107db2eecdc1254fa399a902e49acc7
Reviewed-on: http://git-master/r/40595
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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- Changed the kzalloc param from node to block.
- 'CHECK_CONDITION((physical_address < 0), ...' is not valid,
because the physical_address value is unsigned value.
- Fixed uninitialized values
Bug 825511
Change-Id: Ib579c591c39396533eea8ecc42e92373ed49bd18
Reviewed-on: http://git-master/r/37862
(cherry picked from commit 06d905e9ed14d28224d5f59acf75b4de503f8796)
Reviewed-on: http://git-master/r/39782
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Making sure that keyboard controller should be in the wakeup mode
before going to suspend.
Doing additional check in suspend.
bug 845098
Change-Id: Ia645be1881390de9d18cf03633cef47e654209e2
Reviewed-on: http://git-master/r/40221
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com>
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Change-Id: I115ab2464378df094dae67268c919980bd72b843
Reviewed-on: http://git-master/r/39785
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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The IAA watchdog has been added to work around flaky controllers that
sometimes miss IAA interrupts. We don't need it on Tegra and it is known
to cause panics. Increase it to a large value to make sure it does not
fire unexpectedly.
Signed-off-by: Benoit Goby <benoit@android.com>
Reviewed-on: http://git-master/r/40065
(cherry picked from commit efd61c3725c8759b42550a97e9867e46a77dbf10)
Change-Id: Ia35b06cd9d8f7948ee33aa5793a63d6e929df7f4
Reviewed-on: http://git-master/r/40634
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Carveout memory leak occured in video playback on abnormal termination as the
tegra overlay driver didn't had the implementation to reduce the usage count of
nvmap client on device closure.
Hence on abnormal termination of mediaserver, the carveout memory remained
allocated causing memory leak.
The usage count of nvmap client for overlay driver is incremented on
ioctl TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD.It should be decremented on
device closure.
Added the code to decrement the uage count of nvmap client on release, so that
the client and the carveout memory is free'd whenever the count reaches zero
on successful as well as abnormal termination of mediaserver process.
Similar implementation is done by NvHost channel driver,
The NvHost drivers takes care of nvmap client usage count.i.e. decrement the
uasge count of nvmap client which is incremented by
NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD ioctl.
Bug 845676
Change-Id: I17b8d3c34adba5352af61355d8648b2611b62ef2
Reviewed-on: http://git-master/r/40157
Tested-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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fb_mmap maps current window so that content of screen is
accessible through mmap sys call to user space components.
BUG 832288
Change-Id: I10ccb0b70c951f6d43dbd8a7a1e59e86c0ee75e9
Reviewed-on: http://git-master/r/39204
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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bug: 842809
Change-Id: I68f8a4c358c490c0b66ee55f49de460aced50139
Reviewed-on: http://git-master/r/40096
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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Dvc I2C_DONE_INTR_EN interrupt bit is always enable into dvc
control register3.During normal transaction on dvc i2c bus
sometimes one transaction written two times in TX fifo buffer
because of triggered dvc interrupt.This is causing to corrupt
the next transaction header and send wrong address over dvc
i2c bus.To solve this issue dvc i2c interrupt has to disable
during filling of Tx fifo and enable after that.
Writing last packet into Tx Fifo is generating i2c interrupt
immediately if IE bit is enable in Packet header. Data shared
between isr and normal thread are not in sync. So alway update
these data before writing into Tx fifo.
Updated the following things in code:
(1) Add the code to mask/unmask I2C_DONE_INTR_EN into dvc control reg3
(2) Always updates the i2c driver required field structure data before
writing into Tx Fifo register.
(3) Add the code to handle tx fifo overflow condition also.
(4) Put delay before resetting the controller
BUG 839528
Change-Id: I7780411b474a20f985e1f7993e5ccccbab619bbc
Reviewed-on: http://git-master/r/39985
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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some users might enter fuse data starting
with 0x/x. this will mess up the fuse programming.
do not consider 0x/x while programming the fuses.
also fix some compilation warnings
Reviewed-on: http://git-master/r/#change,38933
(cherry picked from commit fc8e1e492ac362a44ea6254759431d8f1fb1695c)
Bug 836963
Change-Id: If0503d4e22479e2ce230d53f538eea16d39817df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/39614
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
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- vdd_core needs to be 1.14V min before fuse
write/read
- add wait_for_idle before accessing fuses
- add proper programming of PRIV2INTFS field
Bug 841766
Reviewed-on: http://git-master/r/#change,37618
(cherry picked from 8430b859578af1c0a25954d7b018430941943892)
Bug 836963
Change-Id: I9ec96f54c39834d42043f440b087c7498b1ecd73
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/39613
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
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Providing the uart platform data to select the clock source
from given parent list of clocks. The driver will select
the clock source with minimum error between calculated and
requested baudrate.
bug 825530
Change-Id: If6b882b2fb507cee2553136a3b7f98f0571964ed
Reviewed-on: http://git-master/r/39011
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
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BUG_ON() function has wrong comparision.
the comparision should be '>='. (not '>')
Change-Id: I39453cc02615236b52aa04be076184da35df8e94
Reviewed-on: http://git-master/r/39503
Reviewed-by: BK Kim <bkk@nvidia.com>
Tested-by: BK Kim <bkk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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-Setting the minimum clock at enabling clock
-Enabling controller clock before MMC_POWER_UP to ensure
proper register read/write
-Limit max sdio clk to 24MHz for wifi on whistler.
whistler only supports up to 24MHz.
bug 834281
bug 845180
Change-Id: I9993a8bd9ab99af21c81d42f91175279f91cf0e4
Reviewed-on: http://git-master/r/39525
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Adding clk_limit to platform data used at sdhci host driver
to limit clock. whistler only supports up to 24MHz.
bug 845180
Change-Id: Ifb872359095d0f2276d417ab1edc3cec4d79a52f
Reviewed-on: http://git-master/r/39524
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Bug 841766
Reviewed-on: http://git-master/r/#change,37617
(cherry picked from commit b0d7c345cca68450cd433f626947054d42403d52)
Bug 836963
Change-Id: I37fa7a0e65f42d17c06f69917f81392094022a25
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/39612
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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keep fuse clock always enabled to allow fuse
read writes from multiple clients
Bug 841766
Reviewed-on: http://git-master/r/#change,38402
(cherry picked from commit e507984a9a8b5d1e012d5157f3259ed54e354ad1)
Bug 836963
Change-Id: Ia6b554c861e292af9c9d1a9ebd47b17a2ce170d7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/39611
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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The key-matrix is updated for the case scroll-wheel is not enabled.
Bug 847651
Change-Id: I904fd16b284dde95836601378dcb049a97766393
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/39553
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Scrollwheel driver is not needed on phone platforms since we already
have touch-screen on it.
Hence the scrollwheel driver on Whistler is disabled; it was also
causing problems in suspend-resume use-cases.
Bug 841686
Change-Id: I730ba3fb126619ed81caad6f801b1d8876d90d39
Reviewed-on: http://git-master/r/39517
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Tested-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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In the function tegra_otg_probe(), usbd clock is kept on
after probe function completes. Fix this by disabling the clock
before exiting the probe function if usb hotplug is not enabled.
Bug 829628
Change-Id: I2ec96fedb2ed04a9c39f3c7d34cb86fdac821822
Reviewed-on: http://git-master/r/39354
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
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Disable usb clock when no cable is connected.
Bug 829628
Change-Id: Idabe72093ae1fc1a236b0173da93813f07f3501c
Reviewed-on: http://git-master/r/39353
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
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1. The usb UTMIP controllers are set to reset mode when there is no usb cable.
2. Power down the reciever circuitory.
3. Set the OTG_PD for instances which do not use OTG.
4. Turn off the pad power when hotplug support is not supported.
Bug 829628
Change-Id: Icbf82da7d3f35ea882d8a212a01d04c4d536fd0d
Reviewed-on: http://git-master/r/39352
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
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Added support for auto control of RTS.
Bug 825938
Change-Id: Id6f8a26f2178acb9dd8c54069fde4dd879e9d5f1
Reviewed-on: http://git-master/r/39363
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Using proper variable name for uart related api and variables.
Change-Id: I1f431357c3cfacba9d5eea5b9e9da872b498df20
Reviewed-on: http://git-master/r/39012
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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update headers for camera files
bug 846086
Change-Id: Id3e2a9e4f753ca0c9af2b43d49f1d9b49e99e6d7
Reviewed-on: http://git-master/r/39138
Tested-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Gilbert Yeung <gyeung@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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pll_m initialized to 0 so that it stays at the frequency configured
by BCT.
For AP25 pll_m runs at 760MHz. Peripherals connected to pll_m and
running at frequency not multiple of 760MHz switched to pll_c.
Bug 821534
Change-Id: I390b16a31194ad3efe79e68dfbcf371e225cfc70
Reviewed-on: http://git-master/r/36050
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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Relaxed bus set rate success condition: instead of exact rate require
closest rate below the request (makes bus clocks configurable from
sources/PLLs with variable frequencies).
Bug 821534
Change-Id: I491f8841cf2ca206a54beb1c24c84f470d08eb4b
Reviewed-on: http://git-master/r/38868
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
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EMC DVFS table added for AP25 with 380/190 ladder.
Bug 821534
Change-Id: Ic5f936924b4d6b2f3ce52b412e4bb5f2a57ac661
Reviewed-on: http://git-master/r/36051
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 842809
Change-Id: Idb3fde5c3287143e4e67a2083fddd1a07f1d630f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38960
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Avoid Display Controller (DC) syncpoint increments if that instance of DC is
not enabled.
Bug 793874
(cherry picked from commit 5be1dd4dd04db4a4c4e8004e364d504bf9f56857)
Change-Id: I91f05694044bbefb15c3b92047be3be47b2ceacc
Reviewed-on: http://git-master/r/38464
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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dc lock is head while flush occurred, but functions called by workers need
take the dc lock to proceed.
Bug 807015
(cherry picked from commit 2e12d89ac51fe1358f0b01b9ff5cb4978fdcbe9d)
Change-Id: Ib358685c478c05a8f95c926e708de12b6a3556fb
Reviewed-on: http://git-master/r/38463
Reviewed-by: Linqiang Pu <dpu@nvidia.com>
Tested-by: Linqiang Pu <dpu@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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Adding the uart initialization as separate function and handling the
clock and device registration.
It also provides all possible clock source and their handle to
driver so that driver can use this clock information to select baud
rate dynamically.
bug 842665
Change-Id: Ib5ec368b8ceb2df47f48f72aefee4af1b113b913
Reviewed-on: http://git-master/r/38428
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Adding the clock detail entry for the driver serial8250.
bug 842665
Change-Id: I38c4195a3b6522978b60f9212053589c2eafce53
Reviewed-on: http://git-master/r/38427
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Finding the best clock source for uart controller which can
generate the clock rate having minimum error between requested
baudrate and configured baudrate.
bug 842665
Change-Id: I9a750f578f7dfd7ea2138fdf1bcec30b0f3392d5
Reviewed-on: http://git-master/r/38426
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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To improve the power consumption situation for MP3 playback
the scaling governor is set to conservative when display
is turned off and the default governor is saved. The governor
is restored when display is turned on.
Bug 817727
(cherry picked from commit 4c0e831af450f0e5af65e8d09c8d347d23073b65)
(cherry picked from http://git-master/r/35000)
Change-Id: I73fc9e2851eae36c488e17cb97423c44101e1ba5
Reviewed-on: http://git-master/r/37187
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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disable_irq() will do schedule() if threaded IRQ handler is running. But
suspend_cpu_complex() is called from IRQ disabled.
disable_irq_nosync() should be used here because it will not sleep.
BUG 841808
Change-Id: Ib13e31adc7a8591c668dd729995e50e0db885641
Reviewed-on: http://git-master/r/37505
Reviewed-on: http://git-master/r/38191
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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HDMI connect/disconnect will not affect the suspended device.
bug 835157
Change-Id: Ie094a2dcebdca2e405f3e02b4de3d12d0cb665f0
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/37174
(cherry picked from commit 31f69bbe2e832a7dfa7678bb965b3461f421e0f5)
Reviewed-on: http://git-master/r/38089
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Change-Id: I32755368de7059a8aa08b114af84d952adf16a1d
Reviewed-on: http://git-master/r/37981
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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To support the 25.2MHz pixel clock frequency required for CEA-861-B format 1: 640x480p at 59.94Hz
bug 837571
Change-Id: I33d5c82bbc9c79fd43d86abf72d5b94b1c723dd5
Reviewed-on: http://git-master/r/37916
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
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