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2014-04-30kernel: remove CONFIG_USE_GENERIC_SMP_HELPERSChristoph Hellwig
We've switched over every architecture that supports SMP to it, so remove the new useless config variable. Conflicts: arch/arm/Kconfig block/blk-mq.c Change-Id: Ic19c3ac07a38a1636d6aa2fed5e55a58833f9b2c Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: Jan Kara <jack@suse.cz> Cc: Jens Axboe <axboe@kernel.dk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 0a06ff068f1255bcd7965ab07bc0f4adc3eb639a) Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30mm: allow pgtable_page_ctor() to failKirill A. Shutemov
Change pgtable_page_ctor() return type from void to bool. Returns true, if initialization is successful and false otherwise. Current implementation never fails, but it will change later. (cherry picked from commit 390f44e2aa2ab83f08231d7d05f066dc3494490e) Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-30arm64: handle pgtable_page_ctor() failKirill A. Shutemov
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-30mm/arch: use NUMA_NO_NODEJianguo Wu
Use more appropriate NUMA_NO_NODE instead of -1 in all archs' module_alloc() Signed-off-by: Jianguo Wu <wujianguo@huawei.com> Acked-by: David Rientjes <rientjes@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 40c3baa7c66f1352521378ee83509fb8f4c465de) Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30constify copy_siginfo_to_user{,32}()Al Viro
Conflicts: arch/x86/ia32/ia32_signal.c Change-Id: I701cb58fffb756a2d29e7c828728d149c35e6c6a Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> (cherry picked from commit ce3959604878c1c693979ec552069dc8bdb5ccde) Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h"Chen Gang
In current kernel wide source code, except other architectures, only s390 scsi drivers use atomic_clear_mask(), and arm/arm64 need not support s390 drivers. So remove atomic_clear_mask() from "arm[64]/include/asm/atomic.h". (cherry picked from commit aed3a4ed7222ae37860ae33cbad3ea7a6b2eaf8e) Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30ARM64: /proc/interrupts: display IPIs of online CPUs onlySudeep KarkadaNagesha
The non-IPI interrupts are displayed only for the online cpus from show_interrupts in kernel/irq/proc.c before calling arch_show_interrupts(). As a result, the column headers and the IPI count don't match if any CPU is offline. This patch fixes show_ipi_list to display IPIs for online CPUs only. (cherry picked from commit 67317c2689567c24d18e0dd43ab6d409fd42dc6e) Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: compat: Clear the IT state independent of the 32-bit ARM or Thumb-2 modeT.J. Purtell
The ARM architecture reference specifies that the IT state bits in the PSR must be all zeros in ARM mode or behavior is unspecified. If an ARM function is registered as a signal handler, and that signal is delivered inside a block of instructions following an IT instruction, some of the instructions at the beginning of the signal handler may be skipped if the IT state bits of the Program Status Register are not cleared by the kernel. (cherry picked from commit aa62c2091129af81a172350b718eb35d5448cebc) Change-Id: I20632eb816ba4a2fb9db0913e8129fab84a46f7c Signed-off-by: T.J. Purtell <tj@mobisocial.us> [catalin.marinas@arm.com: code comment and commit log updated] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: module: ensure instruction is little-endian before manipulationWill Deacon
Relocations that require an instruction immediate to be re-encoded must ensure that the instruction pattern is represented in a little-endian format for the manipulation code to work correctly. This patch converts the loaded instruction into native-endianess prior to encoding and then converts back to little-endian byteorder before updating memory. Change-Id: I84a8946f66e6eb303d81b7b9198d95cca6b8d42f (cherry picked from commit 122e2fa0d310d262cb85cf0b003032e5d2bc2ae7) Signed-off-by: Will Deacon <will.deacon@arm.com> Tested-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: defconfig: Enable CONFIG_PREEMPT by defaultCatalin Marinas
This way we can spot early bugs when just testing with the default config. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: fix access to preempt_count from assembly codeMarc Zyngier
preempt_count is defined as an int. Oddly enough, we access it as a 64bit value. Things become interesting when running a BE kernel, and looking at the current CPU number, which is stored as an int next to preempt_count. Like in a per-cpu interrupt handler, for example... Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Change-Id: I061cc6b76b282064535a919ec589cf9d80b73bed Using a 32bit access fixes the issue for good. (cherry picked from commit 717321fcb58ed95169bf344ae47ac6098ba5dfbe) Cc: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: use generic RW_DATA_SECTION macro in linker scriptMark Salter
The .data section in the arm64 linker script currently lacks a definition for page-aligned data. This leads to a .page_aligned section being placed between the end of data and start of bss. This patch corrects that by using the generic RW_DATA_SECTION macro which includes support for page-aligned data. Conflicts: arch/arm64/kernel/vmlinux.lds.S Change-Id: Ib951dd0b6839cb3af7c6aca75b2b022e513782c4 Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 3c620626c0cd4cfca856d70a846398275b48a768) Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30ARM64: DT: define ARM64 specific arch_match_cpu_phys_idSudeep KarkadaNagesha
OF/DT core library provides architecture specific hook to match the logical cpu index with the corresponding physical identifier. On ARM64, the MPIDR_EL1 contains specific bitfields(MPIDR_EL1.Aff{3..0}) which uniquely identify a CPU, in addition to some non-identifying information and reserved bits. The ARM cpu binding defines the 'reg' property to only contain the affinity bits, and any cpu nodes with other bits set in their 'reg' entry are skipped. This patch overrides the weak definition of arch_match_cpu_phys_id with ARM64 specific version using MPIDR_EL1.Aff{3..0} as cpu physical identifiers. (cherry picked from commit 6e15d0e04bfeaa5662a289ee915273307326e45a) Signed-off-by: Ishan Mittal <imittal@nvidia.com> Conflicts: arch/arm64/kernel/setup.c Change-Id: I5a5b8d93040453fea70e56dd1a1e5cf1eca71e4d Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30ARM: 7941/2: Fix incorrect FDT initrd parameter overrideBen Peddell
Commit 65939301acdb (arm: set initrd_start/initrd_end for fdt scan) caused the FDT initrd_start and initrd_end to override the phys_initrd_start and phys_initrd_size set by the initrd= kernel parameter. With this patch initrd_start and initrd_end will be overridden if phys_initrd_start and phys_initrd_size are set by the kernel initrd= parameter. Fixes: 65939301acdb (arm: set initrd_start/initrd_end for fdt scan) (cherry picked from commit 4c235cb9e35407bdb4a2debeef4dc8721e8f91f2) Conflicts: arch/arm/mm/init.c Change-Id: Ie88bf6e12b69dc99bfd7f40c5d9c09ab6fbe65c1 Signed-off-by: Ben Peddell <klightspeed@killerwolves.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-04-30arm64: allow ioremap_cache() to use existing RAM mappingsMark Salter
Some drivers (ACPI notably) use ioremap_cache() to map an area which could either be outside of kernel RAM or in an already mapped reserved area of RAM. To avoid aliases with different caching attributes, ioremap() does not allow RAM to be remapped. But for ioremap_cache(), the existing kernel mapping may be used. Conflicts: arch/arm64/mm/ioremap.c (cherry picked from commit c04e8e2fe5e0163fd37ccec7f538be8fa63be40e) Change-Id: I9668fef22e3489fd5f2b4749e3bfafb7f8899f79 Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30percpu: Make __verify_pcu_ptr handle per cpu pointers to arraysChristoph Lameter
__verify_pcpu_ptr() will cause a compilation failure if the type of the pointer is a pointer to a fixed array of objects. Adding zero to the pointer converts the type of pointer to that pointing to a single object of the array. (cherry picked from commit abec1a806e0c3cf168999667d5fb6218398ef12a) Change-Id: I07a9df1e204aa5173fe66a4ad81e827422eeadca Signed-off-by: Christoph Lameter <cl@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-04-30ARM: 7862/1: pcpu: replace __get_cpu_var_usesChristoph Lameter
This is the ARM part of Christoph's patchset cleaning up the various uses of __get_cpu_var across the tree. The idea is to convert __get_cpu_var into either an explicit address calculation using this_cpu_ptr() or into a use of this_cpu operations that use the offset. Thereby address calculations are avoided and fewer registers are used when code is generated. [will: fixed debug ref counting checks and pcpu array accesses] Conflicts: arch/arm/kvm/arm.c arch/arm64/kernel/hw_breakpoint.c (cherry picked from commit 1436c1aa626d0bc0e35c5c5231127086e80ab24a) Change-Id: Ie748770ed78e13d1f80ba0da43d20b6a123e2be7 Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Christoph Lameter <cl@linux.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: update 32-bit kuser helpers to ARMv8Robin Murphy
This patch updates the barrier semantics in the kuser helper functions to take advantage of the ARMv8 additions to AArch32, which are guaranteed to be available in situations where these functions will be called. Note that this slightly changes the cmpxchg functions in that they are no longer necessarily full barriers if they return 1. However, the documentation only states they include their own barriers "as needed", not that they are obligated to act as a full barrier for the caller. (cherry picked from commit d0f38f9130b7683e39611c5a661349e301ee43c8) Change-Id: I1e2f3f1df31aaced5ba735b2803c4baf01752e86 Signed-off-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> CC: Matthew Leach <matthew.leach@arm.com> CC: Dave Martin <dave.martin@arm.com> CC: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: perf: fix event number maskVinayak Kale
This patch fixes ARMV8_EVTYPE_* macros since evtCount (event number) field width is 10bits in event selection register. (cherry picked from commit c019de3de61387d224ba4738e3d196aa24c88844) Change-Id: I06c3d6e197f7f0d94321a67b21bef64c9d78e01f Signed-off-by: Vinayak Kale <vkale@apm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: kconfig: allow CPU_BIG_ENDIAN to be selectedWill Deacon
This patch wires up CONFIG_CPU_BIG_ENDIAN for the AArch64 kernel configuration. Selecting this option builds a big-endian kernel which can boot into a big-endian userspace. (cherry picked from commit a872013d6d03ab63736a01dcd9747580be3a6b70) Change-Id: I71aed977b2abbed3c44d395063a0e2f911fc2dfc Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: Fix the endianness of arch_spinlock_tCatalin Marinas
The owner and next members of the arch_spinlock_t structure need to be swapped when compiling for big endian. (cherry picked from commit 4a12cae7ef2612eb094c4b48e8b37cf837e3df55) Change-Id: I2822f9b66b735a922eb6ef01971fd624f8ddeaa5 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Matthew Leach <matthew.leach@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
2014-04-30arm64: big-endian: write CPU holding pen address as LEMatthew Leach
Currently when CPUs are brought online via a spin-table, the address they should jump to is written to the cpu-release-addr in the kernel's native endianness. As the kernel may switch endianness, secondaries might read the value byte-reversed from what was intended, and they would jump to the wrong address. As the only current arm64 spin-table implementations are little-endian, stricten up the arm64 spin-table definition such that the value written to cpu-release-addr is _always_ little-endian regardless of the endianness of any CPU. If a spinning CPU is operating big-endian, it must byte-reverse the value before jumping to handle this. (cherry picked from commit 710be9ac4ea0d2e02a2c4aa625795e65bf3db5b1) Change-Id: Idf141ebd1be56b7259748cadf3d0982e4397affb Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: big-endian: set correct endianess on kernel entryMatthew Leach
The endianness of memory accesses at EL2 and EL1 are configured by SCTLR_EL2.EE and SCTLR_EL1.EE respectively. When the kernel is booted, the state of SCTLR_EL{2,1}.EE is unknown, and thus the kernel must ensure that they are set before performing any memory accesses. This patch ensures that SCTLR_EL{2,1} are configured appropriately at boot for kernels of either endianness. (cherry picked from commit 9cf71728931a4073b9e3a4bcbf9dada86bc98370) Change-Id: I05542b3c0bda8db0404b767947741767206906b2 Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> [catalin.marinas@arm.com: fix SCTLR_EL1.E0E bit setting in head.S] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: head: create a new function for setting the boot_cpu_mode flagMatthew Leach
Currently, the code for setting the __cpu_boot_mode flag is munged in with el2_setup. This makes things difficult on a BE bringup as a memory access has to have occurred before el2_setup which is the place that we'd like to set the endianess on the current EL. Create a new function for setting __cpu_boot_mode and have el2_setup return the mode the CPU. Also define a new constant in virt.h, BOOT_CPU_MODE_EL1, for readability. (cherry picked from commit 828e9834e9a5b7e61046aa3c5f603a4fecba2fb4) Change-Id: Id12eef061097776b826ba2775d31479d6b466e65 Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: asm: add CPU_LE & CPU_BE assembler helpersMatthew Leach
Add CPU_LE and CPU_BE to select assembler code in little and big endian configurations respectively. (cherry picked from commit e68bedaa03c950ae8045e7899e7a6b2a97d1bf41) Change-Id: I3fe494a0683b43ce5d3235862da9df797e7300de Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: big-endian: don't treat code as data when copying sigret codeMatthew Leach
Currently the sigreturn compat code is copied to an offset in the vectors table. When using a BE kernel this data will be stored in the wrong endianess so when returning from a signal on a 32-bit BE system, arbitrary code will be executed. Instead of declaring the code inside a struct and copying that, use the assembler's .byte directives to store the code in the correct endianess regardless of platform endianess. (cherry picked from commit a1d5ebaf8ccdd100f45042ce32c591867de04ac3) Change-Id: Ia246bef66dd1e30b677a5a31e9522dfd9818a2bb Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: compat: correct register concatenation for syscall wrappersMatthew Leach
The arm64 port contains wrappers for arm32 syscalls that pass 64-bit values. These wrappers concatenate the two registers to hold a 64-bit value in a single X register. On BE, however, the lower and higher words are swapped. Create a new assembler macro, regs_to_64, that when on BE systems swaps the registers in the orr instruction. (cherry picked from commit 55b89540b0d8d031f90e3d711ec0df3f797ecc61) Change-Id: I5b5811e0bb51d7a150c7b45339b3f0e765391d22 Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: compat: add support for big-endian (BE8) AArch32 binariesWill Deacon
This patch adds support for BE8 AArch32 tasks to the compat layer. (cherry picked from commit a795a38eb91cf72c4a05e72a9c84e317ee179a48) Change-Id: I3c6fe80a87f92edd6888b62da9778984f50e877c Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: setup: report ELF_PLATFORM as the machine for utsnameWill Deacon
uname -m reports the machine field from the current utsname, which should reflect the endianness of the system. This patch reports ELF_PLATFORM for the field, so that everything appears consistent from userspace. (cherry picked from commit 94ed1f2cb5d46533f10262b1b760db7dbec9cf10) Change-Id: Ic4fd6fb98b2eff98ee1445b6a5db0aa18f52ef0e Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: ELF: add support for big-endian executablesWill Deacon
This patch adds support for the aarch64_be ELF format to the AArch64 ELF loader. (cherry picked from commit 5436b5c8305b4ed37c5d11f96c1aaccca63c9ab2) Change-Id: Ie805dab397892a5ac9ba80d4e510c2beb53f9a41 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: big-endian: fix byteorder includeWill Deacon
For big-endian processors, we must include linux/byteorder/big_endian.h to get the relevant definitions for swabbing between CPU order and a defined endianness. (cherry picked from commit c194520ada7c8f2eddec5ebf24982483b49736a0) Change-Id: I8b8d0f227ec364e36876e1b4890454348a676af7 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: big-endian: add big-endian support to top-level arch MakefileWill Deacon
This patch adds big-endian support to the AArch64 top-level Makefile. This currently just passes the relevant flags to the toolchain and is predicated on a Kconfig option that will be introduced later on. (cherry picked from commit a0974e6e217aead196033d72f898e2acb575304d) Change-Id: Ia88a4e06ed07a701f68b1e894065420c9fe74179 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: Export __copy_in_user() to modulesCatalin Marinas
This function may be called from loadable modules, so it needs exporting. (cherry picked from commit 2a3f912c782f2364f5e5813ab66ca6c92fb43acb) Change-Id: Iba5f5d4c9d371d38b1b4efc1006c71b9fdb0201c Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Loc Ho <lho@apm.com>
2014-04-30arm64: cmpxchg: implement cmpxchg64_relaxedWill Deacon
This patch introduces cmpxchg64_relaxed for arm64 using the existing cmpxchg_local macro, which performs a cmpxchg operation (up to 64 bits) without barrier semantics. (cherry picked from commit cf10b79a7d88edc689479af989b3a88e9adf07ff) Change-Id: Ia5da0af964dac47203c18d276c92aa5fee218307 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: lockref: add support for lockless lockrefs using cmpxchgWill Deacon
Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can deal with 8-bytes (as one would hope!). This patch wires up the cmpxchg-based lockless lockref implementation for arm64. Conflicts: arch/arm64/Kconfig (cherry picked from commit 5686b06cea34e31ec0a549d9b5ac00776e8e8d6d) Change-Id: I7419ef6b1241530df030eaa5e754659f902d4b85 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: remove unnecessary prom.h includeRob Herring
Remove unnecessary prom.h include in preparation to make prom.h optional. (cherry picked from commit e2d1c994f7194e933236bd874b2d7f31b678bb94) Change-Id: Idda01e7aa133ed1eb1acef84a7ff44631c807aa8 Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: Will Deacon <will.deacon@arm.com>
2014-04-30arm64: define DMA_ERROR_CODEStefano Stabellini
(cherry picked from commit 25b719d7b45947a79d298414cdfb5ec8fadf0ec8) Conflicts: arch/arm64/include/asm/dma-mapping.h Acked-by: Catalin Marinas <catalin.marinas@arm.com> CC: will.deacon@arm.com Changes in v8: - cast to dma_addr_t before returning. Change-Id: Ic989bf507c0d330b0a7b67f9b4ed6889cd458a39 Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30of: remove early_init_dt_setup_initrd_archRob Herring
All arches do essentially the same thing now for early_init_dt_setup_initrd_arch, so it can now be removed. Conflicts: arch/arm/mm/init.c arch/c6x/kernel/devicetree.c arch/powerpc/kernel/prom.c (cherry picked from commit 29eb45a9ab4839a1e9cef2bcf369b918c9c4fcad) Acked-by: Vineet Gupta <vgupta@synopsys.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Mark Salter <msalter@redhat.com> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonas Bonn <jonas@southpole.se> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Grant Likely <grant.likely@linaro.org> Change-Id: I84b59cec16fa7e96fa8ff3de04aa959f7039a7a9 Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: set initrd_start/initrd_end for fdt scanRob Herring
In order to unify the initrd scanning for DT across architectures, make arm64 use initrd_start and initrd_end instead of the physical addresses. Conflicts: arch/arm64/mm/init.c (cherry picked from commit ec2eaa73b3d21776f46797a2eef983d7be09a964) Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Change-Id: I79f9ae06667dbcc3e4f4c08612a5e4a1f82d7885 Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30of: create default early_init_dt_add_memory_archRob Herring
Create a weak version of early_init_dt_add_memory_arch which uses memblock. This will unify all architectures except ones with custom memory bank structs. Conflicts: arch/openrisc/kernel/prom.c (cherry picked from commit 068f6310b965d67d57f89ebf4c539e5933754366) Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Jonas Bonn <jonas@southpole.se> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Cc: microblaze-uclinux@itee.uq.edu.au Cc: linux@lists.openrisc.net Cc: devicetree@vger.kernel.org Change-Id: I8f3bd8d9d0816666cf90363e16f596b365db4632 Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30of: Introduce common early_init_dt_scanRob Herring
Most architectures scan the all the same items early in the FDT and none are really architecture specific. Create a common early_init_dt_scan to unify the early scan of root, memory, and chosen nodes in the flattened DT. (cherry picked from commit 0288ffcbfdf9b8656e7320c24caa1e4c1d498287) Change-Id: I56ce372cc740ab11a8828d11bf8e508069bdac88 Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@linaro.org>
2014-04-30arm64: include VIRTIO_{MMIO,BLK} in defconfigRamkumar Ramachandra
Currently, development on arm64 is aided by a Foundation_v8 emulator distributed by ARM [1]. To run their kernels, users will execute: $ ./Foundation_v8 --image linux-system.axf --block-device raring-rootfs To mount the raring-rootfs filesystem, the kernel parameter should typically include: root=/dev/vda For this device to be present, the kernel must be compiled with VIRTIO_{MMIO,BLK}. To make this work out-of-the-box, make it part of the default configuration. [1]: https://silver.arm.com/browse/FM00A (cherry picked from commit 4eb507b874035873dafdb381e61935fed7a8ad85) Change-Id: I2b5aac8c03232cce27e47f63118a3f838bbd156a Cc: Will Deacon <will.deacon@arm.com> Cc: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Ramkumar Ramachandra <artagnon@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: include EXT4 in defconfigRamkumar Ramachandra
Most readily available root filesystems are formatted as EXT4 these days. For example, see the raring rootfs that the Debian folk is preparing [1]. [1]: http://people.debian.org/~wookey/bootstrap/rootfs/ (cherry picked from commit ade37198937a52bc3f59c40ffb14cb6688b273b7) Change-Id: I8a8fe7ff0a008fdf50b1c618831323559c394b6a Cc: Will Deacon <will.deacon@arm.com> Cc: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Ramkumar Ramachandra <artagnon@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30ARM64: arch_timer: add support to configure and enable event streamSudeep KarkadaNagesha
This patch adds support for configuring the event stream frequency and enabling it. It also adds the hwcaps as well as compat-specific definitions to the user to detect this event stream feature. (cherry picked from commit 46efe547aca8498d51b64460c02366ae4032ca32) Change-Id: Ibeca9b3629225e83f28924bc6e0860fef1fd253d Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
2014-04-30ARM/ARM64: arch_timer: add macros for bits in control registerSudeep KarkadaNagesha
Add macros to describe the bitfields in the ARM architected timer control register to make code easy to understand. (cherry picked from commit 28061758dc83df445a05af347b5ce55ccd968c03) Change-Id: I8432a0df79a93b5033291b113768682e858961a6 Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.comi> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
2014-04-30arm64: use correct register width when retrieving ASIDMatthew Leach
The ASID is represented as an unsigned int in mm_context_t and we currently use the mmid assembler macro to access this element of the struct. This should be accessed with a register of 32-bit width. If the incorrect register width is used the ASID will be returned in bits[32:63] of the register when running under big-endian. Fix a use of the mmid macro in tlb.S to use a 32-bit access. (cherry picked from commit fc18047c732f6becba92618a397555927687efd3) Change-Id: I0a79931f9222449005fd86e9b8cff53b296f1733 Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30sched, arch: Create asm/preempt.hPeter Zijlstra
In order to prepare to per-arch implementations of preempt_count move the required bits into an asm-generic header and use this for all archs. (cherry picked from commit a787870924dbd6f321661e06d4ec1c7a408c9ccf) Conflicts: arch/c6x/include/asm/Kbuild arch/cris/include/asm/Kbuild arch/h8300/include/asm/Kbuild arch/ia64/include/asm/Kbuild arch/mips/include/asm/Kbuild arch/openrisc/include/asm/Kbuild arch/powerpc/include/asm/Kbuild arch/score/include/asm/Kbuild include/linux/preempt.h Change-Id: I544914d3c23cc50da658296a34f9f2796854e259 Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/n/tip-h5j0c1r3e3fk015m30h8f1zx@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Ishan Mittal <imittal@nvidia.com>
2014-04-30arm64: Widen hwcap to be 64 bitSteve Capper
Under arm64 elf_hwcap is a 32 bit quantity, but it is stored in a 64 bit auxiliary ELF field and glibc reads hwcap as 64 bit. This patch widens elf_hwcap to be 64 bit. (cherry picked from commit 25804e6a96681d5d2142058948e218999e4f547c) Change-Id: I4fd594b82ab12da3733a95a4882761320aa596d2 Signed-off-by: Steve Capper <steve.capper@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arm64: Make do_bad_area() function staticCatalin Marinas
This function is only called from arch/arm64/mm/fault.c. (cherry picked from commit 59f67e16e6b79697241c3fd030e3da300377893e) Change-Id: I7f139f99952934b68f7a7ecb878cdd3d5c0c7fa9 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-30arch: mm: pass userspace fault flag to generic fault handlerJohannes Weiner
Unlike global OOM handling, memory cgroup code will invoke the OOM killer in any OOM situation because it has no way of telling faults occuring in kernel context - which could be handled more gracefully - from user-triggered faults. Pass a flag that identifies faults originating in user space from the architecture-specific fault handlers to generic code so that memcg OOM handling can be improved. (cherry picked from commit 759496ba6407c6994d6a5ce3a5e74937d7816208) Conflicts: arch/arc/mm/fault.c Change-Id: I6ddf37c0feae69fcda0c2db76d2b10ca2a11c619 Signed-off-by: Johannes Weiner <hannes@cmpxchg.org> Reviewed-by: Michal Hocko <mhocko@suse.cz> Cc: David Rientjes <rientjes@google.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: azurIt <azurit@pobox.sk> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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