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2015-04-14PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()Lucas Stach
Use pci_create_root_bus() similar to other PCI host controller drivers. The main problem with pci_scan_root_bus() is that it not only creates the root bus, but also activates all devices on the bus. This triggers PCI device driver probe routines, which fail because resources haven't been allocated. To work around this we made sure that the host controller driver is probed early and finishes resource allocation before any other device drivers are registered. Switching to pci_create_root_bus() allows us to get rid of this special handling. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> (cherry picked from commit 92483df2bad7649caacad60ec7b0f8016e894e11)
2015-04-14PCI: designware: Parse bus-range property from devicetreeLucas Stach
This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. [bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> (cherry picked from commit 4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6)
2015-04-14PCI: imx6: Put LTSSM in "Detect" state before disabling itLucas Stach
This fixes a boot hang observed when the bootloader already enabled the PCIe link for its own use. The fundamental problem is that Freescale forgot to wire up the core reset, so software doesn't have a sane way to get the core into a defined state. According to the DW PCIe core reference manual, configuration of the core may only happen when the LTSSM is disabled, so this is one of the first things we need to do. Apparently this isn't safe to do when the LTSSM is in any state other than "detect" as we observe an instant machine hang when trying to do so while the link is already up. As a workaround, force LTSSM into detect state right before hitting the disable switch. There is still a race window because the LTSSM may transition out of "detect" before we can disable it, but it's the best we can do for now. [bhelgaas: mention race window] Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tim Harvey <tharvey@gateworks.com> (cherry picked from commit 3e3e406e3807235906ee0b7c697664ea6dfd88de)
2015-04-14PCI: designware: Add support for v3.65 hardwareMurali Karicheri
The Keystone PCI controller is based on v3.65 DesignWare hardware. This version differs from newer versions of the hardware in functional areas discussed below that make it necessary to change dw_pcie_host_init() to support v3.65 based PCI controller. 1. No support for ATU port. Any ATU-specific resource handling code is to be bypassed for v3.65 h/w. 2. MSI controller uses application space to implement MSI and 32 MSI interrupts are multiplexed over 8 IRQs to the host. Hence the code to process MSI IRQ needs to be different. This patch allows platform driver to provide its own irq_domain_ops ptr to irq_domain_add_linear() through an API callback from the DesignWare core driver. 3. MSI interrupt generation requires EP to write to the RC's application register. So enhance the driver to allow setup of inbound access to MSI IRQ register as a post scan bus API callback. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> CC: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org> (cherry picked from commit b14a3d1784a9252aa3bbe0bb9d14588be32f18a1)
2015-04-14PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardwareMurali Karicheri
DesignWare v3.65 hardware implements MSI controller registers in application space. This requires updates to the DesignWare core to support controllers based on this older hardware. Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit in the application register. Also, v3.65 hardware uses the MSI_IRQ register in application register space to raise MSI IRQ to the RC from EP. Current code uses the standard mechanism as per PCI spec. So add get_msi_data() to get the address of this register so common code can work on both v3.65 and newer hardware. [bhelgaas: changelog] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org> (cherry picked from commit 2f37c5a81cff2c341fa19fdd132ece6aea30a735)
2015-04-14PCI: designware: Add config access-related pcie_host_ops for v3.65 hardwareMurali Karicheri
DesignWare v3.65 hardware requires application space registers to be configured to access the remote EP config space. To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops. [bhelgaas: changelog] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org> (cherry picked from commit a1c0ae9c24627a12c781ebd9947a6442861f6168)
2015-04-14PCI: dra7xx: Add TI DRA7xx PCIe driverKishon Vijay Abraham I
Add support for PCIe controller in DRA7xx. This driver re-uses the designware core code that is already present in kernel. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 47ff3de911a728cdf9ecc6ad777131902cff62b4)
2015-04-14PCI: designware: Program ATU with untranslated addressKishon Vijay Abraham I
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see only 28-bit addresses. So whenever the CPU issues a read/write request, the 4 most significant bits are used by L3 to determine the target controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff] for the PCIe controller but the PCIe controller will see only [0x00000000-0x0fffffff]. For programming the outbound translation window the *base* should be programmed as 0x00000000. Whenever we try to write to, e.g., 0x20000000, it will be translated to whatever we have programmed in the translation window with base as 0x00000000. This is needed when the dt node is modelled something like this: axi { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0x0 0x20000000 0x10000000 // 28-bit bus 0x51000000 0x51000000 0x3000>; pcie@51000000 { reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>; reg-names = "config", "ti_conf", "rc_dbics"; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; }; }; Here the CPU address for configuration space is 0x20013000 and the controller address for configuration space is 0x13000. The controller address should be used while programming the ATU (in order for translation to happen properly in DRA7xx). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mohit Kumar <mohit.kumar@st.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit f4c55c5a3f7f68c06cc559ed7af8b2d017cbb0a7)
2015-04-14PCI: designware: Look for configuration space in 'reg', not 'ranges'Kishon Vijay Abraham I
The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 4dd964df36d0e548e1806ec2ec275b62d4dc46e8)
2015-04-14PCI: designware: Split Exynos and i.MX bindingsLucas Stach
The glue around the core designware IP is significantly different between the Exynos and i.MX implementation, which is reflected in the DT bindings. This changes the i.MX6 binding to reuse as much as possible from the common designware binding and removes old cruft. I removed the optional GPIOs with the following reasoning: - disable-gpio: endpoint specific GPIO, not currently wired up in any code. Should be handled by the PCI device driver, not the host controller driver. - wake-up-gpio: same as above. - power-on-gpio: No user in any upstream DT. This should be handled by a regulator which shouldn't be controlled by the host driver, but rather by the PCI device driver. [bhelgaas: whitespace fixes] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> (cherry picked from commit 1db823ee9f677e1a863cd04fda391a7520fcd0e8)
2015-04-14PCI: mvebu: Remove ARCH_KIRKWOOD dependencyAndrew Lunn
mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. ARCH_MVEBU is sufficient. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net> (cherry picked from commit c27602086d08d22b067a1267e09fb32b4b096aa0)
2015-04-14PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xxPratyush Anand
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip designware PCIe controller. To make that usable, this patch adds a wrapper driver based on existing designware driver. Adds bindings for this new driver and update MAINTAINERS as well. Cc: linux-pci@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> (cherry picked from commit 51b66a6ce12570e5ee1a249c811f7f2d74814a43) Conflicts: MAINTAINERS
2015-04-14PCI: generic: Add generic PCI host controller driverWill Deacon
Add support for a generic PCI host controller, such as a firmware-initialised device with static windows or an emulation by something such as kvmtool. The controller itself has no configuration registers and has its address spaces described entirely by the device-tree (using the bindings from ePAPR). Both CAM and ECAM are supported for Config Space accesses. Add corresponding documentation for the DT binding. [bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> (cherry picked from commit ce292991d88b77160f348fb8a3a2cf6e78f4b456) Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile
2015-04-14PCI: imx6: Add support for MSILucas Stach
This patch adds support for Message Signaled Interrupts in the imx6-pcie driver. Signed-off-by: Harro Haan <hrhaan@gmail.com> Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit d1dc9749a5b8239d9ae718a176b5cd39ff89f976)
2015-04-14PCI: designware: Make MSI ISR shared IRQ awareLucas Stach
On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make sure we don't bail too early from the IRQ handler. The issue is fairly theoretical as it would require a system setup with a PCIe switch where one connected device is using legacy INTD and another one using MSI, but better fix it now. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 7f4f16eef5aeba31bdfb7702ced06a42f2777e04)
2015-04-14PCI: imx6: Remove optional (and unused) IRQsLucas Stach
They are dropped with the new binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5c40eea7783bbcdd5795cd7d50b7b3fd9a94dc94)
2015-04-14PCI: imx6: Drop old IRQ mappingLucas Stach
We don't need this anymore. The IRQs are now properly mapped through the DT. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit e521519a84f6d796d3cff756969cd5902c9550dd)
2015-04-14PCI: imx6: Use new clock namesLucas Stach
As defined in the new binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 57526136532408bacf2f68c26027abc2924b45d1)
2015-04-14PCI: imx6: Fix imx6_add_pcie_port() section mismatch warningSachin Kamat
imx6_add_pcie_port() is called only from from imx6_pcie_probe() which is annotated with __init. Thus it makes sense to annotate imx6_add_pcie_port() with __init to avoid section mismatch warnings. [bhelgaas: changelog] Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Sean Cross <xobs@kosagi.com> (cherry picked from commit 44cb5e94f96cef72a977fc5fdea8095bc0ae25ba)
2015-04-14PCI: exynos: Fix add_pcie_port() section mismatch warningSachin Kamat
add_pcie_port() is called only from exynos_pcie_probe(), which is annotated with __init. Thus it makes sense to annotate add_pcie_port() with __init to avoid the following section mismatch warning: WARNING: drivers/pci/built-in.o(.text.unlikely+0xf8): Section mismatch in reference from the function add_pcie_port() to the function .init.text:dw_pcie_host_init() The function add_pcie_port() references the function __init dw_pcie_host_init(). This is often because add_pcie_port lacks a __init annotation or the annotation of dw_pcie_host_init is wrong. [bhelgaas: changelog] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> (cherry picked from commit 17d7acc8e1c81f8125730aa900c67412a2ac69e2)
2015-04-14PCI: rcar: Add Renesas R-Car PCIe driverPhil Edworthy
This PCIe Host driver currently does not support MSI, so cards fall back to INTx interrupts. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> (cherry picked from commit c25da4778803b41e11fd82dd5576c35c09b5f0e0)
2015-04-14PCI: exynos: Remove unnecessary OOM messagesJingoo Han
The site-specific OOM messages are unnecessary, because they duplicate the MM subsystem generic OOM message. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> (cherry picked from commit 755ba5e406e5ddd876e85a881dc50c7f54a8fd6b)
2015-04-14PCI: designware: Remove unnecessary use of 'conf_lock' spinlockAndrew Murray
Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 11c6fbd8d982617996fbc39097a84092eb6e8005)
2015-04-14PCI: designware: Use new OF interrupt mapping when possibleLucas Stach
Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible. This is the recommended method of doing the IRQ mapping. For old devicetrees we fall back to the previous practice. This makes INTB, INTC, and INTD work on i.MX. Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jingoo Han <jg1.han@samsung.com> (cherry picked from commit 804f57b1a63c7435fe43b36942581cc6c79ebb5c)
2015-04-14PCI: designware: Fix comment for setting number of lanesMohit Kumar
Corrects comment for setting number of lanes. Signed-off-by: Mohit Kumar <mohit.kumar@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> (cherry picked from commit 66c5c34bf80c28d370eb9bcf30153ea0304a288a)
2015-04-14pci: pcie-designware: Remove irq_desc abuseThomas Gleixner
There is no reason to care about irq_desc in that context, escpecially as irq_data for that interrupt is retrieved as well. Use the proper accessor for the msi descriptor Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: pci <linux-pci@vger.kernel.org> Link: http://lkml.kernel.org/r/20140223212736.987803648@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de> (cherry picked from commit f7bfca6db60a6ca0a73126918b2fb6f851065947)
2015-04-14PCI: rcar: Make the Kconfig dependencies more genericMagnus Damm
Update the R-Car Generation 2 PCI driver Kconfig dependencies to follow same style as other drivers - no SoC dependencies. Also, update the COMPILE_TEST bits to depend on ARM. This since the DMA bounce buffer and dma_ops handling code is ARM specific. [bhelgaas: adjust context after dropping DMABOUNCE patches] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> (cherry picked from commit ef4741e90c4e6523795f4375659b5097293d87db)
2015-04-14MLK-9996 arm: imx6: Correct the AHB clock in low_bus_freq_modeBai Ping
When the busfreq is in audio_bus_freq_mode, the AHB bus is at 8MHz, in low_bus_freq_mode, the AHB needs to run at 24MHz. So when switching from audio_bus_freq_mode to low_bus_freq_mode, make sure the AHB is at 24MHz in low_bus_freq_mode. Signed-off-by: Bai Ping <b51503@freescale.com>
2015-04-14ASoC: hdmi: HDMI codec doesn't benefit from pmdown delayJyri Sarha
Adds .ignore_pmdown_time = true to codec driver struct. HDMI codec is currently a dummy codec and doesn't benefit from pmdown delay. Even if in the future the codec would controll HDMI encoder, it would still be a digital to digital interface that should have no need for pmdown delay. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 69434097916bc52a4d6d495a0d719eb02e0cff9e)
2015-04-14ASoC: hdmi: Mark the maximum significant bits to HDMI codecJyri Sarha
HDMI audio can not have more than 24 bits even if on i2s bus there would be 32 bit samples. Mark this by adding .sig_bits = 24 to playback stream definition. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 74d813cf37c210e94d155b0c19598fe269b8f78c)
2015-04-14MLK-9989 arm: imx: imx_v7_mfg_defconfig: enable CONFIG_IMX_SEMA4 by defaultAnson Huang
enable CONFIG_IMX_SEMA4 by default for imx_v7_mfg_defconfig. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-10 arm: imx: add A9-M4 power managementAnson Huang
this patch adds A9-M4 power management, including below features: 1. busfreq: M4 is registered as a high speed device of A9, when M4 is running at high speed, busfreq will NOT enter low bus mode, when M4 is entering its low power idle, A9 will be able to enter low bus mode according to its state machine; 2. low power idle: only when M4 is in its low power idle, busfreq is staying at low bus mode, low power idle is available for kernel; 3. suspend: when M4 is NOT in its low power idle, when linux is about to suspend, it will only force SOC enter WAIT mode, only when M4 is in its low power idle in TCM, linux suspend can enter DSM mode. M4 can request/release wakeup source via MU to A9. as M4 can NOT switch its clk parent due to glitch MUX, to handle this case, A9 will help switch M4's clk parent, the flow is as below: M4: 1. enter low power idle, send bus use count-- to A9; 2. enter wfi and only wait for MU interrupt; 3. receive A9's clk switch ready message, go into low power idle; 4. receive interrupt to exit low power idle, send request to A9 for increase busfreq and M4 freq, enter wfi and only wait for MU interrupt; 5. receive A9 ready message, go out of low power idle. A9: 1. when receive M4's message of entering low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to OSC, ungate M4 clk, send ready command to wake up M4 into low power idle; 2. when receive M4's message of exiting low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to origin high clk, ungate M4 clk, send ready command to wake up M4 to exit low power idle; Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-9 arm: imx: add A9-M4 clk shared managementAnson Huang
As A9 and M4 share many resources on i.MX6SX, especially for clk and power related resource, so we need to handle the hardware conflict between these two cores, there are two cases that we need to consider currently: clk management: for every clk node, only when both A9 and M4 do NOT need it, then we can disable it from hardware; Here we use MU and hardware SEMA4 to achieve our goal, MU is for communiation between A9 and M4, SEMA4 is to protect the shared memory. For clk management, we use shared memory to maintain the clk status for both A9 and M4 side, and this shared memory is protected by hardware SEMA4, A9 and M4 will maintain their own clk tree info in their SW environment, and get other CORE's clk tree info from shared memory to decide whether to perform a hardware setting change when they plan to. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9872-3 arm: imx: adjust qspi device index according to dtb settingAnson Huang
When resume from DSM with Mega/Fast off, we need to restore the right QSPI module for M4, so get the qspi index from dtb file. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9674-3 arm: imx: add QSPI save/restore when M4 is enabledAllen Xu
As M4 is executing on QSPI2 flash, and QSPI is inside Mega/Fast domain which may lost power in DSM, so we need to do save/restore of QSPI2 controller to make sure QSPI flash can be accessed before waking up M4 after exiting from DSM. Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-8 arm: imx: add mu driver supportAnson Huang
add MU driver support in mach-imx, all the MU functions and communications between A9 and M4 will be done in this file, including MCC, shared clk/power management. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-7 arm: dts: imx6sx: add mu supportAnson Huang
add MU support for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-6 arm: dts: imx6sx: add m4 dts supportAnson Huang
1. add i.MX6SX SabreAuto board M4 dts support; 2. add shared memory node support for AMP clk/power management; 3. add qspi restore node for suspend/resume with Mega/Fast off when M4 is enabled and running on QSPI flash. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-5 arm: dts: imx6sx: add sema4 supportAnson Huang
add SEMA4 support for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-4 arm: imx: enable CONFIG_IMX_SEMA4 by defaultAnson Huang
enable CONFIG_IMX_SEMA4 by default. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-3 arm: imx: add HAVE_IMX_AMP for imx6sxAnson Huang
add HAVE_IMX_AMP and select by default for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-2 driver: char: sema4: rename sema4 driver diretoryAnson Huang
as sema4 is a common driver for amp system, not just for mcc, so rename sema4 diretory from imx_mcc to imx_amp. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9955-1 arm: imx: add necessary mcc header fileAnson Huang
add necessary mcc header file for mcc and sema4. Acked-by: Jason Liu Signed-off-by: Anson Huang <b20788@freescale.com>
2015-04-14MLK-9870 mcc: sema4: mutex lock should be initiazledRichard Zhu
mutex lock should be initialized, otherwise there maybe kernel BUG warning. "BUG: spinlock bad magic on CPU#0, swapper/0/1" Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com> (cherry picked from commit 5db690b478afea00ca226f200ddf892b691674dd)
2015-04-14MLK-9707-5 arm: mcc: mcc2.0 sema4 related changesRichard Zhu
imx sema4 driver changes in mcc2.0 updates Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
2015-04-14ENGR00308060-3 mcc: add sema4 driver required by mccRichard Zhu
- add linux sema4 driver, that mandatory required by mcc. - use volatile types in sema4 structure - align the port definiton a9 is 1, m4 is 2. Signed-off-by: Richard Zhu <r65037@freescale.com>
2015-04-14net: fec: only enable mdio interrupt before phy device link upNimrod Andy
Before phy device link up, we only enable FEC mdio interrupt, which is more reasonable. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-04-14net: fec: clear all interrupt events to support i.MX6SXNimrod Andy
For i.MX6SX FEC controller, there have interrupt mask and event field extension. To support all SOCs FEC, we clear all interrupt events during MAVC initial process. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-04-14net: fec: reset fep link status in suspend functionNimrod Andy
On some i.MX6 serial boards, phy power and refrence clock are supplied or controlled by SOC. When do suspend/resume test, the power and clock are disabled, so phy device link down. For current driver, fep->link is still up status, which cause extra operation like below code. To avoid the dumy operation, we set fep->link to down when phy device is real down. ... if (fep->link) { napi_disable(&fep->napi); netif_tx_lock_bh(ndev); fec_stop(ndev); netif_tx_unlock_bh(ndev); napi_enable(&fep->napi); fep->link = phy_dev->link; status_change = 1; } ... Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-04-14MLK-9969 dts: Enable subdev csi driver in imx6sx AI boardSandor Yu
Enable OV5640, VADC and CSI driver in imx6sx AI board Signed-off-by: Sandor Yu <R01008@freescale.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-19 20:18:25 +0000