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2020-04-23MGS-5565-1 staging: android: ion: Flush outer cache after zero CMA allocated ↵Richard Liu
memory Need flush outer cache after zero CMA allocated memory on arm32 platform. Change-Id: Ieaa7c62bf65e4490f904d68bed1fa16fb7c5d8fa Signed-off-by: Richard Liu <xuegang.liu@nxp.com> Reviewed-by: Bing Song <bing.song@nxp.com> (cherry picked from commit 9e51da339eb290f35eb79d9acc0ea147d8bdf0cf)
2020-04-23MGS-5565 staging: android: ion: Flush cache after zero CMA allocated memoryRichard Liu
ION CMA memory default is cacheable, need flush cache after memset(), else cache and physical memory not sync may cause problem. Issue case: VPU Video playback or GPU render have dirty line issue. Root cause: ION CMA allocate cacheable buffer and do memset(), some data still in cache not in physical memory, VPU or GPU write the buffer with physical address, or user call ion_mmap() to map the buffer through pgprot_writecombine() as no-cache and write the buffer, later some CPU cache access trigger cache flush, previous memset() data go to physical memory as dirty data. Change-Id: I82b4cb61bbe6cffc687d452f9f81c1e35914d2f1 Signed-off-by: Richard Liu <xuegang.liu@nxp.com> (cherry picked from commit 5d360f25f3523311b5f478b7b1c7bc9020cfda58)
2020-04-18LF-1236 mxc: vpu_malone: roundup allocated kfifo size to power-of-twoShijie Qin
kfifo memory size must roundup to power-of-two if it is allocated by driver. Because kfifo elements size will roundup to power-of-two in kfifo_init(), must guarantee allocated memory is enough. Signed-off-by: Shijie Qin <shijie.qin@nxp.com> Reviewed-by: ming_qian <ming.qian@nxp.com> (cherry picked from commit c900bb4cd98efc43dddfb18d96c8af358e804481)
2020-03-31MLK-21644 crypto: tcrypt - workaround for overlapping src, dst AADHoria Geantă
This is a temporary workround for the case when: -SWIOTLB is used for DMA bounce buffering AND -data to be DMA-ed is mapped DMA_FROM_DEVICE and device only partially overwrites the "original" data AND -it's expected that the "original" data that was not overwritten by the device to be untouched As discussed in upstream, the proper fix should be: -either an extension of the DMA API OR -a workaround in the device driver (considering these cases are rarely met in practice) Since both alternatives are not trivial (to say the least), add a workaround for the few cases matching the error conditions listed above. Link: https://lore.kernel.org/lkml/VI1PR0402MB348537CB86926B3E6D1DBE0A98070@VI1PR0402MB3485.eurprd04.prod.outlook.com/ Link: https://lore.kernel.org/lkml/20190522072018.10660-1-horia.geanta@nxp.com/ Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Valentin Ciocoi Radulescu <valentin.ciocoi@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2020-03-31LF-717: crypto: dcp - fix scatterlist linearization for hashRosioru Dragos
The incorrect traversal of the scatterlist, during the linearization phase lead to computing the hash value of the wrong input buffer. New implementation uses scatterwalk_map_and_copy() to address this issue. Fixes: 15b59e7c3733 ("crypto: mxs - Add Freescale MXS DCP driver") Signed-off-by: Rosioru Dragos <dragos.rosioru@nxp.com> Acked-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2020-03-26MLK-23681 arm64: dts: imx: enable pcieb on 8qm mek baseboardRichard Zhu
Based on imx_4.1x kernel, enable the PCIEB on i.MX8QM MEK baseboard. Regarding to the base board HW limitation(two Disable#) are not connected. Only the standard PCIe EP device is supported on PCIEB port. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit d0331d84e5a14d6e2520d04540d1e893d75bd678)
2020-03-24MLK-23220:mxc:vpu_malone:kfifo_alloc failure in VPU driver when memory fragmentMing Qian
Suggest to use vmalloc for fifo entity. Then use kfifo_init to init the fifo structure. Then we do not have to require contiguous memory from buddy, especially in a high pressure of memory resource. Signed-off-by: Ming Qian <ming.qian@nxp.com> (cherry picked from commit 0cd3c661b95ecb273da5ee76fe7353ab7abd38c9)
2020-03-06MLK-23396: crypto: caam - ensure CAAM context is not sharing the cachelineIuliana Prodan
In caam_hash_state struct, caam_ctx buffer needs to have a separate cacheline, not sharing it with "update" callback. On imx8, the cacheline size is 64 and the MAX_CTX_LEN, from caam_ctx buffer, is (8 + 64). Therefore, add a ____cacheline_aligned to the update callback, in caam_hash_state struct, to ensure that caam_ctx buffer is not sharing the cacheline. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
2020-02-25MLK-23233-5 PCI: imx: add the mandatory required peripheral clocksRichard Zhu
To avoid potential dump when access the HSIO CRR registers during PCIE initialization. Add the PHY_PER and MISC clocks for both PCI controllers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Enable the clocks before CRR registers manipulations. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23233-4 arm64: dts: refine pcie dts and add the pcieax2 and pciebx1 usecaseRichard Zhu
Different usecase maybe used by customer, add the PCIEA two lanes and PCIEB one lane usecase into fsl-imx8qm-pcieax2pciebx1.dts. Refine the PCIE dts nodes, add the requrired HSIO peripheral clocks for different consumers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23233-3 ata: imx: add the clks into sata driverRichard Zhu
To avoid potential dump when access the PHY and MISC CRR registers. Add the CRRS clocks into SATA driver. The codes are merged back from 4.19 to 4.14 refer to MLK-21695. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23233-2 dts: arm64: sata: add the clks into sata nodesRichard Zhu
To avoid potential dump when access the PHY and MISC CRR registers. Add the CRRS clocks into SATA node. The codes are merged back from 4.19 to 4.14 refer to MLK-21695. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23233-1 dt-bindings: ata: add the peripheral clocks for imx8qm sataRichard Zhu
Add the documentation for the peripheral clocks required by iMX8QM SATA to access the HSIO MIX regions. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23331 arm64: dts: imx8mn: Update settings according to latest datasheetAnson Huang
According to latest datasheet Rev.0.1, 03/2020, VDD_ARM does NOT have dependency on VDD_SOC, so below table in datasheet can be used directly for VDD_ARM: Clock Voltage 1.2GHz 0.85V 1.4GHz 0.95V 1.5GHz 1.0V For DDR4 EVK board, system runs at nominal mode, so GPU can ONLY run up to 400MHz. For LPDDR4 EVK board, system runs at over-drive mode, so GPU can run up to 600MHz. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit e619dfe015d96f9322b59f386e00167ec1aab321)
2020-02-24LF-838: crypto: caam - increase the domain of write memory barrier to full ↵Iuliana Prodan
system In caam_jr_enqueue, under heavy DDR load, smp_wmb() or dma_wmb() fail to make the input ring be updated before the CAAM starts reading it. So, CAAM will process, again, an old descriptor address and will put it in the output ring. This will make caam_jr_dequeue() to fail, since this old descriptor is not in the software ring. To fix this, use wmb() which works on the full system instead of inner/outer shareable domains. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> (cherry picked from commit e4978516eeacb083412753dbc523de7d9dca8463) It looks like this also fixes MLK-23259, so cherry-pick from LF linux-lts-nxp:lf-5.4.y into linux-imx:imx_4.14.y. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2020-02-17MLK-23326 arm64: dts: imx8mn-evk: Correct 1.2GHz OPP voltageAnson Huang
When running at OD mode, VDD_ARM can NOT be lower than VDD_SOC, overwrite the 1.2GHz OPP's voltage to be same as VDD_SOC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 77714128a1da83fbc516b41206574e2e62348dc8)
2020-02-11MLK-23292-2 arm64: dts: fsl-imx8dx-mek: Add JDI WUXGA LVDS panel supportLiu Ying
This patch adds JDI WUXGA LVDS panel support on the i.MX8DX MEK platform. The JDI WUXGA LVDS panel works in LDB split mode. fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts uses LDB1 channel0 as the channel to transmit odd pixels and LDB2 channel0 as the channel to transmit even pixels. fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts swaps the channels to transmit odd/even pixels. Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 31c6c62eff01b3288828f2e1b9ecf6ad9204b3c6)
2020-02-11MLK-23292-1 arm64: dts: fsl-imx8dx-mek: Add IT6263 LVDS2HDMI dual channel ↵Liu Ying
support This patch adds IT6263 LVDS to HDMI transmitter dual channel support. The transmitter works with LDB split mode. fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts uses LDB1 channel0 as the channel to transmit odd pixels and LDB2 channel0 as the channel to transmit even pixels. fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts swaps the channels to transmit odd/even pixels. Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 7cd2417af24b8f54d0b91f9b655211db79f63abb)
2020-02-11arch: arm64: dts: 8dx: Add dts file for dsi panel use-caseRobert Chiras
Create the fsl-imx8dx-mek-dsi-rm67191.dts in order to add support for the MIPI-DSI panel usecase with the Raydium RM67191 DSI panel. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-10MLK-23288 dts: arm64: imx8dx-mek: add tja1100 card support for enet2 portFugang Duan
Add tja1100 card support for enet2 port. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-10MLK-23286: arm64: dts: add ov5640 dts support for i.MX8DX MEKGuoniu.zhou
Add ov5640 dts support for i.MX8DX MEK board Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
2020-01-28MLK-23258-4 dts: SATA requires PCIE_A power domain to be ONRanjani Vaidyanathan
SATA driver write to regisers in the PCIE_A power domain and hence PCIE_A needs to be powered on even when ONLY SATA is enabled. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-23MLK-23258-3 dts: Fix PCIE suspend/resume issueRanjani Vaidyanathan
Fix the parent-child power domain dependency to handle different PCIE usecases. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-23MLK-23258-2 clk:imx8qxp Fix PCIE suspend/resume issueRanjani Vaidyanathan
Fix PCIE LPCG clock power domains. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-23MLK-23258-1 soc:imx8qm/imx8qxp Fix PCIE suspend/resume issueRanjani Vaidyanathan
The power domain driver should ensure all the child power domains are powered off before powering down the parent. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-22MGS-5489: arm64: dts: imx8dx: update GPU memory settingXianzhong
The 8DX MEK only has 1GB DDR, update GPU memory as below: - set GPU MMU mapping size to 1GB (0x80000000-0xC0000000) - set GPU reserve size to 128MB Signed-off-by: Xianzhong <xianzhong.li@nxp.com> (cherry picked from commit 30efecdc1cef0fcff82f5cebd9823c61fee17e74)
2020-01-22MLK-23263 mxc: vpu_malone: correct vpu decoder used bits of fuseShijie Qin
Malone decoder used bits of fuse are 14-15 bits Signed-off-by: Shijie Qin <shijie.qin@nxp.com> Reviewed-by: ming_qian <ming.qian@nxp.com> (cherry picked from commit 8d34c1d1ce31048316da88448f8eecbed885fc44)
2020-01-22MLK-23262-2 ARM64: dts: fsl-imx8dx-mek-rpmsg: delete gpio for type-c ss muxPeter Chen
There is no Type-C ss mux chip on imx8dx mek, so delete the related GPIOs. The rpmsg dts file fsl-imx8x-mek-rpmsg.dtsi includes another phandle typec_ptn5110 for rpmsg i2c, we need this change to delete it again. Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2020-01-22MLK-23262-1 ARM64: dts: fsl-imx8dx-mek: delete gpio for type-c ss muxPeter Chen
There is no Type-C ss mux chip on imx8dx mek, so delete the related GPIOs. Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2020-01-21MLK-23187-2 drm/imx: dpu: crtc: Disable DPRC repeat_en in ->atomic_disable()Liu Ying
In order to avoid garbage data left in RTRAM after disabling CRTC, the SoC designer suggests us to disable DPRC repeat_en after FrameGen FGEN is cleared and before ENSTS is cleared. Also, it is suggested that FGEN clearing should be done in the frame prior to DPRC repeat_en disablement. So, syncing to FrameGen frame counter moving is needed. The disablement procedure should be done as soon as possible, so we disable local irq and preemption during the procedure to ensure this. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit ac84ef51ed68ce0ff9e7a3b5f5878ce0f788bb31) (cherry picked from commit dd0dd77bf3231efb2979b0bbe86d5c99cc892d5f)
2020-01-21MLK-23187-1 gpu: imx: dpu: framegen: Increase timeout again when waiting for ↵Liu Ying
moving In the coming patch, we would wait for FrameGen counter moving in ->atomic_disable() to get synchronization before disabling DPRC repeat_en. It appears that waiting for 50ms for video mode 1920x1080@24Hz is not enough in this case and increasing timeout to 100ms looks ok. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 97ba7831a140f85666306606176004e3634b384c) (cherry picked from commit 0f3a9e7dd10cd152866e32e855e8b9c0f6846020)
2020-01-17MLK-23247: arm64: dts: Add DTS files for DSP play on imx8dx mekShengjiu Wang
This file is almost same as the fsl-imx8qxp-mek-dsp.dts Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-01-15MLK-23243-3 arm64: dts: Add DTS files for iMX8DX MEK boardYe Li
Add iMX8DX MEK DTS file and its rpmsg DTS file, both re-use the common MEK board DTS files. The 8DX MEK only has 1GB DDR, so decrease its CMA size to 320MB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9ab7b42c2c99dc0e2dd7fafa5cb4cebd792aceaf)
2020-01-15MLK-23243-2 arm64: dts: Add new DTS fsl-imx8x-mek for MEK common nodesYe Li
Abstract the MEK board DTS nodes to common files fsl-imx8x-mek.dtsi and fsl-imx8x-mek-rpmsg.dtsi. So that we can share the board nodes between 8QXP and 8DX MEK DTS Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e1a4c61d3c0f9593ec0d2292cc4d510bcb59a01f)
2020-01-15MLK-23243-1 arm64: dts: imx8dx: Fix GPU clock rateYe Li
According to iMX8DX spec, the GPU and shader frequecy are both 372Mhz Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 2dd79af22fd753434b4213b11b799053cb9ec358)
2019-12-23LF-580 dt-bindings: imx: correct i2c4/uart1 clocks IDFugang Duan
Current i2c4/uart1 clocks ID have conflict with pwm2/pwm3, correct them. Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2019-12-20LF-561: [8QM_MEK/8QXP_MEK]mxc:vpu_malone:reinit completion before sendming_qian
command we should reinit the completion before send command who may trigger the completion, otherwise it may be reinit after complete in certain timing, then led to timeout use private workqueue instead of public workqueue Signed-off-by: ming_qian <ming.qian@nxp.com> Acked-by: Shijie Qin <shijie.qin@nxp.com> (cherry picked from commit fc50fb22a8ee8ddf27885c63c49ea45b5b3ba9b3)
2019-12-20MLK-22360 soc: imx8qm/imx8qxp: Fix power state of parent power domainsRanjani Vaidyanathan
Handle the case when powering down a pd with no active slave domains. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> (cherry picked from commit c5403cfa210cd44ba7c427a519a957e24b86dfb7)
2019-12-20MLK-22360 soc: imx8qm/imx8qxp: Fix power state of parent power domainsRanjani Vaidyanathan
Fix power state of parent power domains that have no device associated with them. Current power domain driver does not work well in two cases: 1. A device is controlled by multiple power domains 2. Multiple devices are controlled by a single power domain that is dependent on another power domain(s). This patch attempts to fix these two issues. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> (cherry picked from commit eb6a45d743ff61c1a802145a226c203c5ede155f)
2019-12-19MLK-23135-2 media: platform: imx8: Implementation for HDMI RX HDCPOliver Brown
Adding support hooks for HDCP on HDMI RX port. Currently the HDCP is enabled by the SECO FW. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-19MLK-23135-1 mxc: hdp: Added HDMI RX HDCP APIOliver Brown
Adding support for HDMI RX HDCP 1.4 and 2.2 Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-19MLK-22671 hdmi rx: Correct HDMI RX TMDS and AVI Info frame detectionDamian Kos
Removed setting of EDID and SCDC after video mode change. Now CEC is kept enabled during the video mode change. Added stable TMDS clock detection. -Add TMDS change detection. -Allow TMDS measurement to off by +- 12 Khz (+- 1 timer tick) New Infoframe detection -Infoframe detection written from scratch. -Add infoframe type parameter to hdmi_infoframe_poll function. -Hdmi_infoframe_poll now accepts the InfoFrame type to wait for. Previously InfoFrame type was set only for Vendor Infoframe. -Fix a problem with the VIC mask used to parse the AV infoframe. Disabled disabling of PLL. -Disabling PLL was causing Xtensa crash, so it is disabled. Moved part of HDMI configuration to hdmirx_config. Asserting PHY reset at the beginning of hdmirx_config causes Xtensa crash, so it's disabled for now. Changed moment of entering standby mode -Standby mode is now entered after cable_plugin flag is set which will prevent tmdsmon thread accessing inactive registers causing FW to crash. Added check for cable connection in TMDS measurement function. Now, when the plug gets removed, driver does not perform any reads and writes to PHY registers. Added check if FW is alive and if it's not then driver dumps the debug registers to see what was the last value written to these registers by FW or if the FW is stuck in some infinite loop. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-19MLK-22670 hdmi rx: Update HDMI RX EDIDOliver Brown
Added HDMI Vendor specific descriptor to EDID. Corrected min/max frequency ranges. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-19drivers: seco_mu: Add support for signed messageSilvano di Ninno
Adding support for the signed message API. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Stéphane Dion <stephane.dion_1@nxp.com> (cherry picked from commit bdb4cc7b429bd678255eb3b15f1683a9d916a21a)
2019-12-18MLK-23099 drm: imx: hdp: imx8QM: Handle case when firmware is already loadedOliver Brown
If the firmware is already running, then the driver should not restart or set the clock. This case may occur if the SECO FW is used to load the HDCP keys in u-boot. If the SECO FW loads the keys the HDMI firmware is started before Linux starts. The lifecycle of the HDMI FW must be preserved to keep the HDCP keys intact. If the HDMI FW is restarted, then the HDCP keys would need to be reloaded by the SECO FW. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-18MLK-23098 mxc: hdp: Correct message size in ↵Oliver Brown
CDN_API_HDCP_TX_IS_RECEIVER_ID_VALID_REQ The call to internal_readmsg used the incorrect a message size. Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-17MLK-22756 drm: imx: hdp: EDID read needs to re-enabled on plug outOliver Brown
The no_edid flag must be set back to false after a plugout event so the EDID read can be enabled for the nex plugin event Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2019-12-17MLK-23116-16 drm/imx: dpu: plane: Add some non-native prefetch pfmts support ↵Liu Ying
for i.MX8QXP C0 SoC i.MX8QXP C0 SoC contains SoC design fix for ERR050060, which opens non-native prefetch pixel formats for driver to use. With the previous patches in this serie, it should be save to add some such kind of pixel formats(RG24, BG24, NV16 and NV61) to the DPU plane. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 3e2797be911261dc7f7683f14904999d42b777c9) (cherry picked from commit 78ef3b1b97670e1b007eb22c0dcfacf451894983)
2019-12-17MLK-23116-15 gpu: imx: imx8_dprc/prg: Don't do reset for display instances ↵Liu Ying
in dprc/prg_configure() With proper disablement procedure implemented, we don't need to do DPRC and PRG reset for display instances in dprc/prg_configure(). Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 8053691995129310b57a68517724dd0c7be1bb71) (cherry picked from commit 2166e3f7f1bbc051645c905a051d83f620f7a884)
2019-12-17MLK-23116-14 drm/imx: dpu: plane: Remove uv_prefetch_start flagLiu Ying
The calling to helpers dprc_gasket_shadow_enable/disable() has already controlled the primary(Y plane) and auxiliary(UV plane) PRGs for their important SHADOW_EN bits. Also, it turns out we don't need to wait FrameGen frame counter moving when only the auxiliary PRG starts to function. So, we may remove the uv_prefetch_start flag. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit c439d72ab7b1491a0576da0f6dd8eaf315858395) (cherry picked from commit 330356c943f85708c880110e81004f60375695be)
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