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2019-02-12MLK-17634-9: clk: imx8m: add VIDEO2_PLL2 clock treeLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-8: drm: imx: dcss: read HDR10 LUTs/CSCs from FW fileLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-7: drm: imx: dcss: remove unused dcss_hdr10_priv structure memberLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-6: drm: imx: dcss: add P010 drm formatLaurentiu Palcu
This is 10-bit per channel YUV420 semi-planar. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-5: drm: imx: dcss: overlay planes support HDRLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-4: drm: move hdr_panel_metadata to drm_hdmi_infoLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-3: drm: edid: fix hdr infoframe creation routineLaurentiu Palcu
The frame->type was overwritten, instead of setting the frame->metadata_type field. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17634-2: drm: edid: add support for HLG EOTFLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12drm: Enable HDR infoframe supportUma Shankar
Enable Dynamic Range and Mastering Infoframe for HDR content, which is defined in CEA 861.3 spec. The metadata will be computed based on blending policy in userspace compositors and passed as a connector property blob to driver. The same will be sent as infoframe to panel which support HDR. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Parse Colorimetry data block from EDIDUma Shankar
EA 861.3 spec adds colorimetry data block for HDMI. Parsing the block to get the colorimetry data from panel. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Implement HDR source metadata set and get property handlingUma Shankar
HDR source metadata set and get property implemented in this patch. The blob data is received from userspace and saved in connector state, the same is returned as blob in get property call to userspace. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Add HDR capabilty field to plane structureUma Shankar
Hardware may have HDR capability on certain plane engines. Enabling the same in drm plane structure so that this can be communicated to user space. Each drm driver should set this flag to true for planes which support HDR. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Parse HDR metadata info from EDIDUma Shankar
HDR metadata block is introduced in CEA-861.3 spec. Parsing the same to get the panel's HDR metadata. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Add CEA extended tag blocks and HDR bitfield macrosUma Shankar
Add bit field and macro for extended tag in CEA block. Also, declare macros for HDR metadata block. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12drm: Add HDR source metadata propertyUma Shankar
This patch adds a blob property to get HDR metadata information from userspace. This will be send as part of AVI Infoframe to panel. Signed-off-by: Uma Shankar <uma.shankar@intel.com>
2019-02-12MLK-17634-1: drm: imx: dcss: send vblank event from ISRLaurentiu Palcu
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-15071: ASoC: fsl: imx-ak5558: Fix clk for 384KHz and 786KHzDaniel Baluta
With the current multipliers SAI isn't able to derive a correct bitclk. e.g: When recording at 786Khz with current multiplier MCLK = 24576000, requested freq 24576000 but SAI wants: MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution is to add a 2x factor to mclk. Reviewed-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17626 Use DEFINE_SPINLOCK for imx_ccm_lockAdriana Reus
If spinlock debug is enabled there are BUG_ON asserts in place for default values on the spinlock_t members. DEFINE_SPINLOCK declares and initializes the spinlock and avoids triggering those. Signed-off-by: Adriana Reus <adriana.reus@nxp.com> Tested-by: Marius Vlad <marius-cristian.vlad@nxp.com> Acked-By: Marius Vlad <marius-cristian.vlad@nxp.com>
2019-02-12MLK-17620-2: ASoC: imx-cdnhdmi: switch to generic hdmi codecShengjiu Wang
switch to generic hdmi codec, which provide the api for get the edid information. Add snd controls which is the interface for user to query the HDMI capibility. ( channels, rates, formats) Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-17620-1: hdp: register generic hdmi codec driverShengjiu Wang
Register generic hdmi codec driver, and move audio related code to an independent file. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
2019-02-12drm: Check for lessee in DROP_MASTER ioctlKeith Packard
Don't let a lessee control what the current DRM master is set to; that's the job of the "real" master. Otherwise, the lessee would disable all access to master operations for the owner and all lessees under it. This matches the same check made in the SET_MASTER ioctl. Signed-off-by: Keith Packard <keithp@keithp.com> Fixes: 2ed077e467ee ("drm: Add drm_object lease infrastructure [v5]") Cc: <stable@vger.kernel.org> # v4.15+ Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180119015159.1606-1-keithp@keithp.com Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> (cherry-picked 761e05a702f5d537ffcc from git://people.freedesktop.org/~airlied/linux)
2019-02-12drm: move lease init after validation in drm_lease_createKeith Packard
Patch bd36d3bab2e3d08f80766c86487090dbceed4651 fixed a deadlock in the failure path of drm_lease_create. This made the partially initialized lease object visible for a short window of time. To avoid having the lessee state appear transiently, I've rearranged the code so that the lessor fields are not filled in until the parameters are all validated and the function will succeed. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20171221065424.1304-1-keithp@keithp.com Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> (cherry-picked d2a48e52541cdf4 from git://people.freedesktop.org/~airlied/linux)
2019-02-12MLK-17459-4: drm: imx: dcss: fix westonLaurentiu Palcu
This patch fixes an issue introduced by the cropping patches which made weston look bad. That's because use_dtrc flag was enabled if modifiers were present. However, graphics plane can have modifiers too. This patch adds an extra check. Also, remove an unnecessary debug message. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17323 usb: cdns3: fix the kernel dump during the reboot stress testPeter Chen
During the reboot stress test, there may "nobody cared irq" for CDNS3, the interrupts are occurred during the controller is entering low power mode. In fact, we do no expect interrupt during this period, so disable controller interrupt for it. With this patch, the kernel dump does not occur again during reboot stress test. [ 18.460516] irq 44: nobody cared (try booting with the "irqpoll" option) [ 18.467222] CPU: 0 PID: 112 Comm: kworker/0:1 Not tainted 4.9.51-04150-ge84b58d-dirty #1198 [ 18.475573] Hardware name: Freescale i.MX8QXP MEK (DT) [ 18.480720] Workqueue: pm pm_runtime_work [ 18.484739] Call trace: [ 18.487186] [<ffff0000080884e0>] dump_backtrace+0x0/0x1e0 [ 18.492588] [<ffff0000080886d4>] show_stack+0x14/0x20 [ 18.497644] [<ffff0000083e571c>] dump_stack+0x94/0xb8 [ 18.502701] [<ffff0000081062c0>] __report_bad_irq+0x38/0xe8 [ 18.508276] [<ffff000008106644>] note_interrupt+0x20c/0x2e0 [ 18.513853] [<ffff00000810386c>] handle_irq_event_percpu+0x44/0x58 [ 18.520038] [<ffff0000081038c8>] handle_irq_event+0x48/0x78 [ 18.525608] [<ffff000008107260>] handle_fasteoi_irq+0xb8/0x1b0 [ 18.531445] [<ffff000008102894>] generic_handle_irq+0x24/0x38 [ 18.537187] [<ffff000008102f04>] __handle_domain_irq+0x5c/0xb8 [ 18.543017] [<ffff00000808163c>] gic_handle_irq+0xbc/0x168 [ 18.548506] Exception stack(0xffff80083ff4ae00 to 0xffff80083ff4af30) [ 18.554946] ae00: ffff80083ff4ae30 0001000000000000 ffff80083ff4af60 ffff0000080c1fec [ 18.562781] ae20: 0000000040000145 ffff80083a474000 0000000000000000 0000000000000000 [ 18.570617] ae40: 00000000fffeecc3 ffff000008a2d368 00000000020c49ba 0000000000000020 [ 18.578454] ae60: 000000000f78257c 7fffffffffffffff 0000000000000020 ffff80083a403f00 [ 18.586290] ae80: ffff80083ff51ab0 ffff000008cb0b68 00000000000003ef 0000000000000000 [ 18.594125] aea0: 0000000000000011 00000000000003ef 0000000000000019 0000000000000001 [ 18.601962] aec0: 0000000000000007 ffff0000092f9000 ffff0000092f5b08 0000000000000000 [ 18.609798] aee0: ffff000009501180 ffff80083a002a80 ffff80083a474000 00000000fffeecc2 [ 18.617634] af00: ffff80083ff4b090 ffff000009336000 0000000000000002 ffff80083ff4af60 [ 18.625469] af20: ffff0000080c243c ffff80083ff4af60 [ 18.630343] [<ffff0000080827b0>] el1_irq+0xb0/0x124 [ 18.635220] [<ffff0000080c243c>] irq_exit+0xac/0xf0 [ 18.640099] [<ffff000008102f08>] __handle_domain_irq+0x60/0xb8 [ 18.645928] [<ffff00000808163c>] gic_handle_irq+0xbc/0x168 [ 18.651409] Exception stack(0xffff80083a477ad0 to 0xffff80083a477c00) Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17380-7 usb: cdns3: add platform TPL supportPeter Chen
The TPL support is used to identify targeted devices during EH2.0 and EH3.0 certification test. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17380-6 ARM64: defconfig: enable configurations for USB certificationPeter Chen
These two configurations are needed for USB EH certification test. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17380-4 usb: host: xhci: add EH SINGLE_STEP_SET_FEATURE Test for USB2Peter Chen
This function is similar with EHCI's, but implemented using XHCI. The USB2 host needs to send SETUP packet first, then wait 15 seconds before DATA (IN) + STATUS stage. It is needed at USB Certification test for Embedded Host 2.0, and the detail is at CH6.4.1.1 of On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17380-3 usb: move EH SINGLE_STEP_SET_FEATURE implement to corePeter Chen
Since other USB 2.0 host may need it, like USB2 for XHCI. We move this design to HCD core. Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17380-2 usb: host: ehci: always enable interrupt for qtd completion at ↵Peter Chen
test mode At former code, the SETUP stage does not enable interrupt for qtd completion, it relies on IAA watchdog to complete interrupt, then the transcation would be considered timeout if the flag need_io_watchdog is cleared by platform code. In this commit, we always add enable interrupt for qtd completion, then the qtd completion can be notified by hardware interrupt. Acked-by: Jun Li <jun.li@nxp.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2019-02-12MLK-17459-3: drm: imx: dcss: fixes for compressed format croppingLaurentiu Palcu
Cropping of compressed formats seems problematic and we cannot up-align in this case. For compressed formats we need to down-align both the width and height. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17459-2: drm: imx: dcss: add cropping functionality and fix odd resolutionsLaurentiu Palcu
This patch fixes playback for movies with unaligned widths/heights and adds cropping functionality for tiled formats. Untiled formats will not have this feature as cropping is a DTRC function. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17459-1: drm: imx: dcss: change ctxld irq handlingLaurentiu Palcu
To remove any possible latencies introduced by scheduling the bottom half interrupt handler, do everything in the top half handler and get rid of the IRQ worker thread handler. Also, that needs all mutexes changed to spinlocks since mutexes can sleep. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2019-02-12MLK-17600: ASoC: imx-ak5558: Set MCLK as a function of fsDaniel Baluta
MCLK frequency is determined based on LRCK frequency, according to the operation mode. Because AK5558 runs in Auto Mode, we use table 5 from datasheet to set the correct MCLK. Multiplier must be set twice as value shown in RM because SAI MCLK must be at least double the BCLK. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Cosmin Samoila <cosmin.samoila@nxp.com>
2019-02-12MLK-17597-1: i.MX8MQ workaround affecting other SoCsNitin Garg
Fix iMX8MQ workaround to be specific to that machine. Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2019-02-12MLK-17561-4 ASoC:vpu: Update to the latest SCFW API based on commit 97b8a6eeRanjani Vaidyanathan
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Feb 6 08:54:16 2018 -0600 Add unique ID API call. Required to get info needed for SECO fuse programming. Added info command to DM. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-17561-3 clk:imx8: Update to the latest SCFW API based on commit 97b8a6eeRanjani Vaidyanathan
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Feb 6 08:54:16 2018 -0600 Add unique ID API call. Required to get info needed for SECO fuse programming. Added info command to DM. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-17561-2 ARM64:dts: Update to the latest SCFW API based on commit 97b8a6eeRanjani Vaidyanathan
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Feb 6 08:54:16 2018 -0600 Add unique ID API call. Required to get info needed for SECO fuse programming. Added info command to DM. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2019-02-12MLK-17597: Add GICC, GICH, GICV addresses to iMX8QM device tree.Nitin Garg
Adding GICC, GICH, GICV addresses for iMX8QM Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2019-02-12MLK-17590-02 driver: soc: imx: update the busfreq flow on imx8mqBai Ping
Currently, on imx8mq evk board, we only support 3200mts and 667mts frequency setpoints. So the DDR DVFS flow need to be updated accordingly. The dram pll and dram apb clock rate is changed in ATF when doing frequency, in kernel side, we need to call the clk API to update the clock rate info in clock tree. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-17590-01 driver: clk: imx: update the clk flag of pllBai Ping
Add CLK_GET_RATE_NOCACHE and CLK_SET_RATE_GATE for sscg pll. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-17509: ASoC: imx-ak4458: Set MCLK freq as a function of FSCosmin-Gabriel Samoila
According to AK4458 RM the MCLK freq need to be set externaly as function of LRCK frequency. Notice that multiplier is twice the value shown in RM since SAI MCLK must be at least double the BCLK. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-02-12MLK-17570: Add i.MX8QP supportTeo Hall
Add Kconfig and DTS support for i.MX8QP with a simplified structure Signed-off-by: Teo Hall <teo.hall@nxp.com> Squashed into a single commit during 4.14 rebase. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-17552-2 PCI: imx: enable imx pcie ep dmaRichard Zhu
Enable the imx pcie ep dma in the pcie ep rc validation system. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-17552-1 arm: dts: add the dma int for imx pcie epRichard Zhu
Add the dma int for the the imx pcie ep mode for the controllers that has the dma capability. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12MLK-17528-4: ASoC: imx-ak4497: set MCLK freq as function of FSViorel Suman
According to AK4497 RM the MCLK freq need to be set externaly as function of LRCK frequency. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17528-3: ASoC: fsl_sai: Set clock rate in "set_sysclk" APIViorel Suman
Set the requested clock rate in "set_sysclk" for specified clock id. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17528-2: ASoC: imx_pdm: Use FSL_SAI_CLK_BIT to signal the proper clock idViorel Suman
The current implementation suggest that MAST1 frequency is to be changed, which is wrong. Use FSL_SAI_CLK_BIT clock id instead of FSL_SAI_CLK_MAST1 in order to make the code more intuitive and to signal proper clk_id to SAI. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17528-1: ASoC: fsl_sai: Introduce FSL_SAI_CLK_BIT clock idViorel Suman
Introduce FSL_SAI_CLK_BIT clock id in order to distinguish the bit clock and master clocks in "set_sysclk" API. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
2019-02-12MLK-17574 gpu: imx: dpu: Fix typos for scaler_scale_mode_tLiu Ying
Fix some typos for enum entry names of scaler_scale_mode_t. Signed-off-by: Liu Ying <victor.liu@nxp.com>
2019-02-12MLK-17555 ARM64: defconfig: add usb video supportLi Jun
Add usb video support by build it as module. Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
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