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This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
[shawn.guo: cherry-pick commit 27e3604c82cb from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
drivers/reset/Makefile
(cherry picked from commit 2c8ba990ad6b33bd28f72384fbd238e0aca6c886)
Conflicts:
drivers/reset/Kconfig
drivers/reset/Makefile
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Enable low power idle for i.MX6SX:
WFI -> first level idle;
WAIT mode -> second level idle;
Low power idle -> third level idle, only when system is in low bus mode.
In low powe idle mode, below operations will be done:
ARM power off;
AHB freq lower to 3MHz;
PERCLK freq lower to 6MHz;
MMDC freq lower to 1MHz;
Anatop will be put into low power mode, and regular band-gap will
be off and low power band-gap will be enabled instead.
Also, in low power idle mode, 24MHz XTAL power will be off and 24MHz clk
source will be switched to RC-OSC to save power, this feature is only
enabled on i.MX6SX TO1.2.
This patch is cherry-picked from L3.14.y, it is the latest version, below
conflicts are fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Conflicts:
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/common.h
arch/arm/mach-imx/cpuidle-imx6sx.c
arch/arm/mach-imx/cpuidle.h
arch/arm/mach-imx/mach-imx6sx.c
arch/arm/mach-imx/pm-imx6.c
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This patch adds suspend/resume with Mega/Fast mix off support
for i.MX6SX LPDDR2, tested on i.MX6SX-14x14-LPDDR2-ARM2 board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add i.MX6SX-14x14-LPDDR2-ARM2 board support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch adds busfreq support for i.MX6SX LPDDR2, tested
on i.MX6SX 19x19 LPDDR2 ARM2 board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add busfreq support for i.MX6SX DDR3 board, tested on
i.MX6SX SDB board, busfreq support below 3 setpoints:
high -> 400MHz
audio -> 50MHz
low -> 24MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
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For some bus mux, need to remove CLK_SET_PARENT_GATE
flag as they can NOT be disabled, and they are only
used by bus-freq and the asm code already follow the
correct sequence of changing parent, so we can remove
CLK_SET_PARENT_GATE flag to avoid set parent fail
after bus-freq transition done.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add busfreq support for i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add i.MX6SX-19x19-ARM2 board support.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Update i.MX6SX pinfunc header, add uart mux function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch is to keep usb controller power on while system suspend if there
is usb device connected by telling GPC to keep mega fast domain power.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 74d1524208bfa052f9adac28c8f7d8fb8ed78499)
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Add an interface for GPC used by drivers to keep mega fast mix domain
power.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit f40b0d57803b26a889d12cb70f128801ef75055a)
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Merged from 49108fcf7b79ed77d34be33b53a3964b2ac27204
1. Watermark level in sdma use byte as its unit. but asrc driver use
word, there is mismatch between them. Here fix this issue and sdma can
work more efficiency.
2. Enlarge the larst_period_size, when use small size, for some case,
the dma task will timeout, because sdma has no much data for output.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 8a96e09e265294f396bd3af29b429e4b7bdff461)
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merge 7e1a620a030d17f93fdd97d076f1cdd042e79337
The reason of crach is that some variables are not protected in
function mxc_asrc_suspend(), when suspend, there is possibility to
access one NULL pointer.
Refine the spin lock usage, add protecting for pair_hold.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit e90c73f8170bc929cff54b0478da0573e4e26c23)
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Merge from c086d0151ee3e131b52bef96c5096d1ee603c852
Return value -ERESTARTSYS is not visible for user space according
to include/linux/errno.h. So use -EBUSY replace it.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 69d529646a610d8d1360bd116ceec1341aef4211)
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cherry-pick below patch from v3.14.y:
ENGR00330403-4: ASoC: fsl_asrc: Add Memory to Memory support
ASRC M2M function is not able to put upstream due to its self-designed
ioctl protocol. So I just make a single patch for it and make it merge
into P2P driver as simply as possible.
The patch can only be maintained internally unless some one designs a
new protocol or implement the originally protocol by using some common
approach provided by Linux Kernel.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit b5a7a98da076b0202334db01ecc3833342a7ca11)
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On i.MX6QP, the soc_id exported to the /sys/devices/soc0/soc_id
should be 'i.MX6QP'.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 5b478870b0b936a6c89574e6fe62f5537e31ecf0)
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Enable the M/F funtion support on i.MX6SX. The M4 M/F off
support is not added at present, will be enabled after the M4
funtion is ready.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add 'fsl,mf-mix-wakeup-irq' property used for M/F mix in gpc node
on i.MX6SX.
Signed-off-by: Bai Ping <b51503@freescale.com>
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After the system resume back from suspend, the M/F mix domain
power down bit should be cleared to make sure this domain's power
is on in other low power mode.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add MSL code for i.MX6QP.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add dtsi and dts file for i.MX6QP
Signed-off-by: Bai Ping <b51503@freescale.com>
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fix sdma driver resume back failed if SDMA clock disabled before suspend:
PM: noirq resume of devices complete after 0.802 msecs
imx-sdma 30bd0000.sdma: Timeout waiting for CH0 ready
imx-sdma 30bd0000.sdma: loaded firmware 4.1
imx-sdma 30bd0000.sdma: restore context error!
dpm_run_callback(): sdma_resume+0x0/0x1c8 returns -110
PM: Device 30bd0000.sdma failed to resume early: error -110
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add enet dts file to makefile.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add GPMI NAND support for i.MX6UL 14x14 ddr3 arm2 board.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add gpmi nand support on i.MX7D sdb board.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- Add iomuxc lpsr pad settings, move pinctrl_usbotg1_vbus and
pinctrl_usbotg2_vbus to iomuxc lpsr domain.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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- Add additional pad settiongs for iomuxc_lspr controller
- Move pinctrl_pwm1 to iomuxc_lspr domain
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Because load context code has been removed in prepare DMA transfer everytime.
Need restore them back once mega/fast powered off.
Signed-off-by: Robin Gong <b38343@freescale.com>
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enable dmatest module by default.
Signed-off-by: Robin Gong <b38343@freescale.com>
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dmatest is a common dma test module for dma driver which support mem_2_mem copy
.Since SDMA driver has the mem_2_mem interface, make little code change to
support this feature rather than our internal mxc_sdma_memcopy_test test
module.
Signed-off-by: Robin Gong <b38343@freescale.com>
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i.MX6SX CPUIdle with ARM core power down has issue
and cause system hang during kernel boot up, disable
it for now and will enable it when busfreq driver
is ready.
Signed-off-by: Anson Huang <b20788@freescale.com>
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i.MX6SX has same design as i.MX6SL which has bypass
pmic ready signal, as we do NOT enable this function,
so need to bypass it during suspend/resume.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The LPSR turns off the power for IOMUX when suspending so restore the
IOMUX when resuming in GPMI NAND driver.
The function was not tested yet since NAND only supported on 19x19
LPDDR board.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: b0375f42a27044667082e53449e534b265d7a029)
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Because of the delay of auto suspend, the nand clocks are delayed to
disable when calling the clk_set_rate. This causes the clk_set_rate
failed on some platforms like 6q/6qp, and finally lead the NAND not
working.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 1334dd236d4401d6635accb6c8472d8a5ed088b5)
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support runtime PM on gpmi nand to save the cost to enable/disable clock
in each NAND IO. The driver also claim high-freq bus when resumed.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 5b72b3388d1399420f3b49a0ca937ca5792e2d7d)
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The per1_bch was moved in patch below since it was never mentioned in
any GPMI/BCH/APBH documents, but actually it is necessary for BCH module
since BCH use AXI bus transfer data through fabric, need to enable this
clock for BCH at fabric side.
This patch enabled this clock for all i.MX6 platforms and has been
tested on i.MX6Q/i.MX6QP/i.MX6SX and i.MX6UL.
commit 9aa0fb0a606a583e2b6e19892ac2cab1b0e726c4
Author: Han Xu <b45815@freescale.com>
Date: Thu May 28 16:49:18 2015 -0500
mtd: nand: support NAND on i.MX6UL
support i.MX6UL GPMI NAND driver and removed the unecessary clock
per1_bch.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 53c5964a104f71c061d95bd98599fbf050644ddb)
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support i.MX6UL GPMI NAND driver and removed the unecessary clock
per1_bch.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 9aa0fb0a606a583e2b6e19892ac2cab1b0e726c4)
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change the maximum chips for i.MX7D, this part was missed when adding
i.MX7D NAND support.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 313d4d5e701dd6a28dc7d2bd84094b8fbdb7f9ca)
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when the maximum ecc NAND oob can afford exceed the ecc strength
controller can provide, use the maximum ecc strength controller can
support instead of the minimum ecc NAND spec required.
kobs-ng will also use the same ecc strength to align with kernel to make
sure all NAND chips can boot.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 958a2c5b07524f3502cfdefe66724a9a1f8ad608)
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i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 4302ab74a301626e7e0b9cb398a23b2e488cfa6b)
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Support NAND on i.MX7D
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked and merged from commit: 39af0df85dcbcb2ebd677ec5d2a2a4e6a61ed826)
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Add M/F mix support on i.MX6UL.
Signed-off-by: Bai Ping <b51503@freescale.com>
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fix the typo of code indent.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add pll1, pll1_bypass and pll1_bypass_src clock
reference define in dts file.
Signed-off-by: Bai Ping <b51503@freescale.com>
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This patch adds pll1, pll_bypass and pll1_bypass_src that
will be used in ARM clock switching code.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Replace the clk_get and regulator_get will the devm ones to free the
resources automatically when probe failed or driver is removed.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Currently, the dma engine driver don't support runtime pm,
and it is not necessary to support the feature since it support
slave sg and cyclic mode, and clock enable/disable during dma
chans allocate and release.
The patch remove the runtime pm dummy code.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 2c8f8e3e6a21184e6cf8b8e5ba3ec8e76794c951)
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After dma init by calling .mxs_dma_init(), disable dma_io and
dma_bch clocks. When dma chans are requested by devices, clocks
are enabled in .device_alloc_chan_resources(). The patch is to
fix clock enable count mismatch issue.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 4868cf5e39a0aeb1ad12c5c1a453d233c0f472ce)
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* iMX7D dma-apbh support add additional clock dependency
* Add clock for mxs-dma support dma_apbh_bch dma_apbh_io
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: aea75669daac9101592de2cfbadc7aaacbc7d887)
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