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Support ASRC P2P with ESAI to show the multichannel capibility.
And make this setting align with other platform like imx6
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
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interlaced flag
Add the event VID_API_EVENT_FIRMWARE_XCPT and modify interlaced flag for
vpu decoder
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
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Enable CWT for ATR, and switch to RX_DATA_IM to detect receiving data
in fifo.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
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Camera sensor need to be enabled before ISI when
resolution of caputure image is less than 640*480,
but hdmi need to be enabled after ISI, so add this
patch to compatible these two cases
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit c8d17ffcb0ab007d0be228b2cc4562b9cbc07501)
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Add NV12 output format support. Because nv12 is multi
planes format, so driver need add device for every planes
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
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fix encoder multi-instance bug
modify wait to wait_timeout
complete encoder suspend and resume
Signed-off-by: GuoRui <rui.guo_4@nxp.com>
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Before the kernel starts, optee uses M4 SRAM to allocate its
suspend function. When imx7ulp_pm_map_io() executes, the psci
driver and psci_ops.cpu_suspend are not initialized yet. This
causes the memset to always wipe the optee suspend code in the
M4 SRAM.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
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gpu tiling is not enabled in vg3d, need bypass dprc/prg process,
dprc stuck since no pipeline sync when switch linear to tile.
add force sync for command sequence pipeline when switch to tile,
remove the frequent dprc config for the contigous linear blit.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
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The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clock and assigned-clock-parent
device tree properties from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clocks and assigned-clock-parents
device tree properties from the dpu device tree nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds bypass clocks and disp_sel clocks in the dpu nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Add IMX_MICFIL in arm64 defconfig.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add machine driver for micfill IP in iMX8MM.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add micfil cpu-dai for iMX8MM.
The MICFIL digital interface provides a 16-bit audio
signal from a PDM microphone bitstream in a configurable
output sampling rate.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add micfil DAI node in dtsi and pdm sound card in dts.
We also moved ak5558 nodes into separate dts since
ak5558 uses sai5 which share some pins with micfil.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add documentation for micfil IP.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add iMX8MM PDM pins header.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Add support for interlaced and 10bit in v4l2 driver for vpu decoder
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
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Add ocotp node to make nvmem work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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There is ak4497 audio card even no audio board connected, which
os caused by there is no error return value even the i2c access
failed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Add new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script.
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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After the WAIT mode is enabled on imx8mm, the previous latency setting
seems can NOT meet the system the latency requirement. audio playback is
impacted by cpuidle. So increasing the latency setting as large as possible
to eliminate the impact of system performance. The latency value is not very
accurate, need to be updated after we have enough performance test result.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Optimize the pciea disable pin to drive NTB0104 device:
(NTB0104 requires at least 2 mA per data sheet)
- push-pull output
- pull disabled
- high drive strength
And the patch also change the lvds gpio to lsio gpio.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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simplify the current design about EOS handling:
- add_eos() is called only in V4L2_DEC_CMD_STOP, and no any block for
application
- stream_feed_complete: removed
- firmware_finished: simplified and reserved only for debug
- eos_stop_added: simplified and reserved only for debug
avoid abort hang(h264/hevc) in corner case
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
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Change pixel clock register of qxp PI ss in order to
accommodate scfw change for PI ss
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 1a769a426f4dcbd145280b3ff613607fbf6bcaa4)
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A9, A12 and A17
** Not yet queued for inclusion in mainline **
In order to prevent aliasing attacks on the branch predictor,
invalidate the BTB on CPUs that are known to be affected when taking
a prefetch abort on a address that is outside of a user task limit.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
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** Not yet queued for inclusion in mainline **
In order to avoid aliasing attacks against the branch predictor,
some implementations require to invalidate the BTB when switching
from one user context to another.
For this, we reuse the existing implementation for Cortex-A8, and
apply it to A9, A12 and A17.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
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For linear and tiled mixed blit, wait the dprc idle
before disable it in linear blit.
Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
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pcie aux clock is mandatory required by pcie power management.
add the aux clock into imx8mm pcie dts node explicitly.
pcie ctrl clock would be turned on, when pcie root clock
is enabled.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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enable spdif1 tx for hdmi rx arc
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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turn on aux_ana for rx arc
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Enable FlexSPI driver on i.MX8MM EVK.
Signed-off-by: Han Xu <han.xu@nxp.com>
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Add FlexSPI in i.MX8MM EVK device tree
Signed-off-by: Han Xu <han.xu@nxp.com>
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When enabling the panel, the initial brightness level was hard-coded to
0x20. This way, during a suspend/resume cycle, after resume, this
hard-coded brightness was used, instead of the one before suspend.
Removing the hard-coded level and using the one stored in backlight
device.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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suspend/resume
Added no_clk_reset property for 8M dts files, since DSI doesn't need
it's clocks stopped during suspend.
Also, added power on delay for 8QM and 8QXP for a better suspend/resume
stability.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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On some platforms, like the i.MX8M, the Display Controller is not
completely powered off during suspend, just stopped. Since there are
problems if we stop the clocks in DSI sub-system, while the Display
Controller is still powered on, the display clocks will get out of sync.
Adding this new property to specify, on such platforms, not to reset the
clocks.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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Remove the NO_CLK_RESET define and add a property for this.
On some platforms, like the i.MX8M, the Display Controller is not
completely powered off during suspend, just stopped. Since there are
problems if we stop the clocks in DSI sub-system, while the Display
Controller is still powered on, the display clocks will get out of sync.
Adding this new property to specify, on such platforms, not to reset the
clocks.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
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add node for MIPI CSI, CSI, and camera OV5640
Signed-off-by: Robby Cai <robby.cai@nxp.com>
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on imx8mm, use different way rather than via SRC. so use different
device id to distinguish different MIPI-PHY reset method.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
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add csi clock, CLKO1 for MCLK, and also BUS clock
Signed-off-by: Robby Cai <robby.cai@nxp.com>
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We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs.
When tile resolving is enabled by using the new IPs, the design team
indicates that DPU fetch unit base address and DPU/PRG stride need to be
calculated in the below steps:
1) prg_Baddr = dpr_Baddr
2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel
3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1)
tmp_burst_size = round_up(tmp_burst_size, 8)
burst_size = min(tmp_burst_size, 128)
4) tmp_dpu_stride = dpu_width * bytes_per_pixel
5) dpu_stride =
round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size)
6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride
7) prg_stride = dpu_stride
The legacy DPR/PRG IPs and linear formats driver logic should not be
essentially touched.
This patch implements the above calculation method in the drivers
so that all valid in-micro-tile x/y cropping arguments can be supported.
Without this, at least, some cropping cases with odd x value would fail.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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It caused by 10ms delay during isi hardware reset. During this
10ms, runtime PM will call isi runtime suspend/resume callback
but isi is not ready, so delete the 10ms delay.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
(cherry picked from commit 7d0922252f986e6300da75f7cf87ad7a2f511923)
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gpio controller ignored all values were set before request resources,
move the devm_gpio_request to spi_imx_setup to fix the issue.
Signed-off-by: Han Xu <han.xu@nxp.com>
Suggested-and-reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Franck Lenormand <franck.lenormand@nxp.com>
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create multi workqueue for vpu encoder
add suspend and resume code to encoder driver
add wait resume done in decoder resume function
solve coverity issue: 3520461 Out-of-bounds read
Signed-off-by: GuoRui <rui.guo_4@nxp.com>
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enable hdmi rx audio
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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platform device id of TX is 1, RX is 2.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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For entry id of video is 0, audio is 1, if entry id of meta data is
1, then it conflict with audio.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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add delay count in audio auto config to avoid blocking
change the justify to right
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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