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Disabling the battery config variable in the def-config file.
Enabling battery driver causing the kernel boot failure.
Bug 715080
Change-Id: I479bb8b9611af67737a3f86d6a10bc5824c55ec4
Reviewed-on: http://git-master/r/4449
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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defconfig change to enable battery changes for ventana
Change-Id: Ib4da3a7328c89b86a5557cb9255360dd7fa3df56
Reviewed-on: http://git-master/r/4362
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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removed the BoardID based identification, now use only Peripheral GUID for
determining if the board supports accelerometer or not
Change-Id: I95938ff4836cbb0bb8547e2d9684dfb534816bfc
Reviewed-on: http://git-master/r/4031
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The GPIO port R pin 6 needs to be set low for charging of battery on ventana rev C
Change-Id: I2ac17494f65f550d5bf676ae8ec09819983b72ac
Reviewed-on: http://git-master/r/4171
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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It is recommended by ASIC to make sure that fifos are empty
before starting any new transfer specially dma based transfer.
Adding support code for this.
Change-Id: Ic6b5db650b50e664b5cdd601eed9e0c3286a764b
Reviewed-on: http://git-master/r/4211
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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SDRAM initialization is broken in the boot ROM on AP20 A03, so LP0 restore
needs to reload the first-stage bootloader and then jump to its LP0
restore sequence. to trigger this behavior, the lp0 flag is moved to a
dummy location in the scratch register which the boot ROM ignores, but
the bootloader will detect.
Change-Id: Iea144e7440367938755ab66d67758558bc184b44
Reviewed-on: http://git-master/r/4022
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Fixed timer "fix" in commit c0fd286380b8b5276c7aed6fb7a9f5eacde9f60e.
Removed from the LP0 entry path call to set_power_timers(), that could
overwrite 32kHz-scaled timer values. This did not happen (and original
"fix" worked in testing) because set_power_timers() does nothing when
there is no change in APB frequency since last call, i.e., since last
LP2 before LP0.
Change-Id: Ida84319f26eff06d4d94f11c717fe667082bb54f
Reviewed-on: http://git-master/r/4376
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Sometimes, due to high interrupt latency in the continuous mode
of DMA transfer, the half buffer complete interrupt is handled
after DMA transferred the full buffer. In this case, SW DMA state
and HW DMA state is out of sync. When out of sync detected,
stopping DMA immediately and restarting the DMA with next buffer
if next buffer is ready.
bug 696953
Change-Id: Ic4b7cb251e472a309e9583eedbd26ea5dfcfceb1
Reviewed-on: http://git-master/r/4351
Tested-by: Victor (Weiguo) Pan <wpan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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smp_processor_id() must not be called from a preemptible context (this
is checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so.
This lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth
could be incremented, causing a BUG_ON(*depth <= 0); in
kunmap_high_l1_vipt().
The solution is to move the call to smp_processor_id() after the call
to preempt_disable().
Change-Id: I205a85ebecaedb430860462012d0571b83f08adc
Reviewed-on: http://git-master/r/4342
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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The CP14 (debug interface) registers were not being saved as part of
the CPU suspend context. This can cause attached JTAG debuggers to
lose their mind after CPU hotplug or suspend.
Change-Id: Ia9cfd8a711160fd1f0852c33e3fb72f15298de85
Reviewed-on: http://git-master/r/4281
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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In odm query, returning the is_removable prop of sdio3
from the static array. The redundant check is removed.
This is causing locking issues between kernel and nvrm.
Bug 711837
Change-Id: I9d49a0f65ebb1de79d091badb0f316798c63c1cf
Reviewed-on: http://git-master/r/4340
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The rm spi driver is using the nvrm dma driver which is wrapper
over the native dma. Using directly the native dma driver to
get rid of one more level of wrapper call from spi driver.
Making sure that prev dma operation is completed before starting
new transfer.
Removed the code which was specific to OAL as this is not
required any more.
Calling the write buffer barriers after writing into the write
dma buffer and before starting the transmit dma to make sure
that all written data is available in physical memory before
dma start.
Change-Id: Iabcd86f0d63b2decffda0ad6da6f1b22161e9d3b
Reviewed-on: http://git-master/r/2670
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Regulator current limit uses mutex, which is called from the irq after acquiring
the spin locks. Similarly when vbus is detected phy clock enable is called,
which uses mutex inside the spin locks. This is fixed by calling these apis
under work when called from interrupt context.
Bug 711837
Change-Id: Ib926ad33d3d3674353447b3d94ff63f9eecf6f65
Reviewed-on: http://git-master/r/4339
Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Frank Cheng <fcheng@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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with out this change, we would only support signal mode 0...
Change-Id: I2cd2c9a3e30da94f2e95a654f3154fd33e940f13
Reviewed-on: http://git-master/r/4286
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Rescaled CPU power timers to 32kHz clock on entry to LP0 (before these
timers were rescaled only on entry to LP1, but power off timer does
affect LPO as well).
Change-Id: Ifb316170a1225767f3e9b9033b5f5cb0999504d4
Reviewed-on: http://git-master/r/4349
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Iqbal Bhinderwala <iqbalb@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Setting the gpio to Input mode for the HDMI.
Change-Id: If8eebb714bf09450ebaf5cae924e2b5cae4048df
Reviewed-on: http://git-master/r/3771
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Set 2 sources of wake up, for ventana
1. PWR key
2. WAKE key
Added support for reading the odm option for the low power state from the
odm data that is provided during nvflash.
Change-Id: Ib8da228a89bb514f1bce2f4971e432c269cd80ea
Reviewed-on: http://git-master/r/4187
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Set LP2 configuration options for NV platforms.
Change-Id: I5fcf1192f0b30774496ddcc95ca71e9613a7aecc
Reviewed-on: http://git-master/r/4233
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The interrupt thread handler have the static variable inside
a function. This is causing the corruption in the variale
when two processor execute the interrupt thread at same time
in smp mode.
Removing the qualifier static of a variable as this is not
required and also safe in smp mode.
Change-Id: I43fdab81a0a71c82e67eb4c12be0826f3bd8a927
Reviewed-on: http://git-master/r/4300
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Added GUID for broadcom and csr to identify which BT chip is
present.
Change-Id: Ib4163d2aacd97700047be4f20b66fc40d7aa1a35
Reviewed-on: http://git-master/r/4238
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
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There was a change introduced in K32 to optimally spin inside the
mutex-lock implementation. This in-turn caused a regression and
manifested as a soft-lockup in kernel while running mulit-media stress
test.
By enabling this config, we are disabling the newly introduced change.
Bug 702462
Change-Id: I25720a4462a2c6a1b52a9682ba5cbc03a7bcca19
Reviewed-on: http://git-master/r/3718
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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After resume from LP0 VBUS and ID interrupt enable bits are cleared and are not
enabled. So cable connect/disconnect is not functional after resume from LP0.
This is fixed by enabling the interrupts during the resume functionality.
Bug 712862
Change-Id: I67fd63f4daefbb811757c675538071371242c428
Reviewed-on: http://git-master.nvidia.com/r/4266
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Set CPU power off time on Whistler to assure correct power-on reset on
exit from LP2.
Possible fix for bug 710566
Change-Id: Ifb15183150b32345e21df23da96dc5d76fdb0802
Reviewed-on: http://git-master.nvidia.com/r/4189
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Adding odm support for broadcom bcm4329 chip.
Change-Id: I9155d06c37ca31ad00f0c90fa1470ea9ad384ec0
Reviewed-on: http://git-master.nvidia.com/r/4236
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Integrated Elpida EMC DVFS table for Whistler E1108 processor board.
Bug 709629
Change-Id: I493d2e8cb3f87b9bcabeee97602994d4d85c794e
Reviewed-on: http://git-master.nvidia.com/r/4106
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Setting OTG state to device mode on resume from LP0 if VBUS is detected during
LP0 resume.
Change-Id: Ib029e6ea5b1d3e4b5c4b5c913c71e2789106a426
Reviewed-on: http://git-master/r/4247
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Making DeepSleep as a default power state during system suspend.
Suspend[LP1] power state can be selected with ODMDATA
Change-Id: I41fbffb901174a121447e1f97de2d8150245d1db
Reviewed-on: http://git-master/r/4115
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Added configuration options to set default LP2 policy.
Change-Id: I81820f575858dda62d31b304b6adf09f7d0f3689
Reviewed-on: http://git-master/r/4164
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Adding rfkill Implementation for Broadcom BT chip (BCM4329) in
existing code.
Change-Id: I9a59052ca440124a1039255c72aa7cb00a015416
Reviewed-on: http://git-master/r/3883
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Bug 678046
Change-Id: Id807aeb5fb004ec52714603aae78debf76b7c405
Reviewed-on: http://git-master/r/4229
Reviewed-by: Bowen Sun <bsun@nvidia.com>
Tested-by: Bowen Sun <bsun@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Bug 678046
Change-Id: If9b208a47e77e9c57c02d89c4c133933a82249df
Reviewed-on: http://git-master/r/4095
Reviewed-by: Bowen Sun <bsun@nvidia.com>
Tested-by: Bowen Sun <bsun@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Change-Id: I353d5ff87243c3098100320b2cd184b47b471e84
Reviewed-on: http://git-master/r/4182
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
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Implemented SW WAR for getting Updated IV for X9.31 using
following steps:
1. Perform CBC encryption on zero data to get
A=CBC(encrypt, plaintext=zeroes)
2. Perform ECB decryption on A. This will result in Updated IV.
UpdatedIV = ECB(decrypt, A)
In the current implementation X9.31 operations are disabled with
key slots where reads of Updated IV have been disabled.
This restriction has been removed now.
Bug 672022
Change-Id: I756d8500e00b9572648eec5803a5a04e25a7b70d
Reviewed-on: http://git-master/r/4129
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Adding the entry for volume-up, volume-down and onkey of
ventana to support these keys events.
Change-Id: Ia01f369626052de7a76361d47b6df1d5839b7353
Reviewed-on: http://git-master/r/4141
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Disabling the CONFIG_WAKELOCK config variable from defconfig file.
Bug 700568
Change-Id: I042937ea692d08f6ce6754295fb9c628536acdb2
Reviewed-on: http://git-master/r/4113
Reviewed-by: Rakesh Iyer <riyer@nvidia.com>
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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gpio-names.h must be included as a local header, not a system header.
Change-Id: I3ea5d2f92bb283f68e6acbfb5bc813cd993a8acf
Reviewed-on: http://git-master.nvidia.com/r/4161
Tested-by: Maria Gutowski <mgutowski@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The problem is that some drivers can keep GART memory pinned, fragmenting
it and making impossible to pin the memory allocated in other process.
24M limit on GART made situation less probable but didn't solve it
completely.
This fix disables GART allocation for ap20rm_i2c driver.
Change-Id: I22889a58ca9f6c0e38b00301abd36e272654e7d4
Reviewed-on: http://git-master/r/4150
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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- Change TEGRA_DEFAULT_BUFFER_SIZE to 4k, as it's the normal
processing size in Audiofx.
- Update tegra_sndfx.h to keep it in sync with audiofx header
file.
Change-Id: Ica7a396b4fa66134be7193a983da64b312fe5f38
Reviewed-on: http://git-master/r/4131
Tested-by: Manjula Gupta <magupta@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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change to subtract the boot partiotion size from the entire device size
so that proper device size is reported.
updated the code as per suggestions from Gary, removed the comment
bug: 683019
Change-Id: Iaa1a8d773dc1b876eb1da55823ff44a7f745d234
Reviewed-on: http://git-master/r/3496
Tested-by: Nitin Ghate <nghate@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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To avoid spurious signal transitions on exit from deepsleep
pinmux restoration should be done in an order.
Change-Id: Ie7fc48c964aef83d7f6c5e150d9b0f387bd26998
Reviewed-on: http://git-master/r/4116
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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The POR value of the lcd_de pin is pull up. Becasue of
default pull up of lcd_de pin, display controller is
triggering the frame even when TE is not connected to
the panel. So, configuring the lcd_de pin in Normal mode
instead of default pullup. With this change, Android is
display is seen on the dsi panel only when TE is connected
to the panel, else there will not be any display.
Tested on: Whistler, Android using dsi panel.
Bug 703400
Change-Id: I0f934d703caedac1be2317bfe80568d3a74e21db
Reviewed-on: http://git-master/r/4126
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Enabling the USB_SUSPEND config variable from defconfig file.
Bug 700516
Change-Id: Icf7c5c8cfc571b95f8315f3da027ba3c0d601acf
Reviewed-on: http://git-master/r/4105
Reviewed-by: Rakesh Iyer <riyer@nvidia.com>
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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In continous mode, dma should stop after last transfer completed and
if there is no more req pending.
If there is pending req then it should check whether it has updated
in hw for next transfer or not and if it has not started then stop dma
and start new req immediatley.
Change-Id: Id79f72fbd9650685962fc7085b6bb8f818effd27
Reviewed-on: http://git-master/r/3799
Reviewed-by: Panneer Arumugam <parumugam@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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- Saved/restored CPU power Off timer on LP1 entry/exit
- Re-arranged symmetrically suspend entry/exit code
Change-Id: Iebc2f56e2794e1e93f2c195f22d70007243b1036
Reviewed-on: http://git-master/r/3989
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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After long time of executing LP0 cycles some times device fails to handle the
udc irq in OTG mode. This is due to the OTG state which is changed to unknown
before the controller is completely stopped. Fixed this by setting OTG state
properly to unknown only after disabling the interrupts and stopping the
controller completely in suspend path.
Change-Id: I4baf2f29857cd35937acc67aca7c01077e362be1
Reviewed-on: http://git-master/r/4016
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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change 53f34260 accidentally deleted the code that checked the dma
address to determine if it needed to be bounced, so no bouncing was
performed.
revert this part of the change
Change-Id: Iae2d097c38e178c25132cacfe58c132736186c46
Reviewed-on: http://git-master/r/4053
Tested-by: Szming Lin <stlin@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Registering the board info for the magnetometer AK8975 and ALS
isl29018 hw monitor i2c client driver based on ventana board
layout.
Change-Id: I48d4dbb62605c2c840af4df4e6d31ae371fe75ba
Reviewed-on: http://git-master/r/3855
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Modified AES kernel driver to copy client buffer into DMA
buffer instead of copying it to local buffer.
This reduces number of memory copies from four to two.
Bug 660522
Change-Id: Iafb4aff9c8d10e1bc40bef29ef762174420ec057
Reviewed-on: http://git-master/r/4069
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Enabling the CONFIG_SENSORS_AK8975 for enabling the magnetometer
AK8975 driver to provide the measurements of magnetic flux in
3 axis.
Enabling the CONFIG_SENSORS_ISL29018 for enabling the intersil
ISL29018 driver to provide the ambient light sensing in lux.
Change-Id: Id289dde1d216096a02520e373f2a1a408a87229a
Reviewed-on: http://git-master/r/3861
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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Adding the new kernel driver for the ambient light sensor which
provides the light intensity measurement functionality.
This kernel driver provides the sysfs interface to change the
property and read the lux information. Following sysfs interface
are available:
op_mode: set the opertaing mode as 0 for power down and 1 for
conversion.
min_range: Set the minimum range for the light sensing.
max_range: Set the maximum range for the light sensing.
show_lux: To get the current light intensity in lux. This is
blocking call and convesrion start once this file is
read.
The driver can be enabled by setting the CONFIG_HWMON to y and
CONFIG_SENSORS_ISL29018 to y in the defconfig. The board information
for device can be provided through odm init code.
Change-Id: Ifaf2cb322506efc27005980d6924bcc69ff9725f
Reviewed-on: http://git-master/r/2546
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
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