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2012-11-09ARM: tegra: Document sysfs/debugfs LP2 node changeBo Yan
The name of one sysfs node for CPU power state control has been changed from "lp2_in_idle" to "power_down_in_idle", the name of the corresponding debugfs node has been changed from "lp2" to "power_down_stats". bug 1034196 Change-Id: I72daa591c4da783062f070bd32b4245eb6a350df Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/162462 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-11-09asoc: tegra: cs42l73: Add VSPIN to DAPM routeRahul Mittal
Workaround to get VSP recording working with Cirrus codec Need to add proper DAPM route based on Cirrus inputs Change-Id: I118f90b8561525979e23cfab011e99490d8f86a0 Signed-off-by: Rahul Mittal <rmittal@nvidia.com> Reviewed-on: http://git-master/r/162260 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijay Mali <vmali@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-11-09video: tegra: dc: Select BACKLIGHT_CLASS_DEVICERobert Morell
We call into the bl subsystem for smartdimmer. Building without it will fail to link. Bug 1047558 Change-Id: Ia6fb4b4e343509811e764ddaf9aface71f1d3269 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/162168 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-11-09Revert "ARM: tegra: misc: pmureader driver"Bo Yan
This reverts commit c1be13b9d1895756acb18054a2c14b595bfd6037. Change-Id: I02c1683f98816a59fdce6932d115e45460a4cbc0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/161865 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-11-09media: video: tegra: ov9772: add 960x720 supportPhil Breczinski
Add support for 960x720 resolution to ov9772 driver. This provides a 4:3 resolution in addition to the existing 16:9 resolution (720p). Also includes support for sensor-specific setmode frame delays (needed for driver functionality). Bug 1156852 Signed-off-by: Phil Breczinski <pbreczinski@nvidia.com> Change-Id: I5dfb5f9aa131caae66f19ff975b879b4a54c2788 Reviewed-on: http://git-master/r/161830 Reviewed-by: Frank Chen <frankc@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-11-09arm: tegra: iovmm: add tracing support for iovmm.Krishna Reddy
Change-Id: Iea1c776a66f35b10bb182220dab8db99ff5d4e64 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/161824 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
2012-11-09arm: tegra: panels: sd update bl after linear bl adjustmentsMitch Luban
Smart dimmer assumes a linear backlight. Therefore, we should be applying smart dimmer backlight adjustments after we do linear backlight correction. Bug 1047558 Change-Id: I9a4705b752fddaf647ac566e9dc07636a2069dbc Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/161818 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-09video: tegra: dc: allow r/w of cmu_enable sysfs nodeMitch Luban
Allows reading and writing to cmu_enable sysfs node. Change-Id: I66e09c7bd9eb92e1125cd311608bd0ac3f6bf7bc Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/161795 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2012-11-09 i2c: tegra: handle system rebootSeshendra Gadagottu
When system reboot happens, if any i2c tranafers are active then they are cauing issue after reboot. To avoid this, shutdown handler is added and i2c driver is suspended before shutdown. Bug 1159422 Bug 1164896 Change-Id: I50c7659b6051840f19a5b4dcff7544df649a7617 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/161724 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Chaitanya Bandi <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-11-09arm: tegra: isomgr: Fix deadlock issues.Krishna Reddy
Fix the deadlock issues and avoid renegotiations for the client, who is realizing. Remove redundant variables. Change-Id: Ie95a875682cc46caf3c7a8af407e6704732c5f36 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/161387 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com>
2012-11-09hwmon: ina219: INA219 driver with more sysfsAnshul Jain
This new driver allows state change of the INA219 device using this sysds node: To turn the ina219 device on, echo 1 > /<i2c device path>/cur_state To turn it off: echo 0 > /<i2c device path>/cur_state It has new sysfs nodes current2_input and power2_input that contains current and power calculated using shunt resistor and voltage drop across shunt resistor. This driver is backward compatible with the old driver. Bug 1160868 Change-Id: I5e05947e8e3b20a85f02188a48ea4441218e27a8 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/160070 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-11-09ARM: tegra: dalmore: Change INA219 platform dataAnshul Jain
Changed INA219 platform data declaration to include values of shunt registers, trigger config data and continuous config data Bug 1160868 Change-Id: I0bfaeaa217607272b48bdab256d1990ffa8e4da2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/160068 Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-11-09ARM: tegra: cardhu: Changed INA219 platform dataAnshul Jain
Changed INA219 platform data declaration to include values of shunt resistor, continuous config data and trigger config data Bug 1160868 Change-Id: If7bcae81804b2807f11daae524bf66055ba3dd03 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/160067 Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-11-09hwmon: ina219: Update INA219 platform dataAnshul Jain
platform data structure now contains: shunt resistor value trigger config data continuous config data Bug 1160868 Change-Id: I5a4102745db2304fd7c5735981e1f70d182f32f6 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/160065 Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-11-09tty: serial: tegra: Add stub runtime power managementPradeep Goudagunta
Add stub runtime_pm calls which go through the flow of enabling and disabling but don't actually do anything with the device itself as there's nothing useful we can do. This provides the core PM framework with information about when the device is idle, enabling chip wide power savings. Bug 887359 Change-Id: I159f7798dbf141813ec1aa56ddb06cc8ca6595f4 Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/159835 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-09arm: enable the control of CORENPDRQ bitLiang Cheng
Transitions to suspend states cripple any ongoing JTAG or coresight debug session. It can be prevented by setting the bit CORENPDRQ in debug register DBGPRCR. This change provides the control interface. Bug 1029902 Change-Id: I1d82dfdce4136f3c9bd40f1a5d6dc619020fe6fc Signed-off-by: Liang Cheng <licheng@nvidia.com> Reviewed-on: http://git-master/r/147012 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-11-09arm: tegra: cardhu: print less alarming messageNaveen Kumar S
Print a less alarming message for cardhu boards which does not have the mechanical fix for touch screen. Bug 1049937 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Change-Id: I114b05fa513d3e03994498da7670d76ab247b52f Reviewed-on: http://git-master/r/146374 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-09media: video: tegra: Ad5816 power/gpio changesSudhir Vyas
* Reorganise power sequence. * Restructure focuser driver code. * Add support for dalmore focuser. * Make changes for image sharpness. * Remove unnecessary code. Bug 1156996 Bug 1157339 Change-Id: I578e6f586a66f751d35a6cc99fa5e7c229194ff9 Signed-off-by: Sudhir Vyas <svyas@nvidia.com> Reviewed-on: http://git-master/r/160205 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com> Reviewed-by: Charlie Huang <chahuang@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-11-09ARM: tegra: ad5816 power/gpio programming changesSudhir Vyas
* Reorganise power sequence. * Add support for dalmore focuser. Bug 1156996 Change-Id: I63a7b133f18922061f2bca96dbaf6f39172f3749 Signed-off-by: Sudhir Vyas <svyas@nvidia.com> Reviewed-on: http://git-master/r/159880 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-11-08media: video: tegra: add imx091 nvc driverWei Chen
add NVC framework driver for imx091 Bug 961418 Change-Id: I2a6c984eac956f62fefb36119d3868aadb800f26 Signed-off-by: Wei Chen <wechen@nvidia.com> Reviewed-on: http://git-master/r/159376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Frank Chen <frankc@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-11-08drivers: power: tps65090: detect battery from fuel-guageSyed Rafiuddin
detect battery in tps65090 charger driver using bq20z45 fuel-gauge driver. Change-Id: Ic19a8f2459b3fecde2c7cf17b3d02b9e4b71c307 Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com> Reviewed-on: http://git-master/r/161649 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Daniel Solomon <daniels@nvidia.com>
2012-11-08video: tegra: host: Fix error handling of reg readJuha Tukkinen
Check value of mem_sgt and check value of mem_dma only after setting it. Change-Id: I949cbc3b3496e959234c8ad8c24d9f60250dcb1a Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/161566 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-11-08ARM: tegra: dvfs: Add targeted predict millivolts APIsAlex Frid
Implemented voltage prediction APIs that return expected voltage for clock domain if pll or dfll clock source is used, regardless of the actual source selection (in addition to existing API that predicts voltage for current clock source selection). Made sure dfll mode can not be enabled for clock domains that do not have dfll support. Change-Id: I6bb0b7ab5fa60bc6633ebb207f3fc6e52844f770 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/161078 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-11-08arm: tegra: dalmore: Add Sharp LQ101R1SX01 panel supportAnimesh Kishore
10.1" 2560x1600 panel. Change-Id: I13a901114c908ce1b2d5e2025594def50f8d151c Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/160725 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-08arm: tegra: dalmore/pluto: add imx091 nvc driverWei Chen
add board file related changes for imx091 nvc driver Bug 961418 Change-Id: Ibc179fbfac0e31642158990c0ac77c52076b5ace Signed-off-by: Wei Chen <wechen@nvidia.com> Reviewed-on: http://git-master/r/160285 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-08ARM: tegra11: dvfs: Enable CPU and core voltage scalingAlex Frid
Set configuration options for CPU and core voltage scaling. No changes in current system behavior (VDD_CPU is scaled, VDD_CORE is not scaled) is expected, since - by default after boot DFLL is used as CPU clock source, and CPU voltage is automatically scaled by CL-DVFS (this change only enables scaling when/if PLL is used as a clock source) - EMC DVFS tables requires nominal voltage for all rates, and effectively prevents core voltage scaling, even if it is enabled Change-Id: I9a1ee3a9dfce57521dd31f75d767763238be2acc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/160138 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-08arm: tegra: tai: PRISM calibration for TaiMitch Luban
Modified board-enterprise-panel.c file which has calibration data for Tai panel. Bug 1029936 Reviewed-on: http://git-master/r/130834 (cherry picked from commit 695665ca15c1b71786b1d98ac8193076de76db94) Change-Id: I4cb164359bbb2b5047b1f48f470a0106e4cbda1a Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/133722 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-07Revert "arm: tegra: Separating out pmc from usb phy."Ray Poudrier
This reverts commit c2958491e5a392be8f52824d59eabadb34b82060. Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: Idf66b95f1df2b732d319357ae4ea54f798cba82d Reviewed-on: http://git-master/r/162093 GVS: Gerrit_Virtual_Submit Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-07ARM: tegra: Kconfig: NVMAP_CACHE_MAINT_BY_SET_WAYS for tegra11xHiroshi Doyu
Enable NVMAP_CACHE_MAINT_BY_SET_WAYS for tegra11x Bug 1158336 Change-Id: I72ac4790c859cd464fafcde4f5da5c45d3d0abeb Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/161224 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-07arm: mm: cpa: Configurable cache_maint_{inner,outer}_thresholdHiroshi Doyu
Introduce configurable cache_maint_{inner,outer}_threshold via debugfs. Bug 1158336 Change-Id: I7bb94adadbc41ff65dbd9992920c938df2449b06 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/161209 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-11-07video: tegra: nvmap: Configurable cache_maint_{inner,outer}_thresholdHiroshi Doyu
Introduce configurable cache_maint_{inner,outer}_threshold via debugfs. Bug 1158336 Change-Id: I0b20d44ddf1e8e88954ac8fac7750b4e31959564 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/161208 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-11-07video: tegra: nvmap: Clean up fast_cache_maint()Hiroshi Doyu
Get rid of ifdef in a function for readability. Bug 1158336 Change-Id: I31e9521f97dda91fecf523bcd49ff5b34db86e45 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/161207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-11-07ARM: tegra11x: cpuidle: Remove LP2 referencesBo Yan
This change completely removes references to lp2 in cpuidle-t11x.c, some related changes also affect cpuidle-t2.c, cpuidle-t3.c, and a few other files. bug 1034196 Change-Id: Ic2387bf614b39bd08ed4b2fc6e996f6fbf8306c0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/160017 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-11-06input: misc: Added sysfs to MAX77665 haptics driverSumit Sharma
Added sysfs support to access and modify vibrator parameters Change-Id: If372f0ce8df34c6b88a87056c4a214f63207d108 Signed-off-by: Sumit Sharma <sumsharma@nvidia.com> Reviewed-on: http://git-master/r/159817 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-11-06arm: tegra: Added MAX77665 vibrator EDP dataSumit Sharma
Added EDP states in MAX77665 platform data for EDP implementation Bug 1043388 Change-Id: Ieae95d196a43526084c11f3ee1063af57b6cc0e0 Signed-off-by: Sumit Sharma <sumsharma@nvidia.com> Reviewed-on: http://git-master/r/159816 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-11-06input: misc: Added EDP support in MAX77665 haptics driverSumit Sharma
Registered vibrator EDP client Implemented throttle callback function for EDP Bug 1043388 Change-Id: I444251c6791baf112fdc86bed9aa02994236bde7 Signed-off-by: Sumit Sharma <sumsharma@nvidia.com> Reviewed-on: http://git-master/r/159815 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-11-06regmap: no need primary handler for nested irqYunfan Zhang
The primary handler will NOT be called if the interrupt nests into another interrupt thread. Remove it to avoid confusing. Signed-off-by: Yunfan Zhang <yfzhang@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit 81380739516730124067576c9cc9f2418be5bf36) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: If06302d8d5806c00f34dd473b3ad937ebe626000 Reviewed-on: http://git-master/r/161555 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-11-06regmap: irq: Add mask invert flag for enable registerXiaofan Tian
Currently, regmap will write 1 to mask_base to mask an interrupt and write 0 to unmask it. But some chips do not have an interrupt mask register, and only have interrupt enable register. Then we should write 0 to disable interrupt and 1 to enable. So add an mask_invert flag to handle this. If it is not set, behavior is same as previous. If set it to 1, the mask value will be inverted before written to mask_base Change-Id: I1c6875de71e0b9b9a89a23c1669638df4dfe541e Signed-off-by: Xiaofan Tian <tianxf@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/161554 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-11-06regmap: irq: initialize all irqs to wake disabledStephen Warren
The kerneldoc for irq_set_irq_wake() says: Enable/disable power management wakeup mode, which is disabled by default. regmap_irq_set_wake() clears bits to enable wake for an interrupt, and sets bits to disable wake. Hence, we should set all bits in wake_buf initially, to mirror the expected disabled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit 40052ca0c243d101cfadd65936f60ef81df10b02) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: I2ae49a53467ea10eb01b37604a093c99720d4d37 Reviewed-on: http://git-master/r/161553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-11-06regmap: set MASK_ON_SUSPEND/SKIP_SET_WAKE if no wake_baseStephen Warren
If a regmap-irq chip has no wake base: * There's no point calling .irq_set_wake, hence IRQCHIP_SKIP_SET_WAKE. * If some IRQs in the chip are enabled for wake and some aren't, we should mask those interrupts that are not wake enabled, so that if they occur during suspend, the system is not awoken. Hence, IRQCHIP_MASK_ON_SUSPEND. Note that IRQCHIP_MASK_ON_SUSPEND is handled by check_wakeup_irqs(), which always iterates over every single interrupt in the system, irrespective of whether an interrupt is a child of a controller whose output interrupt has no wake-enabled inputs and hence is presumably masked itself. Hence this change might cause interrupt unnecessary masking operations and associated register I/O. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit 685879f4b2036e58c1a0cdaaee2b155d3c965461) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: Ibdb63f7574fa2017d1ba1f6f497c787f12f4e260 Reviewed-on: http://git-master/r/161552 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-11-06regmap: name irq_chip based on regmap_irq_chip's nameStephen Warren
This is intended to give each irq_chip a useful name, rather than hard- coding them all as "regmap". Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit ca142750f8ac3d01e45909e624ca783779894640) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: I1dfe76e23fe60b46b33bfc2ef048b8498ffc8ac6 Reviewed-on: http://git-master/r/161551 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-11-06regmap: store irq_chip inside regmap_irq_chip_dataStephen Warren
This will allow later patches to adjust portions of the irq_chip individually for each regmap_irq_chip that is created. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit 7ac140ec426ed304237205be77f99eedfc1186b5) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: Ib73deca2d8ca01d1ec49bdc94ebe20053c97981c Reviewed-on: http://git-master/r/161550 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-11-06regmap: irq: Only update mask bits when doing initial maskMark Brown
Don't write the full register, it's possible there's bits other than the masks in the same register which we shouldn't be changing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> (cherry picked from commit 0eb46ad0c8d60943c1f46cef795fc537fbffd177) Change-Id: I4e9f42422e961f9f842ab793227af7be25ca82cf Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/161549 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-11-06regmap: fix some error messages to take account of irq_reg_strideStephen Warren
A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> (cherry picked from commit 16032624f511b2fac0671cba5e7da40aa7e73a66) Change-Id: I60e982d5f9f2bc5aba7a8a72e45893e23c4bb0d4 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/161548 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-11-06asoc: tegra: Rt5640: modify DAPM route tableVijay Mali
a) register DAPM route table with snd_soc_card structure and remove the open-coded DAPM add route calls. b) set card.fully_routed flag to request the ASoC core calculated unused codec pins, and call snd_soc_dapm_nc_pin() for them. Bug 1054060 Change-Id: I512b6329bf1328eff172f40d4cc6b59c763f1323 Signed-off-by: Vijay Mali <vmali@nvidia.com> Reviewed-on: http://git-master/r/161249 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
2012-11-06arm: tegra: sdhci: Set emmc voltage to 1.8Vrrajk
Set emmc supply interface voltage to 1.8V Bug 1167307 Bug 1167312 Change-Id: I066fba8fe68b74d540a5803cc463ceef75cdfebb Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/161248 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-11-06mmc: tegra: Set proper emmc voltagerrajk
Check interface supply voltage limit of emmc and set it to 1.8V or 3.3V at resume Bug 1167312 Bug 1167307 Change-Id: I2dda670ed9c270761f61eacb93233a7487894d84 Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/161246 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-11-06spi: tegra11: Set MODE bits before setting CS bitKunal Agrawal
Implemented change to set the MODE bits first and then set CS and other bits of the command register. Bug 1168218 Change-Id: I87bd94b8fac5821f11e575e53ee5694d6cad6d2c Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/161184 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-11-06ARM: tegra: configs: Enable ROTH platform supportPavan Kunapuli
Change-Id: I2c56843f1fad3d962be811a4a83e0aae10dedaa5 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/161159 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-11-06ARM: tegra11: dvfs: Update miscellaneous dvfs tablesAlex Frid
- Updated dvfs tables for SBUS (system clock), Host1x, and VI clocks - Updated maximum limits for Host1x and MSELECT clocks - Allowed only integer divisors for Host1x, VI, and MSELECT clocks Change-Id: I4128cde767609a6bf4ccc3dd85a0f060feaa2dcb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/147681 (cherry picked from commit 03a2546f2745dab8a8adda72777a062b7c113865) Reviewed-on: http://git-master/r/161070 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-01-29 18:24:21 +0000