Age | Commit message (Collapse) | Author |
|
|
|
In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit f97994abf50e9917a959ae62eabd08908a75a222)
|
|
In order to save the power consumption, enable the
PDDQ mode of AHCI PHY when there is no sata disk
on the port
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit a53c29d7e484a3562e3a4f24d952485fbeb4c933)
|
|
The chip document says the counter counts up to period_cycles + 1
and then is reset to 0, so the actual period of the PWM wave is
period_cycles + 2
Signed-off-by: Yuxi Sun <b36102@freescale.com>
(cherry picked from commit e1465447502c77b2951af7ace43d8f76fa5039fb)
|
|
The FlexCAN clock source must be lp_apm (24MHZ) instead
ipg_clock_root (60MHZ) to meet automotive clock requirements.
Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com>
(cherry picked from commit b7456a4f5f6fa12235effbffe4e4d1b62159b948)
|
|
Increase DMA zone size from 96 to 112 size, and default size is 112,
change imx5_defconfig, change SPBA0_BASE_ADDR_VIRT from 0xFB100000 to
0xF7C00000 , so that it can't overlap with DMA zone
Signed-off-by: Robin Gong <B38343@freescale.com>
(cherry picked from commit 2d04dcb9b717a7c46358987f41a03141eccc42b0)
|
|
Fix typo error for pwm1 pad disable function.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
(cherry picked from commit d04b2646528b586baeecc1f128508b5363e7ed63)
|
|
MX5: Add I2C dummy write when acessing DA9053 registers and mask nONKEY event
for i2c operation before suspend
Signed-off-by: Wayne Zou <b36644@freescale.com>
(cherry picked from commit 0cc56da7dc91bbd5b6e9a51c1576daedce36093c)
|
|
DA9053 i2c issue: Rarely the i2c interface of DA9053 hang and it can
not be recovered if not power off totally. The Dialog suggests adding
dummy write for DA9053 I2C register access, in order to decrease the failure
of DA9053 register access and possibility of i2c failure.
Signed-off-by: Wayne Zou <b36644@freescale.com>
(cherry picked from commit bfd7cba1eeb46977b18a3c5fa65d812817a8294d)
|
|
It fix gpu hang.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
(cherry picked from commit acc00a6f1847bf8cdde1802b4375dc89d5160dfe)
|
|
This patch clears IDMAC_LOCK_EN_1 for tough single display(dmfc=3).
For example, 1080P50/1080P60 with 32bpp fb.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 204a5fb6af1426c499332224dff00f52bdbef39b)
|
|
Add VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM ioctls
implementation for registerring bitwork memory allocated from user
space to vpu driver.
Signed-off-by: Sammy He <r62914@freescale.com>
(cherry picked from commit 98d71e85dbd05df9c866d153a4ead9526a26422e)
|
|
Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM
for vpu driver.
The two ioctls can be used when user allocates working buffer
from user space, for exmaple, allocating it from pmem interface
on android, then register it to vpu driver.
Signed-off-by: Sammy He <r62914@freescale.com>
(cherry picked from commit ad29cb1c2ad8ca4bbb30ff2ff55a4e8888b08373)
|
|
1) Clear IDMAC_LOCK_EN when dual display is enabled
to workaround black flash issue when playing video
on DP-FG.
2) Only set IDMAC_LOCK_EN for IPUv3M.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 7c22da39601cfc6551292cbd2c5c1d9ee3b4fbfa)
|
|
Correct wrong parameter when call ipu_csi_set_window_size function
Signed-off-by: Yuxi Sun <b36102@freescale.com>
(cherry picked from commit c1cb33e5cbebb979967f74eecf55efe6a83884ab)
|
|
This patch restores IDMAC_CH_LOCK_EN_1 register when IPUv3
driver resumes. This avoid the relative issue if setting
IDMAC_CH_LOCK_EN_1 to be zero.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit fce84cf35dcb338886df8e58f66a7ad1048d2abe)
|
|
Because of reboot failure, we add mc34708's WDI reset function and the pin's
mux function when system reboot. So mc34708 will be reset when AP reboot.
Signed-off-by: Robin Gong <B38343@freescale.com>
(cherry picked from commit 8e03278824625e8d528e129ad49e094e4d533f87)
|
|
Set IDMAC_LOCK_EN_1 to make SDC display channels to generate
eight AXI bursts upon the assertion of the DMA request.
This change fixes the random garbage lines when showing
NV12 frames decoded by VPU with V4L2 output on
XGA@60 display's overlay framebuffer. V4L2 output uses
MEM_PP_MEM to do 180 degree rotation.
The issue can be reproduced by the following VPU unit test
on MX53 SMD platform:
/unit_tests/mxc_vpu_test.out -D
'-i /1920x1080_H264_AAC5.1ch.2.1ch_track1.h264 -f 2 -w 1024
-h 768 -r 180 -u 1 -t 1'
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 50f969030c25bc33cf0f05a6a5cad98c52afd858)
|
|
After enable DMA, GPS will keep report these DMA error:
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2050 sr2:508a
UART: DMA_ERROR: sr1:2050 sr2:508b
UART: DMA_ERROR: sr1:10 sr2:1083
UART: DMA_ERROR: sr1:50 sr2:1082
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2050 sr2:508a
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:50 sr2:1083
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
(cherry picked from commit ddaf091fd3f5fae56b3c83f5cf59ee4f189f0a40)
|
|
1) ESAI does not support 44.1Khz
2) need checking word width for asrc p2p mode
Signed-off-by: Dong Aisheng <b29396@freescale.com>
|
|
Reset reg variable before setting or it will set an unexpected wrong value.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
|
|
Change from u8 declaration in pxp_dma.h to __u8
Signed-off-by: Danny Nold <dannynold@freescale.com>
|
|
- Add support for 8-bit grayscale colormaps to be used
during EPDC update processing
- Add support in PxP for programming of colormaps
Signed-off-by: Danny Nold <dannynold@freescale.com>
|
|
there is hardware pin conflict between sii902x DET and egalax touch screen
on mx53 loco board. Request gpio during sii902x probe can fix this conflict
only when these two module not co-exist.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
there is hardware pin conflict between sii902x DET and egalax touch screen
on mx53 loco board. Request gpio during sii902x probe can fix this conflict
only when these two module not co-exist.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
- Move the majority of code from the IRQ handler routine into a workqueue
routine. This should improve system interrupt latency.
- Change the spin_lock protecting EPDC queues into a mutex and change all
associated spin_lock calls into mutex calls.
Signed-off-by: Danny Nold <dannynold@freescale.com>
|
|
When setup irq is received, the status phase of the transfer is primed
on ep0 before the data phase. The usb requests are added to the list
of transfer descriptors (maintained by driver) in reverse of their
expected completion order. Completion order is data followed by status,
however the list of tds contains status followed by data.
Upon completion of the data request, the irq handler proceeds to check
the 1st td in the list -- the status request. In full speed mode,
the status phase has not yet completed at this time, so the td's
ACTIVE bit is still set. This leads irq handler to ignore the completion
interrupt without checking the actual td for the data request that caused
the interrupt.
In high speed mode, this issue does not bear itself out because the status
request also completes by the time the irq handler goes to process the data
completion interrupt.
The simple fix for this issue is to prime the status request AFTER the data
request, so that the list of tds maintained by the driver contains the tds
in the order of expected completion.
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
Do not deal with un-enabled device interrupt
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
Because VUSB is supply by SWBST , we shouldn't off SWBST, otherwise
VUSB will not kept in 3.3V , so there is no normal wakeup signal
produced when USB device plug in or out after system go into stop
mode.
Signed-off-by: Robin Gong <B38343@freescale.com>
|
|
powerdown DAC,LINE_OUT,HP in shutdown
Signed-off-by: b02247 <b02247@freescale.com>
|
|
1. Add DDR self-refresh mode and float pin operation when system idle
For audio playback use case on android r10.3, it can save 10mA@1.54V
about 15mW on DDRIO+ memory power, and 6.6mA@2.5V -16.5mW on VDD_REG
It can reduce more memory power consumption if cpu idle time is longer
2. remove the L1/L2 cache operation during suspend for mx53
The L1/L2 cache are powered by VDDA/VDDAL1 and they should be supplied
according to iMX53 datasheet, there is also no EMPG on MX53,
so it can be removed to improve system performance and power.
3. remap the suspend_iram_base as MT_MEMORY_NONCACHED instead of MT_HIGH_VECTORS
If the IRAM page is marked as Cacheable, the ARM cache controller will
attempt to flush dirty cache lines to DDR, so it can fill those lines with
IRAM instruction code. The problem is that the DDR is in self-refresh mode
and HighZ DDR IO PADs during system idle or suspend, so any DDR access
causes the ARM MPU subsystem to hang.
It needs to cherry-pick two patches(5a4aeb9f6,7c8d972d8) from community.
4. Add DDR self-refresh mode and float pin operation for mx53 ARD board,
and mx53 QS/Ripley board
This patch can resovle ramdom suspend/resume issue, since the early code
didn't consider the TLB missing case during suspend. It needs to save all
the M4IF/IO MUX registers firstly to make sure the page table entried into
TLB, and then enter DDR self-refresh mode.
Signed-off-by: Wayne Zou <b36644@freescale.com>
|
|
fix eSDHC errata 'DDTS ENGcm03648'
if it's command with busy, we should poll data0 signal
until it's high which means bus is idle.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
|
|
The commit f1a2481c0 sets up the default flags for MT_MEMORY and
MT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly
set as default for these entries so remove it. Also adding
the 'L_PTE_WRITE' flag so that these pages become read-write
instead of just being read-only
[this stops them being exposed to userspace, which is the main
concern here --rmk]
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED
types so that at boot-up, we can map memories outside system memory
at page level granularity
Previously the mapping was limiting to section level, which creates
unnecessary additional mapping for which physical memory may not
present. On the newer ARM with speculation, this is dangerous and can
result in untraceable aborts.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
- When usb cable is plugged out, the B_SESSION_VALID interrupt is disabled to
avoid usb disconection work queue interrupting. After usb disconection work
queue task is finished, re-enable it to generate interrupt.
Signed-off-by: Tony Liu <b08287@freescale.com>
|
|
-remove all the un-necessary operation in suspend_irq
-remove delay work queue
-fix review comments
Signed-off-by: Tony Liu <b08287@freescale.com>
|
|
a counter used in sdhci_enable_sdio_irq function is not correct.
calling the function with enable flag will skip enabling the irq if it
follows two continuous calls with disable flag because of the counter.
to resolve this problem, simply set the counter to 1 or 0 instead of counting.
this bug is reported by a customer.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
|
|
[ARM] Do not call flush_cache_user_range with mmap_sem held
We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.
Also, since we really can't be holding the mmap_sem while calling
flush_cache_user_range AND vma is actually unused by the flush itself,
get rid of vma as an argument.
Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106
Signed-off-by: Dima Zavin <dima@android.com>
|
|
in board_init ,kernel will read the system_rev TAG from uboot
and configure the right interrupt gpio
Signed-off-by: Robin Gong <B38343@freescale.com>
|
|
FG pos need be reset to 0 when channel disable, but it will lost old setting.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
For split mode, if using vf/enc task, the display is not correct.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
One issue was found in split mode: For input 1024x600, output 1360x768,
after stripe calculation, input width and input column are not right.
This patch fix this issue.
Signed-off-by: Jason Chen <b02280@freescale.com>
|
|
The standard EHCI design will clear RS bit after usb bus goes to
suspend, but it causes some remote wakeup issues, like remote-wakeup
featured device will be reset after resuming.
According to usb 2.0 spec, the SOF need to be sent out within 3ms
after resume signal ends, or device may consider host disconnects
with device. Freescale's USB Controller (Chipidea's core) will ends
up resume signal automatically within 21ms after it recevices remote
wakeup signal. So, if software does not set RS bit within 21ms after
it recevices remote wakeup signal, the problem described above will
be occurred.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
1. If change defconfig and only build in mc34708 dirver,
the following error is reported:
undefined reference to `mc13892_alloc_data'
undefined reference to `mc13892_init_registers'
undefined reference to `mc13892_get_revision'
This patch is to fix above compiling error.
2. Add mc34708 dependency in Kconfig
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
Driver part
Please follow below load sequence to use OTG
- fsl_otg_arc
- ehci-hcd
- arcotg_udc
Besides, in order to match i.mx53 release windows, it changes some
common code, there will be a better solution at 2.6.38 in future
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
MSL part
Follow below load sequence to use OTG
- fsl_otg_arc
- ehci-hcd
- arcotg_udc
Besides, in order to match i.mx53 release windows, it changes some
common code, there will be a better solution at 2.6.38 in future
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
Merge this patch for SR 1-775080061.
The error is the system can find the CAN bus, but cannot communicate
physically.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
|
|
Use CONFIG_MXS_DMA_ENGINE flag to control mxs dma engine
code
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
Set this clock closed by default, and open it when it is needed.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
|
|
enable coin cell battery charger
Signed-off-by: Wayne Zou <b36644@freescale.com>
|