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use regulator _sel interface set to support auto delay,
as when regulator's voltage go up, it will take some time
to ramp up to the required voltage, so the delay is necessary.
_sel interface set support such function, now we switch to this
interface set.
Signed-off-by: Anson Huang <b20788@freescale.com>
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1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Kree and reset udc_controller should be done when remove udc driver to avoid
kernel dump during modprobe gadget driver after modprobe and rmmod udc driver.
Signed-off-by: make shi <b15407@freescale.com>
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implement headphone and speaker automatically switch
even if headphone is plugin/out during suspend
Signed-off-by: Gary Zhang <b13634@freescale.com>
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soc_pcm_trigger() calls trigger functions of cpu_dai, codec_dai
and platform, but the trigger function of machine is not called.
add calling of trigger in machine driver in soc_pcm_trigger()
Signed-off-by: Gary Zhang <b13634@freescale.com>
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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Remove unused function "asrc_get_output_buffer_size()" to fix build
warning.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Since YV12 format is supported in mxc_v4l2_capture, it should be also
supported in mxc_vout.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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Android CTS verifier have a must requirement for YV12 format. Since IPUv3
common driver has supported IPU_PIX_FMT_YVU420P pixel format, add the
support of YV12 format in mxc_v4l2_capture.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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In current linux BSP USB H1 driver default load before otg driver load,
which cause USBx not match the ehci controller number. like bellow:
root@freescale /sys/devices/platform/fsl-ehci.0$ ls
driver modalias pools power subsystem uevent usb2
root@freescale /sys/devices/platform/fsl-ehci.1$ ls
driver modalias pools power subsystem uevent usb1
Signed-off-by: make shi <b15407@freescale.com>
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1. Refine VPU suspend/resume according to open_count to completely
fix bug: ENGR00230203 [Android_MX6DL_SD] Gallery: System hang
after resume from suspend during video playback. 20%
open_count == 0 case can be simplified because VPU is released
(all instances are freed), so
- clock is already off
- context is no longer needed
- power is already off on MX6
VPU reset is removed from resume because power is ensured to be off
before entering resume on MX6 by calling regulator API.
2. Fix bug: VPU always busy after suspend/resume
Error log (VPU refused to suspend due to VPU busy):
pm_op(): platform_pm_suspend+0x0/0x54 returns -11
PM: Device mxc_vpu failed to suspend: error -11
PM: Some devices failed to suspend
Root cause:
- Suspend happened during vpu_Init(), somewhere after VPU lib started
to download FW (when PC == 0), but before run FW. (BIT_BUSY_FLAG=1,
BIT_CODE_RUN=1).
- In such case, VPU resume downloaded FW and run VPU to idle because
suspend was triggered after VPU was opened (active).
- vpu_Init run VPU again with BIT_BUSY_FLAG=1. So VPU was trapped in
idle loop but BIT_BUSY_FLAG was never cleared. VPU lib regarded VPU
as always busy.
Solution (in VPU resume):
- run VPU FW only if VPU was opened and PC before suspend is not 0
- restore host register is required
- download FW is required, because program memory is lost after power
off.
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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MTD partition for SPI-NOR was not aligned to 8K.
Replace its offset from MTDPART_OFS_APPEND to MTDPART_OFS_NXTBLK.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Since some ethernet MAC flow control is relied on phy pause
status, both link partners exchange information via auto neg to
determine if both parties are capable of flow control.
Advertise phy pause frame to avoid pause frame is not responsed
by the other net node.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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USB does not work when plug in a usb device during system suspend. Under this
case, USB driver will be in low power mode, but WIE bit not be set if usb wake
up is not enabled.So there are only ID change interrupt no USB wakeup interrupt
after system resume.In current bsp, after system resume ID change status not be
clear,and ID change interrupt will continue happen, which cause the system busy.
No checking WIR bit if ID change interrupt happen when USB in low power mode to
fix this issue.
Signed-off-by: make shi <b15407@freescale.com>
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- It is better to disable otgsc and wake up interrupt to avoid an
abnormal interrupt happen during USB driver being removed.
- If the USB host is already at low power mode, only need turn on
the clock, no need turn off the clock.
- Need discharge dp and dm during USB driver being removed ,in order
to avoid a wakeup interrupt happen. And if the USB otg is in host
mode, we should clear discharge dp and dm in fsl_otg_set_host()
during system boot up.
Signed-off-by: make shi <b15407@freescale.com>
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Another patch changed caam_ipg_clk's CG to CG4 and this commit will
revert this change.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix chip select for SPI-NOR and
remove flags for no writeable partition for weim nor and
SPI-NOR
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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On Uart driver, CTS signal were never disabled
on the imx_set_mctrl function since the register was
written inside of the conditional.
if (mctrl & TIOCM_RTS) {
temp |= UCR2_CTS;
writel(temp, sport->port.membase + UCR2);
}
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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when detect hp inserted, disable speaker; when hp is plugout,
enable speaker.
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Warning: no return statement in function returning non-void.
fec_ptp_ioctl return zero when 1588 is not enable.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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When do Ethernet UDP stress overnight test with abundance of
data transmission, RX path may hang-on.
Dump the RX BD, found all BD "Empty" bit is cleared, which means
CPU read BD status is not right and waiting here.
Change BD memroy attribute from Normal to strongly ordered:
changes the memory attribute of C=0, B=0 instead of C=0, B=1.
Apply the change, the issue cannot be reproduced.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Issue:
By default, cd_gpio is 0 for always presented host controller, which is a
valid gpio. Then it will result to free_irq for 0 in esdhc_pltfm_exit for
these always_present host controllers.
Fix:
Invalid cd_gpio if the controller is indicated to be always present.
Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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This patch add device drvier for novatek touch screen driver.
This touch screen chip will be support because it have
more populary screen size.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Per hardware design, we can't set LDO bypass mode on Sabreauto board,otherwise,
system will can't reset,if cpu freq run in 400Mhz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, if we used LDO bypass, will set pfuze register by I2C bus to modify
voltage according to different cpu frequency, if I2C transfer error, we should
restore to old cpu frequency, not only in cpufreq driver but also cpufreq core.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Our SDMA code did not support SDMA M2M copy function before, we add
SDMA M2M copy function in this patch, you can use 'sg' to use this
function, you can refer to 'linux-test/module_test/mxc_sdma_memcopy_test.c'
for how to use this function.
Signed-off-by: Ge Lei <b42127@freescale.com>
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Add V4L2_MEMORY_USERPTR support for csi v4l2 capture
Support V4L2_MEMORY_USERPTR and V4L2_MEMORY_MMAP now
Signed-off-by: Robby Cai <R63905@freescale.com>
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Bypass eMMC version checking, so that eMMC v4.5 can work on current kernel as
eMMC v4.4 cards, no specific v4.5 feature supported. Only basic read/write
operations are supported, also ddr mode is supported.
Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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ov5642 add some delay to wait for sensor stable after S_PARM.
And ov5640_mipi should keep the same behavior.
So the upper layer can trust the first frame comes out of ov5640_mipi.
- delay added according to the recommended time from ov company
Signed-off-by: Sheng Nan <b38800@freescale.com>
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- must add a new config item to enable USB
CONFIG_USB_FSL_ARC_OTG=y
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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The job ring driver exhibited a hang condition in the top of
caam_jr_dequeue() where a BUG_ON statement looks for a condition
where the output ring is said to have valid entries by the ring logic,
but the ring entries apparently have NULL descriptor pointers.
In the initial ARM port of this driver, the cache flush call
of the output ring content occured before the output ring read index
register read occurred, exposing a condition where the driver sensed valid
output entries, yet the entries written by the ring hardware were not
invalidated, and therefore were not visible to the processor, appearing
as false NULL entries.
This patch relocates the invalidate call to immediately follow the
check of the output read index, where it is required.
Signed-off-by: Vicki Milhoan <vicki.milhoan@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Didn't care about pu_regulator is enabled or not when regulator restore if some
regulator set failed.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default.
Signed-off-by: Robin Gong <b38343@freescale.com>
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This bug was introduced by ENGR00229290 which fixed
the problem of greater than 16 LUTs used when 5-bit
waveform loaded. The bug is that now the driver is also
restricted to using 16 LUTs in 4-bit mode.
The fix is to correct the test of the EPDC_FORMAT
register used to determine if a 5-bit waveform
is loaded.
Also removed the while loop in favor of a bitwise OR
used to determine if a chosen LUT has yet to be
acknowledged by the interrupt handler.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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* Aline weim-nor partition layout with u-boot expected
offtsets
"bootloader" /dev/mtd0
"bootenv" /dev/mtd1
"kernel" /dev/mtd2
"rootfs" /dev/mtd3
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Aline spi-nor partition layout
* set correct chip-select value
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Commit 88f5acf88ae6 ("mm: page allocator: adjust the per-cpu counter
threshold when memory is low") changed the form how free_pages is
calculated but it forgot that we used to do free_pages - ((1 << order) -
1) so we ended up with off-by-two when calculating free_pages.
Reported-by: Wang Sheng-Hui <shhuiw@gmail.com>
Signed-off-by: Michal Hocko <mhocko@suse.cz>
Acked-by: Mel Gorman <mgorman@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Currently, we use pm_notifier to enter suspend/resume flow. But in the notifier
we only set cpufreq, didn't tell CPUFREQ core what the current cpufreq setting
now. So in the next time if CPUFREQ core find the current cpu frequncy is not
the value that CPUFREQ core want to set before. CPUFREQ core will force to set
the freqs.old with its own rule, which means the freqs.old will be MODIFYED
unexpectedly, and this will cause wrong loops_per_jiffy. We need add cpufreq_
notify_transition in the suspend/resume interface of cpufreq.
Signed-off-by: Robin Gong <b38343@freescale.com>
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When pause the capture test program, the "working queue empty" message
shows up repeatedly. However this message is expected to show up because
there's no QBUF called. Change pr_err to pr_debug to keep it as debug level.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Without this dependency, we have to manually disable
CONFIG_VIDEO_MXC_PXP_V4L2 when disable CONFIG_FB_MXC_ELCDIF_FB.
Otherwise, a build error shows up. This patch fixed it.
Signed-off-by: Robby Cai <R63905@freescale.com>
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added ioctls are:
VIDIOC_ENUM_FRAMEINTERVALS
VIDIOC_ENUM_FRAMESIZES
VIDIOC_ENUM_FMT
VIDIOC_DBG_G_CHIP_IDENT
Signed-off-by: Robby Cai <R63905@freescale.com>
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Forget submit some local change...
Signed-off-by: Robin Gong <b38343@freescale.com>
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On Sabresd board design, the WDOG_B output to reset external pmic source from
GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,
we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the
related pins.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Restore back cpu freq and regulator if set fail.
Signed-off-by: Robin Gong <b38343@freescale.com>
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U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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This patch add the fuse check for VPU_DISABLE feature. If the fuse
bit for VPU_DISABLE is 1, which means VPU is disabled, then we will
not register VPU device to the kernel.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Setting certain IOMUX settings on SD1 prevents the system from
entering suspend. These pins are already configured as GPIO, so
it does not help to reconfigure them during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Signed-off-by: Terry Lv <r65388@freescale.com>
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