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2010-06-14[ARM/tegra] spi: Adding support for the hw based CS.Laxman Dewangan
It is require to use the hw based CS to meet the timing requirement as: - Minimum CS setup time i.e. time from CS active to first clock. - Maximum CS hold time i.e. CS should be active after last clock. SW based CS can support the above 1 but not 2 because it dpeneds on os load and system performance. To meet the above requirements, it is require to enable the hw based CS. As spi controller support for the hw based CS for the smaller number of packet, enabling this feature. Driver use the sw based CS by default. If client want to use the hw based CS, then it need to enable this through nvodm query NvOdmQuerySpiDeviceInfo table for different CS. For this, client need to set device info as CanUseHwBasedCs = TRUE, CsSetupTimeInClock = xx CsHoldTimeInClock = xx Change-Id: I9e943e0b39f2d75272826cc2ec7687b3434b1c2a Reviewed-on: http://git-master/r/2536 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-14tegra ALSA: Making function and struct names genericSandeep Shinde
Making function and structure names generic instead of being board specific. Also updated the comment at the start of the file with correct file name. Change-Id: I45bd23e97a701c06abee7a37a6e5f307708022d8 Reviewed-on: http://git-master/r/2461 Reviewed-by: Vijay Mali <vmali@nvidia.com> Tested-by: Vijay Mali <vmali@nvidia.com> Tested-by: Sandeep Shinde <sashinde@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
2010-06-12[ARM/tegra] whistler ODM: configure GMA pingroup as pull-upSuresh Mangipudi
The gma pingroup was not pulled up. doing a pull up of the gma pingroup reduces the power on the VDDIO_NAND rail by 1.5 mW. Bug 688283. Change-Id: I73fcd4bf6ebef66ae4cfc1ffcfeef8bed659b611 Reviewed-on: http://git-master/r/2470 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[arm] tegra : added SYSVIPC for GNU Linux configurationYu-Huan Hsu
Added CONFIG_SYSVIPC and CONFIG_SYSVIPC_SYSCTL into harmony and whistler GNU Linux configuration. Change-Id: I57db6adf55eecf5b5f7c141c00f1bedb97979d3d Reviewed-on: http://git-master/r/2532 Tested-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-06-11tegra: Move SOC-specific pinmux data to SOC-specific filesScott Williams
Change-Id: I9bb3607e9605eefd5c0eec07a8be3fafce9bae64 Reviewed-on: http://git-master/r/2528 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11sdhci: set MMC_CAP_MMC_HIGHSPEED for high-speed controllers.Pavan Kunapuli
Setting MMC_CAP_HIGHSPEED in host capabilites to detect high speed eMMC cards, set high speed mode and configure maximum supported clock frequency(52MHz). Tested on: AP20 Android with high speed eMMC card Change-Id: I0da6a4122a2caec1c70918b5801ddb5ac53dcbb5 Reviewed-on: http://git-master/r/2485 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] rename cortex_a9_save to tegra2_saveGary King
more of the code in this file is tegra power-state specific than common CPU save and restore routines, so rename it to reflect that it won't run on non-Tegra SoCs Change-Id: I22643da41309b48a7f85e62407ec8b7d9f75baff Reviewed-on: http://git-master/r/2244 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11tegra: gpio based keyboard driver for E1206 platform.Laxman Dewangan
Adding the gpio based keyboard driver support for the E1206 based platform. The gpio-key driver will get the platform data from odm. The odm will return gpio pin group information for E1206 based platfrom otherwise return NULL. The gpio pin information is converted to platform data which will be used by the gpio key driver. Change-Id: I9fd34f82abef86157a92aabcb01cc3ebe0059886 Reviewed-on: http://git-master/r/2420 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] suspend: add support for LP0 and LP1 suspend modesGary King
in both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely perform this transition, the final shutdown procedure responsible for * turning off the MMU and L1 data cache * putting memory into self-refresh * setting the DDR pads to the lowest power state * and turning off PLLs is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the start of the suspend process. in LP1 mode (like LP2), the CPU is reset and executes the code specified at the EVP reset vector. since SDRAM is in self-refresh, this code must also be located in IRAM, and it must re-enable DRAM before restoring the full context. in this implementation, it enables the CPU on PLLP, enables PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset vector to restore the rest of the system (MMU, PLLX, coresite, etc.). the LP2 reset vector is expected to be found in PMC_SCRATCH1, and is initialized during system-bootup in LP0 mode, the core voltage domain is also shutoff. as a result, all of the volatile state in the core voltage domain (e.g., pinmux registers, clock registers, etc.) must be saved to memory so that it can be restored after the system resumes. a limited set of wakeups are available from LP0, and the correct levels for the wakeups must be programmed into the PMC wakepad configuration register prior to system shutdown. on resume, the system resets into the boot ROM, and the boot ROM restores SDRAM and other system state using values saved during kernel initialization in the PMC scratch registers for simplicity, the outer cache is shutdown for both LP0 and LP1; it is possible to optimize the LP1 routine to bypass outer cache shutdown and restart v2 fixes from Vik Kasivajhula: * restore PLLC during LP1 resume * fix typo which set the CPU clock burst policy to PLLM, rather than PLLP Change-Id: Icb1d2cbcbac8503369a10d16fd5c8b561af5a35a Reviewed-on: http://git-master/r/1773 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] suspend: add scratch register mapping for tegra 2 LP0Gary King
to restore from LP0, a large number of memory, arbitration and PLL settings need to be preserved in scratch registers in the AO domain for the boot ROM to reload them after exiting LP0. Change-Id: Ic446ef47c3cba9b792dd7b86b176157757504bde Reviewed-on: http://git-master/r/2154 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM] outer_cache: add outer_restart callback and l2x0 implementationGary King
outer_restart should be called by platform suspend_ops to restore the outer cache to an active state following a power transition which disables or otherwise invalidates the outer cache state. Change-Id: I07a5268d1783fecd36491138e20913fca24a26d9 Reviewed-on: http://git-master/r/2243 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11framebuffer: tegra: fix compiler warningGary King
redefine an unsigned long variable as NvU32 to make gcc happy Change-Id: I4f949c9f812e5834f61899a57a8c4a957b571c62 Reviewed-on: http://git-master/r/2521 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] dma: don't save & restore the channel status registerGary King
CHAN_STA is the interrupt status register (write-to-clear), so preserving it across power transitions doesn't make a lot of sense Change-Id: Ibf4d6da17da5afbbde7572295207844cca63d38a Reviewed-on: http://git-master/r/2516 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM] harmony: enable CONFIG_GPIO_KEYSLaxman Dewangan
Enabling the gpio key config to enable the functionality of gpio based key driver for the E1206 based platform. Change-Id: I9296051993a8e93034cc3a90edf988a1df9a5925 Reviewed-on: http://git-master/r/2459 Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] aes: obfuscate cached keysKasoju Mallikarjun
- Clearing dma buffer after ECB operation - Removed acquisition / releasing of hardware lock in AesCoreEcbProcessBuffer. Change-Id: I942d1758ef08af2b3bd0c2d72207a90daeffba20 Reviewed-on: http://git-master/r/2416 Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11nvmap: tighten handle validation before pinningAnssi Kalliolahti
Added check for handle poison before pinning. This prevents panic (BUG_ON in _nvmap_handle_pin_locked) when trying to pin already freed handle. Bug 684375 Change-Id: I85ba4b37b2f193c19782edeaa562b7f77915cfc4 Reviewed-on: http://git-master/r/2478 Tested-by: Anssi Kalliolahti <akalliolahti@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] RM: speed up clock usage API.Alex Frid
Skipped spare clock h/w access when DVFS is running - it was not used, anyway, since all rates in this case are available in DVFS variables. Change-Id: Id324c7904e30ea8fe50b319cfd06c75a721b6b3f Reviewed-on: http://git-master/r/2458 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11tegra: disable_nonboot_cpus() requires CONFIG_PM_SLEEP_SMPScott Williams
Change-Id: I56e56dc8ad7d848be8363845dff5bd48a7e4fe38 Reviewed-on: http://git-master/r/2507 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11tegra: EHCI bus suspend/resume requires CONFIG_PMScott Williams
Change-Id: I86faa2f56dbfd0ed145f40b04346a85f64bab12c Reviewed-on: http://git-master/r/2508 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11tegra: Fix potential data abort if module doesn't existScott Williams
This is a port of change 1465 from android-tegra-2.6.29. Change-Id: Ibca32ecc0424fae28e4db04977722f7d7a6c6938 Reviewed-on: http://git-master/r/2502 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11tegra: Perform DSB immediately before WFIScott Williams
As per ARM recommendation, perform a DSB immediatly before a WFI. Change-Id: I8a94ca13c73e7a1d2d96712b0e29122a0b4c1618 Reviewed-on: http://git-master/r/2501 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11tegra: Avoid the use of literals in assembly codeScott Williams
Literals can be problematic in certain types of code. Avoid them by taking advantage of ARMv7 architecture features. This is a port of change 1255 from android-tegra-2.6.29. Change-Id: I728177cd940a9524feca6bc1de7353a98dfc1878 Reviewed-on: http://git-master/r/2495 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11[ARM/tegra] dma: set dma burst for slink based on transfer size.Laxman Dewangan
Setting the dma burst size for slink based on tarnsfer size. If transfer size is multiple of 16 bytes then set burst size as 4 word otherwise 1 word. For other dma requestor, the dma burst size is 1 word. Change-Id: I9c699b124c5f8f4c4b1fb3b916da5f235faa8704 Reviewed-on: http://git-master/r/2476 Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-11sdhci-tegra: always call sdhci_suspend_controller, use dev_pm_opsGary King
sdhci_suspend_controller should be called regardless of the type of media in the SD slot (SDIO or memory); rip out the code which conditionally suspended the host based on the card type additionally, move the suspend and resume functions out of platform_driver and into dev_pm_ops Change-Id: I7403aec8c26ef1c4374bb376f99b54767177504b Reviewed-on: http://git-master/r/2488 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11flusher: Fix PF_FROZEN raceOGAWA Hirofumi
To touch task->flags directly is racy. thaw_process() still has race (changing non_current->flags, but this is another issue) though, I think it's much better off. So, use thaw_process() instead. Signed-off-by: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> Signed-off-by: Jens Axboe <jens.axboe@oracle.com> Change-Id: Ifcd4aa521a7bb1f3b263ac4dbb3c483deb935ae8 Reviewed-on: http://git-master/r/2423 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-11fs: writeback: do not sync superblocks if bdi tasks are freezingGary King
during a system suspend operation without MMC_UNSAFE_RESUME, the mmc stack removes all of the cards on the bus so that they can be redetected during resume for data cards, the remove operation causes calls to sync the file systems on the mounted partitions however, since this happens during the device driver suspend path, tasks will already be frozen, including the bdi flusher task which are responsible for performing all of the queued operations to sync the removed card's file system. since the superblock sync is a blocking operation, this causes a deadlock, as the suspend operation is blocked on a frozen task this patch causes the fs-writeback code to skip the superblock sync if the bdi flusher tasks are freezing or already frozen, to prevent the deadlock Change-Id: I5970ac9a50f1968ba5f413a46be0c2e16222581c Reviewed-on: http://git-master/r/2373 Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-10[ARM/tegra] ODM: added PMU power off properties.Alex Frid
Added support for wake event delay, and CPU power off time controls. Exposed the respective settings as ODM PMU properties. Bug 690326. Change-Id: I2c30365de3fce4e2d45b1e66c7af9087f10d8451 Reviewed-on: http://git-master/r/2377 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-10[ARM/tegra] time: forced delay routine alignment.Alex Frid
Forced delay routine alignment - without it calibration results (BogoMIPS and loops_per_jiffy) may very depending on the code layout. Change-Id: I0abcacf947c6e451b72bdb4f2ec5fee160ad68b2 Reviewed-on: http://git-master/r/2455 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-10[arm] whistler: Add non-Android configuration fileYu-Huan Hsu
Added non-Android configuration for Tegra Whistler platform. Bug 694513 Bug 693422 Change-Id: I9696d1ce44bfd4195e1544ae90344a9afe6558c3 Reviewed-on: http://git-master/r/2435 Tested-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-06-10[arm] harmony: Added non-Android configuration fileWinnie Hsu
Added non-Android configuration for Tegra Harmony platform. Bug 694513 Bug 693422 Change-Id: I3eae367803868373ff9c0e10686f535aa8ee4151 Reviewed-on: http://git-master/r/2448 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-06-10[arm] harmony: Fixed compilation issue when CONFIG_USB_ANDROID is not set.Winnie Hsu
Change-Id: Ie08e1384cc8896ad23eac96e942cf54ae7792015 Reviewed-on: http://git-master/r/2444 Tested-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-06-10[ARM/tegra] RM: expanded CPU power off (LP2) policies.Alex Frid
Expanded CPU power off (LP2 state) policies as follows: (a) "Enter in Low Corner" - LP2 is entered and DVFS tick interrupt is masked only when DVFS is in low corner. (b) "Mask in Low Corner" - LP2 is entered independently of DVFS, but DVFS tick interrupt is masked only when low corner is hit (c) "Ignore Low Corner" - LP2 is entered and DVFS tick interrupt is masked independently of DVFS low corner. Ported from android-tegra-2.6.29, but set default policy to (c), which is the same as current android-tegra-2.6.32 kernel behavior (on 2.6.29 kernel (a) was default). Added sysfs node to change and evaluate policies. Change-Id: I22e89f4d58dfa2e2fb668154c1ae2cd301fbe1ca Reviewed-on: http://git-master/r/2359 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-10usb gadget: preventing reg access after phy is powered downAbhishek Aggarwal
The device was hanging on USB cable disconnect because fsl_ep_dequeue() function in fsl_udc_core.c was trying to access USB registers after the phy has been powered down. Fixed this by putting a check for vbus status and preventing the register access if the vbus status is 0. Bug: 696989 Change-Id: I802d6efa84b3cf20da736dfce1d546f044576b37 Reviewed-on: http://git-master/r/2394 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-10 tegra usb: Resume the device without re-enumerationSeshendra Gadagottu
When fast wakeup feature is supported by a host controller port, then avoid the restarting of controller. Fast wakeup is enabled on the port where device like usb modem is connected always. BUG 692574: Fast Wakeup for USB modems BUG 594395: Fast Wakeup Change-Id: Iaee9f184189f8a1aa8aa0e440879600c0eb625cc Reviewed-on: http://git-master/r/2375 Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09tegra nvrm: fixing access permission for nvrm.vdumpa
Bug 663469 nvrm is split into two nodes, /dev/knvrm and /dev/nvrm. /dev/nvrm has access to limited set of API's. Added validation of params in the API's that can be accessed from /dev/nvrm. Change-Id: I57c2aae000bf873fe85db00df66ec004c2882b5c Reviewed-on: http://git-master/r/2300 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com>
2010-06-09mmc: sdhci-tegra: set SDHCI_QUIRK_RUNTIME_DISABLEGary King
sd controllers in tegra socs should be disabled when idle to save power Change-Id: If1c20e43187356c94f4c5b846e3862e30834d842 Reviewed-on: http://git-master/r/2344 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09mmc: sdhci: add mmc_host_ops->enable and ->disableGary King
add support for the mmc delayed suspend interface to the sdhci driver, so that hosts which support it (controlled by a new quirk: SDHCI_QUIRK_RUNTIME_DISABLE) can use runtime delayed suspends to reduce the power consumption from idle SD controllers Change-Id: Iaa6a9dfad4cb9496caca715b5a7ce9e1b533d998 Reviewed-on: http://git-master/r/2343 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09[ARM]tegra:enable config USB_SUSPENDNarendra Damahe
Bug 696988 Change-Id: Id814b03c89d5cd48c6b779b55fdb7f5ee56f06f8 Reviewed-on: http://git-master/r/2347 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09tegra framebuffer - dsi one shot supportArthur Spence
DSI one shot support requires register access in the tegra framebuffer to poke the frame trigger bit (with both the trigger bit and the tearing effect signal are high, a frame of pixels will be sent to the panel). The boot args must also be expanded to have a "use tearing effect" flag. tegra RM: Expanded Display clock configuration options. Added an option for restricted Display clock synchronization with MIPI PLL - select MIPI PLL as a pixel clock source, but preserve PLL settings. To specify this option flag NvRmClockConfig_InternalClockForPads should be set by RM client along with NvRmClockConfig_MipiSync flag (in the absence of the former flag, MIPI PLL can be re-configured at RM discretion - current behavior). Change-Id: I495c2d76656efe8653aa5731c07180c2bfcd2fc0 Reviewed-on: http://git-master/r/2342 Tested-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09[ARM/tegra] move MC error interrupt out of NvRmGary King
MC error interrupts are useful debug features, so implement them separately from the RM; also, enhance the printouts to include the client name, so that cross-checking the status value against a separate list isn't necessary Change-Id: I9aa2857388bf252bbcd2f3048eae0fb63d90a011 Reviewed-on: http://git-master/r/2280 Tested-by: Gary King <gking@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-09usbnet: smsc9514: fix build break with USB_SUSPENDGary King
ccf5b801c changed uintf.pm_usage_cnt to an atomic_t; update this driver to reflect the change bug 696988 Change-Id: If587ca9c98a7f92f35a0143283c6d13a862c3d6e Reviewed-on: http://git-master/r/2336 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09[ARM/tegra] nvrm dma: remove err parameter from dma callbackGary King
Change-Id: I6ee6d3a6ce9defa25a30343932db309d05feb557 Reviewed-on: http://git-master/r/2289 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09serial: tegra_hsuart: Cleanups and bug fixesColin Cross
tegra_start_tx was called directly by the serial core, as well as from dma and serial interrupts to queue the next block of data. Separate out the "queue next data" functionality into tegra_start_next_tx. Also fixes TX PIO by adjusting FIFO sizes and prevents last characters from getting lost by spinning on TEMT before disabling clocks. Change-Id: If8ce15490f77dcbde48f1e64959d5c3f0ec35120 Signed-off-by: Colin Cross <ccross@android.com> Reviewed-on: http://git-master/r/2288 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09serial: tegra_hsuart: Fix DMA receive, drop err in dma callbacksColin Cross
Change-Id: I4c4bc12e8c883912f8979b75a8eb418a62e77f94 Signed-off-by: Colin Cross <ccross@android.com> Reviewed-on: http://git-master/r/2287 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09[ARM] tegra: dma: Drop err argument to dma callbacksColin Cross
Change-Id: I78359ccf3defc70e623735925d423cb048f68075 Signed-off-by: Colin Cross <ccross@android.com> Reviewed-on: http://git-master/r/2286 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-09[ARM] tegra: dma: Prevent double-queued requestsColin Cross
Change-Id: I08165ea202530bc65be9d418a889dd0622a3ac4f Signed-off-by: Colin Cross <ccross@android.com> Reviewed-on: http://git-master/r/2285 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-08[ARM/tegra] power: Added LP2 time logging.Alex Frid
Saved tegra idle LP2 time in PMC scratch register for DVFS logging. Change-Id: Ia7c4bf2168e7d9dacab36a7d000c930ee9a85650 Reviewed-on: http://git-master/r/2290 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-08ehci-tegra: do not request_mem_region for OTG controllerstegra-9.12.13.ERGary King
if the platform data indicates that the controller will be used in OTG mode, do not call request_mem_region since this would conflict with the gadget controller, causing one of the two probes to fail bug 696526 Change-Id: I64f71af8adf7ffa27e98e4fdb42d90de4203efde Reviewed-on: http://git-master/r/2298 Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-06-08[ARM/tegra] board-nvodm: fix sdio instance filteringGary King
a NULL pointer check for the ODM kit SDIO property was incorrectly entered as a check against the instance ID, which resulted in SDHCI instance 0 never being registered. bug 693414 Change-Id: I29b21d9d215ec1aeafd3d22a4468e0960c52621b Reviewed-on: http://git-master/r/2189 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-06-07USBNET:adding smsc power(suspend/resume)aware driverNarendra Damahe
Bug 693439 Change-Id: Id251d6be11e1b251c45e811173ba770683f11c48 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-15 15:40:19 +0000