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2010-03-21tegra usb: Switching of USB busy hints, when no active USB tranferstegra-9.12.8sgadagottu
are happening though a device connection on host port. Currently for harmony, an intergrated SMSC hub present on USB3. Because of this device connection is present on USB3 and USB power busy hints are always on. To avoid this, for host by default busy hints are off and USB busy hints will be on for : 1.Bulk and isochronus transfers 2.Interrupts transfers with buffer length >= 256. Busy hint will be on for pre-defined amount of time and after that busy hints will be off automatically. With this in idle state power is reduced. Tested on : Harmony Enumeartion is happening fine. LAN and USB HID devices are working fine Change-Id: Ifd653bebfb52c7702f7d24bf11ccf93e62ea0f66 Reviewed-on: http://git-master/r/915 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-19Tegra gpio: Wrapping up nvrm gpio to native gpio.Laxman Dewangan
NvRm Gpio driver will be wrapper on the native gpio driver such that it will provide the same existing api and implementation will be use the native gpio driver. In this approach, it does not need to change the existing gpio client driver. Tested on whistler with sdcard insert/remove, touch panel and scroll wheel. Tested on harmony with the suspend/resume. Change-Id: I2fa98f8f62a111a1463c1e5b1034e145eaae42a3 Reviewed-on: http://git-master/r/851 Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-19tegra pm: power aware nvrm_daemon kernel sideKaz Fukuoka
- Remove using signal. - fix bug 664864: unable to run LP1 - see also bug 642072: Power Aware NvRM Daemon Change-Id: I952b8aa0aa4ea0c4c289fa1d20fc0bae3a98cac7 Reviewed-on: http://git-master/r/914 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Kaz Fukuoka <kfukuoka@nvidia.com>
2010-03-19tegra RM: Separated EMC scaling floors per SDRAM type.Alex Frid
Separated EMC frequency low corners for LPDDR2 and DDR2. For now, kept both limits the same as common floor before (50MHz). Change-Id: Ieaa238f78ceb5a7f4f238ffe78c576bb7d5840b1 Reviewed-on: http://git-master/r/906 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-19tegra usb:Enable host based on the odm usb propertyVenkat Moganty
USB host is getting enabled when the odm usb property is set to None. During the system initialization host enable condition was not checked properly when Odm USB mode property is set to "NvOdmUsbModeType_None". Due to the wrong condition, host controller is turned on and consuming the power. Bug 665409: [whistler/android/power] - USB power consumption has increased Tested on AP20 whistler Change-Id: I47622e1da6ca2c9edd107df9b5e6de3953260f5c Reviewed-on: http://git-master/r/908 Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-18tegra usb: Integrating power aware LAN 9500 driver from SMSCNarendra Damahe
Integarting SMSC v1.01.06.03 (03/18/2010) LAN driver to tegra. This new version is a power aware driver and support suspend/resume functionality. Bug 635375 : [AP20 \ Android] SMSC Ethernet LAN(9514) 3rd Party driver power management in Android Tested on : Harmony Change-Id: I112a8d9805f3ce6fed45999130c7c8004865bb98 Change-Id: I112a8d9805f3ce6fed45999130c7c8004865bb98 Reviewed-on: http://git-master/r/884 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-18tegra pm: add suspend/resume to tegra-sdhci driverDeepesh Gujarathi
Implement suspend/resume functionality for the tegra-sdhci driver. Call the sdhci_suspend/resume functions which handles the power off and re-enumeration of sd memory cards. We ignore suspend/resume requests for all sdio devices asssuming that the individual drivers will manage their own power. For tegra devices, the wifi driver implements its own early suspend model and hence is ignored by the sdhci driver. Change-Id: I5041d314123bac958da7775ee24bd2dc1be55ab5 Change-Id: I5041d314123bac958da7775ee24bd2dc1be55ab5 Reviewed-on: http://git-master/r/852 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Rahul Bansal <rbansal@nvidia.com> Tested-by: Rahul Bansal <rbansal@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
2010-03-17tegra nvec: suspend/resume without nvec mouse connectedNinad Malwade
- when mouse is not present or connected to board, do not register the mouse driver with EC bus driver. - Bug 663803 Change-Id: Iec11af103c4ab00a9d01e66969fceb6161cec1e2 Reviewed-on: http://git-master/r/862 Reviewed-by: Ninad Malwade <nmalwade@nvidia.com> Tested-by: Ninad Malwade <nmalwade@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-17tegra usb: Device hangs after connecting devices to USB3sgadagottu
AP20 pop chip is not having USB3 ID pin. Currently both pop and non-pop whistler are using same odm query with Idpin type as "Cable Id". Since, it is not reflecting correct Id pin type for pop, causing the issue. With this change based on the board type, proper id pin type is returned as part of usb odm query for USB3. Without ID pin dynamic detection of devices is not possible, so host functionality is disabled for USB3 on pop boards. With this change USB3 host is working for non-pop modules and no hang is seen with pop modules. Bug 655520 : [AP20/Android/Whistler]: Device hangs after connecting USB devices(mouse/keyboard). Tested on : whistler E1109 and whistlerE1008 Change-Id: I5cd67c54756666e58cbc778da2b1015df27c14c6 Reviewed-on: http://git-master/r/795 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-17tegra regulator: Enable regulator for USB chargingVenkat Moganty
Enabling CONFIG_REGULATOR_TEGRA on whistler for USB charging support. Bug 631316 USB charging support in Android Tested on: whistler/Android Change-Id: If13169d7bb7321cf1b2806c80966e1050e39fed0 Reviewed-on: http://git-master/r/840 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-16tegra RM: Stabilized local timers input frequency.Alex Frid
Utilized local timers prescaler to keep input frequency at calibration (boot) level while CPU clock is scaled by DVFS. The local timer tick is lowered to 2.0MHz/1.5MHz on T20/AP20 (was 250MHz/187.5MHz respectively). Still it is better than 1MHz used as a base for jiffies counting. The LP2 dead time is not compensated by this commit, nevertheless it should address bug 660382 (no LP2 during video playback). Change-Id: I9fd0e1238afa4cf1b44339bf30c37a2a84e97ae9 Reviewed-on: http://git-master/r/865 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-16tegra power: implement early_suspend handler for display powerAntti Hatala
For proper power behavior Android expects the display to be turned off and on in the early_suspend stages instead of as a part of the actual suspend sequence. Add notifications for display on/off in the nvrm power notification interface, and call them at appropriate times. When CONFIG_HAS_EARLYSUSPEND is not defined, continue to notify nvrm_daemon in the power manager suspend/resume calls. Tabify & whitespace cleanup nvrm_user.c. Change-Id: Ie0129e0a5812352e97c95c4f323928d907782dee Reviewed-on: http://git-master/r/866 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-12gpio: using proper API for getting the irq dataLaxman Dewangan
To get the ird data for the gpio pin irq, it should use the get_irq_chip_data() in place of get_irq_data(). This is because at the time of registration, the irq data is added as the chip irq data. Tested on whistler. Change-Id: Ic80d0f05fa5490ee2ca876a750daa27135e681c9 Reviewed-on: http://git-master/r/849 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-12nvmap: add barriers around atomic_read and atomic_setGary King
add SMP memory barriers before atomic_read and after atomic_set to ensure that any changes to the values are properly flushed so that they are visible to all processors in the system, since neither operator guarantees atomicity. change the poison flag to be a non-zero value, so that zero-filled memory isn't improperly detected as a valid handle. re-enable error prints for pinning & unpinning handles with no local references, now that the performance regression-causing misuse in the codec firmware is resolved. Change-Id: Ibbf5f0ad48f83f5eb475afb6dec8633adba8e3ca Reviewed-on: http://git-master/r/844 Reviewed-by: Antti Hatala <ahatala@nvidia.com> Tested-by: Antti Hatala <ahatala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-12tegra clock: Cleanup of reset codeVenkat Moganty
Removed the code that brings all controllers out of reset. Change-Id: I1c4934bd5ff08f305806c6bfc74fddb9f6d6da6a Reviewed-on: http://git-master/r/835 Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-12tegra power: simplify lp2, enable for non-wakelock buildsGary King
since the target lp2 time is being computed directly from the OS timer list, it can be used computed immediately prior to entering lp2. previously, it was computed by a previous invocation of the idle loop and stored in a static variable; which was clearly wrong since, after the calculation, the idle loop would wfi. move all of the lp2 logic out of the CONFIG_WAKELOCK block; the only information wakelocks provide is an additional hint as to whether or not entering lp2 is allowed, so this can be checked at the top of the idle loop and non-wakelock dependent code can handle the actual entry into LP2. partial fix for bug 660382 Change-Id: I397c8dbc946cb3495e9b9b247d11eae782503623 Reviewed-on: http://git-master/r/846 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-11tegra touch: enable multi-touchVarun Wadekar
adding multi-touch support to the touch screen driver. Tested with Gallery3D, Multitouch Visualizer and Multitouch Visualise test apps. Fod Bug 653317 Change-Id: I2976ab91c06a54de4772d88c3d96d72a753205ed Reviewed-on: http://git-master/r/834 Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-11serial: delete tegra DDK serial driverGary King
this driver is no longer being used, and its continued existence just causes confusion. Change-Id: Ia5b4a350b6590bbd0e8914625e9e81951096fb8c Reviewed-on: http://git-master/r/843 Reviewed-by: John Davis <jodavis@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-11tegra: Tristating the unsed pin groups in VDDIO_NAND rail.Suresh Mangipudi
The power numbers were high on the VDDIO_NAND rail, when the Nand module was not present in EMMC boot. Doing a Pullup of the unused pin groups and tristating the pad groups in the VDDIO_NAND rail, brings down the power from 9mW to 2mW. Bug 630271 Tested Nand and EMMC boot up on whistler. Change-Id: I98ac3c0ae237093b0f17552799e0beb956c735e9 Reviewed-on: http://git-master/r/822 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-11Export NvULowestBitSet and NvOsGetProcessInfo.Acorn Pooley
pre-existing NvULowestBitSet must be exported for upcoming channel-in-kernel change NvOsGetProcessInfo is useful for debugging. Implemented and exported. Change-Id: I9265626bc4496589a71c6b3517af44d8571a2c2e Reviewed-on: http://git-master/r/828 Reviewed-by: Acorn Pooley <apooley@nvidia.com> Tested-by: Acorn Pooley <apooley@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-11tegra ODM: Moving the board specific USB trimmer values to odm_query.Steve Lin
The usb ddk will use these trimmer values if they are specified in the NvOdmUsbProperty. Otherwise, it will use the default values specified inside NvDDK. Bug 657479: USB trimmer values should not be hardcoded in the DDK Change-Id: Idd819dc6faba63831ba5164c6c2ebd1a99567a1c Reviewed-on: http://git-master/r/786 Tested-by: Szming Lin <stlin@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-11tegra RM: Minimized DRAM IO pad power in LP1.Alex Frid
Configured minimal power DRAM IO setting on entry to LP1, and restored run-time settings on exit (bug 660887). Code clean up. Change-Id: I1586faa497a4374741688318a88d99dc6b8717e2 Reviewed-on: http://git-master/r/836 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-10KGDB: add smp_mb() in synchronisation during exception handler exitWill Deacon
KGDB uses atomic variables and busy-wait loops to co-ordinate between multiple CPUs on an SMP system. When an exception is handled, the primary CPU executes kgdb_handle_exception() whilst the others execute kgdb_wait. There comes a point when the waiters are waiting for the primary CPU to finish: /* Wait till primary CPU is done with debugging */ (1) while (atomic_read(&passive_cpu_wait[cpu])) cpu_relax(); /* Do important KGDB stuff */ /* Signal the primary CPU that we are done: */ atomic_set(&cpu_in_kgdb[cpu], 0); In parallel to this, the primary CPU is doing: for (i = NR_CPUS-1; i >= 0; i--) atomic_set(&passive_cpu_wait[i], 0); /* * Wait till all the CPUs have quit * from the debugger. */ for_each_online_cpu(i) { (1) while (atomic_read(&cpu_in_kgdb[i])) cpu_relax(); } There is a potential deadlock situation at point (1) because the previous writes to the passive_cpu_wait variables by the primary CPU may not yet be visible to the other CPUs [for instance, they may be sitting in the local store buffer]. This means that the waiter CPUs will never exit the while loop and therefore never write to the cpu_in_kgdb variables, which the primary CPU is blocked on. Furthermore, because the primary CPU is aggressively performing reads, the store buffer may not necessarily drain so the system will deadlock. This deadlock has been experienced on a quad-core ARM11MPCore platform. The following patch addresses the issue by adding a memory barrier to the primary CPU before the polling loop, therefore forcing the previous atomic_sets to be visible before waiting for the waiters to finish. Cc: KGDB Mailing List <kgdb-bugreport@lists.sourceforge.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Will Deacon <will.deacon@arm.com> Change-Id: I93a294896342ca0fd2df86c68d9f8790eec0576c Reviewed-on: http://git-master/r/829 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-10tegra RM: Fixed CPU PowerGood timer settings.Alex Frid
Loaded CPU PowerGood timer on entry to LP1 with count value for 32kHz system bus clock. Restored original count (which was set by DVFS at run time) on LP1 exit. Reduced margin of DVFS PowerGood calculations. Change-Id: I7f61c568dd6c81edea12b9965f7758d9bd496798 Reviewed-on: http://git-master/r/819 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-09tegra pcie: fix support for simultaneous root portsJeremy Alves
eliminate overlapping memory ranges for the root ports reduce config accesses Change-Id: I9eb2af226a88bcd27ee445ddee01c18663fe4449 Reviewed-on: http://git-master/r/762 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-09tegra serial: Tx Path OptimizationsAnantha Idapalapati
Based on profiling, observed UART Tx to be mostly waiting for a previous DMA to be finished so that it can proceed for further processing of data from upper layers. Two Mmodifications are implemented as part of this commit 1. Forming a DMA request for smaller transfers and waiting for DMA request to be finished introduced overhead. Implemented a polling based transfers for transfers less than a certain limit. 2. Implemented a parallel activity between "DMA Buffer -> UART FIFO" and "Application -> DMA Buffer" copies. introduced a new DMA Buffer which can be made ready by the time DMA finishes use of another DMA Buffer that was filled by Driver. Bug ID: 652334 Change-Id: I30cad291553f9c0c67cb95afa67e468446f7ffd7 Reviewed-on: http://git-master/r/743 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-09tegra gpio: Implementing the native gpio driver.Laxman Dewangan
Adding the native driver for the gpio which support the gpio chiplib for the kernel and user space gpio client. Tested on whister with the touch panel and scroll wheel. Tested with the lp1 entry exit multiple times on harmony. Change-Id: I2f0f9b8ac9ef4fa2ed35c084a713edd42f732c89 Reviewed-on: http://git-master/r/711 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: John Davis <jodavis@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-09Tegra RM: Fixed MIPI PLL power rail control.Alex Frid
Fixed MIPI PLL power rail control that was missed by CL 5598660. (transparent for Whistler/Harmony where MIPI PLL rail is combined with other always On PLLs). Change-Id: Ic2e86df28e05dcd66d6b45f435bed882cf8ee7b4 Reviewed-on: http://git-master/r/811 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-09tegra power: Properly obtain start/end lp2 times.tkasivajhula
The lp2 times are used to calculate dfs duty cycle via dfs_log. Correct lp2 times are also needed to properly modify the jiffy values. Change-Id: I2c5c14cbe853276356c5422ae24e3a7ca07b52df Reviewed-on: http://git-master/r/759 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-09tegra: tegra_pm_notifier() notifier requires CONFIG_PMScott Williams
If CONFIG_PM is not selected, don't compile tegra notifier code. Change-Id: I24f7bd5c889db8b20c73815940a8f4af9a8522b3 Reviewed-on: http://git-master/r/806 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-08Tegra RM: Removed 50MHz floor for MIPI PLL output.tegra-9.12.7Alex Frid
Removed 50MHz floor for MIPI PLL high speed output frequency. This floor kept MIPI PLL low speed output (= high speed output / 8) above DSI panel specification - bug 651446. Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a Reviewed-on: http://git-master/r/787 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
2010-03-08[nvmap] fix strided read/write loop incrementGary King
in the process of cleaning up the implementation of do_rw so that it could be called from both ioctl and kernel contexts, the loop increment for source and distination addresses was erroneously set to the element size, rather than the provided strides. bug 660448 Change-Id: I02e2b2b980f90a2171d811192b667883f2a3ab41 Reviewed-on: http://git-master/r/805 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-08tegra uart: Make device id equal to instance idRama Kandhala
Changed the registration to use the device ID same as instance. With this change instance 0 will show up as ttyHS0 and instance 1 will show up as ttyHS1 and so on. Before this change, if the instance 0 was not used on a platform, instance 1 would have showed up as ttyHS0. Bug 656451 Tested with Harmony. Made sure that all nodes showup in the device list except the missing instance. Change-Id: Ib4e04b12f16002deb899b38630de102c24e588b0 Reviewed-on: http://git-master/r/735 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-08tegra: Commenting the error prints for memory pin/Unpin functionsNinad Malwade
- On behalf of Gautam Moharir - Bug 660462 Change-Id: I66e22e247ce5df6135f31c75ae91ec5d0b11e666 Reviewed-on: http://git-master/r/792 Reviewed-by: Ninad Malwade <nmalwade@nvidia.com> Tested-by: Ninad Malwade <nmalwade@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-05[arm] implement TLS register workaround for Tegra errata 657451Gary King
tegra 2 systems have a hardware errata which causes bit 20 of the TLS register (CP15 c13, operations 2-4) to be unreliable. in common user space threading libraries (glibc pthreads, bionic pthreads), the value stored in this register is guaranteed to be at least word-aligned, leaving bit 0 free. the work-around for this hardware errata is storing bit 20 of the user space-provided TLS value into bit 0 of the register inside __set_tls, and restoring it in the get_tls helper. Change-Id: I06439378edc01dc897708e3298cd91b5721c6e50 Reviewed-on: http://git-master/r/779 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-05[tegra iovmm] implement stubs for no-iovmm caseGary King
nvmap build fails when CONFIG_TEGRA_IOVMM is not selected. add stubs to allow that combination to work. Change-Id: Ie7e47a987feaeffd987996d11a594b2c8551311e Reviewed-on: http://git-master/r/785 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-05Tegra pm:disable pllp pll during system suspend. other code cleanupNarendra Damahe
Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Reviewed-on: http://git-master/r/750 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-05tegra-nvodm-touch: Remove unneed condition check width[0] == 0xfHoang Pham
This condition check width[0] == 0xf is not need based on spec and it is causing second finger samples are ignored many times. Fixes bug 653317 Change-Id: I2ada2732f0c4965817a0ed1dca1b6351e01d256a Reviewed-on: http://git-master/r/769 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2010-03-05tegra: EHCI bus suspend/resume requires CONFIG_PMScott Williams
If CONFIG_PM is not selected, don't compile EHCI bus suspend/resume. Change-Id: Ia89612fa3d82dc671accc597e4d1ca05f56eaa5c Reviewed-on: http://git-master/r/783 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-05[nvmap] handle NULL return for pin multiple, fix infinite loopGary King
the handle alignment parameter query had an off-by-one bug in its loop initializer which caused any carveout handle to trigger an infinite loop. the only caller of this API was the debug EGL driver, which used it to verify that the allocation matched the requested alignment. also, if the user passes NULL as the address array when pinning multiple handles to ioctl_pinop, pin the handles and skip the output write, rather than returning a permission error. big thanks to antti for finding the infinite loop. bug 660526 Change-Id: I90f819a231b5a8bef5b473252122cdbefc744efb Reviewed-on: http://git-master/r/782 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-04tegra ODM: Added new Whistler PMU revision support.Alex Frid
Added support for the new Whistler PMU revision that preserves CPU voltage across LP2 (it will allow to enable core voltage scaling on E1109 processor boards). Change-Id: I0724414c5148f39b3c6fa4f0d3f84963231d2520 Reviewed-on: http://git-master/r/726 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-04[usb mass storage] return -EINVAL on NULL requestGary King
there appears to be a race condition which causes req to be NULL. issue a warning and return -EINVAL in this case, rather than dereferencing a NULL pointer Change-Id: I46d7fdd63ec6fb09bdda18e1a1e5509af079beab Reviewed-on: http://git-master/r/768 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-04tegra usb: Save/Restore context for dedicated host mode only.sgadagottu
Save/Restore context works only for dedicated host. Earlier it was enabled even for OTG. This is corrected by modifying the check in nvddk_usbphy.c. Checking for host mode instead of "IsHostMode" flag. Bug 658225: USB host is not working on android/whistler USB port1 in OTG mode. Tested on : Whistler USB1 OTG + USB3 host Now OTG host is getting detected Change-Id: Ia5a1e0744074a6486d8853ea10f6c860b3abb4f3 Reviewed-on: http://git-master/r/741 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-03-04nvmap: implement nvmap as a full memory manager driverGary King
previously, the task of managing RM-managed memory handles was split between nvos (OS page allocation), the RM (heap management for carveout & IRAM heaps, and handle life-time management), nvreftrack (abnormal process termination) and nvmap (user-space read/write/map of memory handles). this resulted in an opaque system that was wasteful of kernel virtual address space, didn't support CPU cache attributes for kernel mappings and couldn't fully unwind leaked handles (e.g., if the application leaked a pinned handle the memory might never be reclaimed). nvmap is now a full re-implementation of the RM memory manager, unifying all of the functionality from nvreftrack, nvos, nvmap and nvrm into one driver used by both user and kernel-space clients. add configs to control paranoid operation. when paranoid is enabled, every handle reference passed into the kernel is verified to actually have been created by nvmap; furthermore, handles which are not global (the GET_ID ioctl has not been called for it) will fail validation if they are referenced by any process other than the one which created them, or a super-user process (opened via /dev/knvmap). each file descriptor maintains its own table of nvmap_handle_ref references, so the handle value returned to each process is unique; furthermore, nvmap_handle_ref objects track how many times they have been pinned, to ensure that processes which abnormally terminate with pinned handles can be unwound correctly. as a compile-time option, fully-unpinned handles which require IOVMM mappings may be stored in a segmented (by size) MRU (most-recently unpinned) eviction cache; if IOVMM space is over-committed across multiple processes, a pin operation may reclaim any or all of the IOVMM areas in the MRU cache. MRU is used as the eviction policy since graphics operations frequently operate cyclically, and the least-recently used entry may be needed almost immediately if the higher-level client starts (e.g.) rendering the next frame. introduce a concept of "secure" handles. secure handles may only be mapped into IOVMM space, and when unpinned their mapping in IOVMM space will be zapped immediately, to prevent malicious processes from being able to access the handle. expose carveout heap attributes for each carveout heap in sysfs, under the nvmap device with sub-device name heap-<heap name> * total size * free size * total block count * free block count * largest block * largest free block * base address * name * heap usage bitmask carveout heaps may be split at run-time, if sufficient memory is available in the heap. the split heap can be (should be) assigned a different name and usage bitmask than the original heap. this allows a large initial carveout to be split into smaller carveouts, to reserve sections of carveout memory for specific usages (e.g., camera and/or video clients). add a split entry in the sysfs tree for each carveout heap, to support run-time splitting of carveout heaps into reserved regions. format is: <size>,<usage>,<name> * size should be parsable with memparse (suffixes k/K and m/M are legal) * usage is the new heap's usage bitmask * name is the name of the new heap (must be unique) carveout heaps are managed using a first-fit allocator with an explicit free list, all blocks are kept in a dynamically-sized array (doubles in size every time all blocks are exhausted); to reduce fragmentation caused by allocations with different alignment requirements, the allocator will compare left-justifying and right-justifying the allocation within the first-fit block, and choose the justification that results in the largest remaining free block (this is particularly important for 1M-aligned split heaps). other code which duplicated functionality subsumed by this changelist (RM memory manager, NvOs carveout command line parser, etc.) is deleted; implementations of the RM memory manager on top of nvmap are provided to support backwards compatibility bug 634812 Change-Id: Ic89d83fed31b4cadc68653d0e825c368b9c92f81 Reviewed-on: http://git-master/r/590 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-04tegra init: register iovmm deviceGary King
register the GART (for harmony & whistler) with IOVMM, to instantiate the IOVMM device node. Change-Id: I0d8eba7fd056e2c2db979abbc3ddd0bb650d4312 Reviewed-on: http://git-master/r/446 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-03nvodm_battery:Correcting the sizeof when NvOdmOsMemsetSachin Nikam
The sizeof parameter provided to NvOdmOsMemset() was having the wrong value. It can create unpredictable results if NvEcOpen() fails. Change-Id: I19a6adabc1b8d780160a017df7b3fb03ac8c8a60 Reviewed-on: http://git-master/r/760 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-03tegra ODM: Adding new GUID for EMP M570 modem and GUID filterSteve Lin
Adding new GUID for EMP M570 ULPI modem and the GUID filter in nvodm_query_discovery. The GUID will be filtered out according to the RIL option in odmdata. Change-Id: I6bb2093e35d89c7945c82829f0283cf5a36b804a Reviewed-on: http://git-master/r/713 Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-03nvec_battery:Adding a new sysfs attribute "status_poll_period"Sachin Nikam
The default Battery status poll period is 30 Sec. Adding a new sysfs attribute by which this polling period can be modified. To view the polling period:- cat /sys/devices/nvec/nvec_battery/status_poll_period To modify polling period:- echo <newvalue> > /sys/devices/nvec/nvec_battery/status_poll_period bug 646822 Synopsis:[Harmony/android] Battery status is not updated whenever there is any change in battery/power supply property Change-Id:I3b17be7f01fcf91f1c268fdb36fe348ddcf5f626 Reviewed-on: http://git-master/r/742 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-03tegra usb: Making USB busy hints off on resume, when there is no adbsgadagottu
cable/usb device connection Currently on resume from LP1, though there is no adb cable/USB device connected to USB1/USB3 then also usb busy hints are getting on. With this change on resume: For gadget driver, if cable is not connected then busy hints made off. For host driver, if device(s) are not connected then busy hints are off. Code Clean-up for power improvement Tested on : Whistler board USB1 OTG + USB3 host Tested with all possible connection on USB1 and USB3 Change-Id: I6d210bba1264d9c0134d586d3f67ff609ba2b3fe Reviewed-on: http://git-master/r/745 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-03-02Proper fix for commit I5c6914ef8906eed80cba15249b0760d71e3d0255Venkata(Muni) Anda
csd_struct version on some of the cards is 4.4 cards is 3. This change skips the check for that verison. Change-Id: Ib44344237c99e1a52e1b3eb864e96194b090929b Reviewed-on: http://git-master/r/739 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-07 03:12:46 +0000